From: "Rob Herring (Arm)" <robh@kernel.org>
To: Conor Dooley <conor@kernel.org>
Cc: linux-clk@vger.kernel.org,
Claudiu Beznea <claudiu.beznea@tuxon.dev>,
devicetree@vger.kernel.org,
Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>,
Conor Dooley <conor.dooley@microchip.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Daire McNamara <daire.mcnamara@microchip.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>
Subject: Re: [PATCH v1 2/3] dt-bindings: clock: mpfs-ccc: Add pic64gx compatibility
Date: Mon, 17 Nov 2025 15:48:08 -0600 [thread overview]
Message-ID: <176341608757.773703.18386473879112962175.robh@kernel.org> (raw)
In-Reply-To: <20251117-mocha-shelter-4d9aa88e34b5@spud>
On Mon, 17 Nov 2025 15:35:19 +0000, Conor Dooley wrote:
> From: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
>
> pic64gx SoC Clock Conditioning Circuitry is compatibles
> with the Polarfire SoC
>
> Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../devicetree/bindings/clock/microchip,mpfs-ccc.yaml | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
next prev parent reply other threads:[~2025-11-17 21:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-17 15:35 [PATCH v1 0/3] pic64gx clk kconfig/binding changes Conor Dooley
2025-11-17 15:35 ` [PATCH v1 1/3] clk: microchip: drop POLARFIRE from ARCH_MICROCHIP_POLARFIRE Conor Dooley
2025-12-06 11:11 ` Claudiu Beznea
2025-11-17 15:35 ` [PATCH v1 2/3] dt-bindings: clock: mpfs-ccc: Add pic64gx compatibility Conor Dooley
2025-11-17 21:48 ` Rob Herring (Arm) [this message]
2025-11-17 15:35 ` [PATCH v1 3/3] dt-bindings: clock: mpfs-clkcfg: " Conor Dooley
2025-11-17 17:42 ` Rob Herring (Arm)
2025-11-17 17:48 ` Conor Dooley
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