From: Chuan Liu <chuan.liu@amlogic.com>
To: Jerome Brunet <jbrunet@baylibre.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 23/26] clk: amlogic: use the common pclk definition
Date: Thu, 3 Jul 2025 15:16:36 +0800 [thread overview]
Message-ID: <1fcf7e52-b265-4341-a360-93aaf293f131@amlogic.com> (raw)
In-Reply-To: <20250702-meson-clk-cleanup-24-v1-23-e163c9a1fc21@baylibre.com>
Hi Jerome:
On 7/2/2025 11:26 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> Replace marcros defining pclks with the common one, reducing code
> duplication.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
> drivers/clk/meson/axg-aoclk.c | 35 +++++++++-----------------
> drivers/clk/meson/c3-peripherals.c | 34 +++++++-------------------
> drivers/clk/meson/g12a-aoclk.c | 50 +++++++++++++++-----------------------
> drivers/clk/meson/gxbb-aoclk.c | 33 +++++++++----------------
> 4 files changed, 51 insertions(+), 101 deletions(-)
>
> diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
> index 74c2f51424f11cc04a80a3a4918e4de0a5d11d08..902fbd34039cc06d512f1237a1e5d9050fd00b4b 100644
> --- a/drivers/clk/meson/axg-aoclk.c
> +++ b/drivers/clk/meson/axg-aoclk.c
> @@ -34,30 +34,19 @@
> #define AO_RTC_ALT_CLK_CNTL0 0x94
> #define AO_RTC_ALT_CLK_CNTL1 0x98
>
> -#define AXG_AO_GATE(_name, _bit, _flags) \
> -static struct clk_regmap axg_ao_##_name = { \
> - .data = &(struct clk_regmap_gate_data) { \
> - .offset = (AO_RTI_GEN_CNTL_REG0), \
> - .bit_idx = (_bit), \
> - }, \
> - .hw.init = &(struct clk_init_data) { \
> - .name = "axg_ao_" #_name, \
> - .ops = &clk_regmap_gate_ops, \
> - .parent_data = &(const struct clk_parent_data) { \
> - .fw_name = "mpeg-clk", \
> - }, \
> - .num_parents = 1, \
> - .flags = (_flags), \
> - }, \
> -}
> +static const struct clk_parent_data axg_ao_pclk_parents = { .fw_name = "mpeg-clk" };
>
> -AXG_AO_GATE(remote, 0, CLK_IGNORE_UNUSED);
> -AXG_AO_GATE(i2c_master, 1, CLK_IGNORE_UNUSED);
> -AXG_AO_GATE(i2c_slave, 2, CLK_IGNORE_UNUSED);
> -AXG_AO_GATE(uart1, 3, CLK_IGNORE_UNUSED);
> -AXG_AO_GATE(uart2, 5, CLK_IGNORE_UNUSED);
> -AXG_AO_GATE(ir_blaster, 6, CLK_IGNORE_UNUSED);
> -AXG_AO_GATE(saradc, 7, CLK_IGNORE_UNUSED);
> +#define AXG_AO_GATE(_name, _bit, _flags) \
> + MESON_PCLK(axg_ao_##_name, AO_RTI_GEN_CNTL_REG0, _bit, \
> + &axg_ao_pclk_parents, _flags)
> +
> +static AXG_AO_GATE(remote, 0, CLK_IGNORE_UNUSED);
> +static AXG_AO_GATE(i2c_master, 1, CLK_IGNORE_UNUSED);
> +static AXG_AO_GATE(i2c_slave, 2, CLK_IGNORE_UNUSED);
> +static AXG_AO_GATE(uart1, 3, CLK_IGNORE_UNUSED);
> +static AXG_AO_GATE(uart2, 5, CLK_IGNORE_UNUSED);
> +static AXG_AO_GATE(ir_blaster, 6, CLK_IGNORE_UNUSED);
> +static AXG_AO_GATE(saradc, 7, CLK_IGNORE_UNUSED);
>
> static struct clk_regmap axg_ao_cts_oscin = {
> .data = &(struct clk_regmap_gate_data){
> diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peripherals.c
> index e9c1ef99be13d0542b8a972ceffe69c8a9977118..02c9820cd98655e57a290859b595cf09d39e5fe3 100644
> --- a/drivers/clk/meson/c3-peripherals.c
> +++ b/drivers/clk/meson/c3-peripherals.c
> @@ -164,30 +164,13 @@ static struct clk_regmap c3_rtc_clk = {
> },
> };
>
> -#define C3_PCLK(_name, _reg, _bit, _fw_name, _ops, _flags) \
> -struct clk_regmap c3_##_name = { \
> - .data = &(struct clk_regmap_gate_data){ \
> - .offset = (_reg), \
> - .bit_idx = (_bit), \
> - }, \
> - .hw.init = &(struct clk_init_data) { \
> - .name = "c3_" #_name, \
> - .ops = _ops, \
> - .parent_data = &(const struct clk_parent_data) { \
> - .fw_name = (_fw_name), \
> - }, \
> - .num_parents = 1, \
> - .flags = (_flags), \
> - }, \
> -}
> +static const struct clk_parent_data c3_sys_pclk_parents = { .fw_name = "sysclk" };
>
> -#define C3_SYS_PCLK(_name, _reg, _bit, _flags) \
> - C3_PCLK(_name, _reg, _bit, "sysclk", \
> - &clk_regmap_gate_ops, _flags)
> +#define C3_SYS_PCLK(_name, _reg, _bit, _flags) \
> + MESON_PCLK(c3_##_name, _reg, _bit, &c3_sys_pclk_parents, _flags)
>
> -#define C3_SYS_PCLK_RO(_name, _reg, _bit) \
> - C3_PCLK(_name, _reg, _bit, "sysclk", \
> - &clk_regmap_gate_ro_ops, 0)
> +#define C3_SYS_PCLK_RO(_name, _reg, _bit) \
> + MESON_PCLK_RO(c3_##_name, _reg, _bit, &c3_sys_pclk_parents, 0)
Adding 'SoC' prefix to clock names appears redundant and inconsistent - only
'sys_clk' carries this prefix while all other clock names don't.
>
> static C3_SYS_PCLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0);
> static C3_SYS_PCLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0);
> @@ -290,9 +273,10 @@ static C3_SYS_PCLK(sys_vc9000e, SYS_CLK_EN0_REG2, 2, 0);
> static C3_SYS_PCLK(sys_pwm_mn, SYS_CLK_EN0_REG2, 3, 0);
> static C3_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG2, 4, 0);
>
> -#define C3_AXI_PCLK(_name, _reg, _bit, _flags) \
> - C3_PCLK(_name, _reg, _bit, "axiclk", \
> - &clk_regmap_gate_ops, _flags)
> +static const struct clk_parent_data c3_axi_pclk_parents = { .fw_name = "axiclk" };
> +
> +#define C3_AXI_PCLK(_name, _reg, _bit, _flags) \
> + MESON_PCLK(c3_##_name, _reg, _bit, &c3_axi_pclk_parents, _flags)
>
> /*
> * NOTE: axi_sys_nic provides the clock to the AXI bus of the system NIC. After
> diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c
> index 45e4df393feb6f916b6e035ad71e379e6e30ee99..96981da271fa1453ebbe433e36cff4409661fa6a 100644
> --- a/drivers/clk/meson/g12a-aoclk.c
> +++ b/drivers/clk/meson/g12a-aoclk.c
> @@ -37,22 +37,10 @@
> #define AO_RTC_ALT_CLK_CNTL0 0x94
> #define AO_RTC_ALT_CLK_CNTL1 0x98
>
> -#define G12A_AO_PCLK(_name, _reg, _bit, _flags) \
> -static struct clk_regmap g12a_ao_##_name = { \
> - .data = &(struct clk_regmap_gate_data) { \
> - .offset = (_reg), \
> - .bit_idx = (_bit), \
> - }, \
> - .hw.init = &(struct clk_init_data) { \
> - .name = "g12a_ao_" #_name, \
> - .ops = &clk_regmap_gate_ops, \
> - .parent_data = &(const struct clk_parent_data) { \
> - .fw_name = "mpeg-clk", \
> - }, \
> - .num_parents = 1, \
> - .flags = (_flags), \
> - }, \
> -}
> +static const struct clk_parent_data g12a_ao_pclk_parents = { .fw_name = "mpeg-clk" };
> +
> +#define G12A_AO_PCLK(_name, _reg, _bit, _flags) \
> + MESON_PCLK(g12a_ao_##_name, _reg, _bit, &g12a_ao_pclk_parents, _flags)
>
> /*
> * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons
> @@ -63,22 +51,22 @@ static struct clk_regmap g12a_ao_##_name = { \
> * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable
> * for a particular clock.
> */
> -G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0, CLK_IGNORE_UNUSED);
> -G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1, CLK_IGNORE_UNUSED);
> -G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2, CLK_IGNORE_UNUSED);
> -G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3, CLK_IGNORE_UNUSED);
> -G12A_AO_PCLK(uart, AO_CLK_GATE0, 4, CLK_IGNORE_UNUSED);
> -G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5, CLK_IGNORE_UNUSED);
> -G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6, CLK_IGNORE_UNUSED);
> -G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7, CLK_IGNORE_UNUSED);
> -G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(uart, AO_CLK_GATE0, 4, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8, CLK_IGNORE_UNUSED);
>
> -G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0, CLK_IGNORE_UNUSED);
> -G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1, CLK_IGNORE_UNUSED);
> -G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2, CLK_IGNORE_UNUSED);
> -G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3, CLK_IGNORE_UNUSED);
> -G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4, CLK_IGNORE_UNUSED);
> -G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4, CLK_IGNORE_UNUSED);
> +static G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5, CLK_IGNORE_UNUSED);
>
> static struct clk_regmap g12a_ao_cts_oscin = {
> .data = &(struct clk_regmap_gate_data){
> diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
> index 2bf45fd7fe4ba0783e736fbbb126209870985b22..c7dfb3a06cb5f70c98f65bb91b937e1b870b34fe 100644
> --- a/drivers/clk/meson/gxbb-aoclk.c
> +++ b/drivers/clk/meson/gxbb-aoclk.c
> @@ -23,29 +23,18 @@
> #define AO_RTC_ALT_CLK_CNTL0 0x94
> #define AO_RTC_ALT_CLK_CNTL1 0x98
>
> -#define GXBB_AO_PCLK(_name, _bit, _flags) \
> -static struct clk_regmap gxbb_ao_##_name = { \
> - .data = &(struct clk_regmap_gate_data) { \
> - .offset = AO_RTI_GEN_CNTL_REG0, \
> - .bit_idx = (_bit), \
> - }, \
> - .hw.init = &(struct clk_init_data) { \
> - .name = "gxbb_ao_" #_name, \
> - .ops = &clk_regmap_gate_ops, \
> - .parent_data = &(const struct clk_parent_data) { \
> - .fw_name = "mpeg-clk", \
> - }, \
> - .num_parents = 1, \
> - .flags = (_flags), \
> - }, \
> -}
> +static const struct clk_parent_data gxbb_ao_pclk_parents = { .fw_name = "mpeg-clk" };
>
> -GXBB_AO_PCLK(remote, 0, CLK_IGNORE_UNUSED);
> -GXBB_AO_PCLK(i2c_master, 1, CLK_IGNORE_UNUSED);
> -GXBB_AO_PCLK(i2c_slave, 2, CLK_IGNORE_UNUSED);
> -GXBB_AO_PCLK(uart1, 3, CLK_IGNORE_UNUSED);
> -GXBB_AO_PCLK(uart2, 5, CLK_IGNORE_UNUSED);
> -GXBB_AO_PCLK(ir_blaster, 6, CLK_IGNORE_UNUSED);
> +#define GXBB_AO_PCLK(_name, _bit, _flags) \
> + MESON_PCLK(gxbb_ao_##_name, AO_RTI_GEN_CNTL_REG0, _bit, \
> + &gxbb_ao_pclk_parents, _flags)
> +
> +static GXBB_AO_PCLK(remote, 0, CLK_IGNORE_UNUSED);
> +static GXBB_AO_PCLK(i2c_master, 1, CLK_IGNORE_UNUSED);
> +static GXBB_AO_PCLK(i2c_slave, 2, CLK_IGNORE_UNUSED);
> +static GXBB_AO_PCLK(uart1, 3, CLK_IGNORE_UNUSED);
> +static GXBB_AO_PCLK(uart2, 5, CLK_IGNORE_UNUSED);
> +static GXBB_AO_PCLK(ir_blaster, 6, CLK_IGNORE_UNUSED);
>
> static struct clk_regmap gxbb_ao_cts_oscin = {
> .data = &(struct clk_regmap_gate_data){
>
> --
> 2.47.2
>
>
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
next prev parent reply other threads:[~2025-07-03 7:17 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-02 15:25 [PATCH 00/26] clk: amlogic: clock controllers clean-up and factorisation Jerome Brunet
2025-07-02 15:25 ` [PATCH 01/26] clk: amlogic: a1-peripherals: naming consistency alignment Jerome Brunet
2025-07-02 15:26 ` [PATCH 02/26] clk: amlogic: a1-pll: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 03/26] clk: amlogic: axg-ao: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 04/26] clk: amlogic: axg: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 05/26] clk: amlogic: c3-peripherals: " Jerome Brunet
2025-07-03 2:51 ` Chuan Liu
2025-07-03 7:48 ` Jerome Brunet
2025-07-03 8:31 ` Chuan Liu
2025-07-03 9:02 ` Jerome Brunet
2025-07-03 9:23 ` Chuan Liu
2025-07-02 15:26 ` [PATCH 06/26] clk: amlogic: c3-pll: " Jerome Brunet
2025-07-03 2:57 ` Chuan Liu
2025-07-02 15:26 ` [PATCH 07/26] clk: amlogic: g12a-ao: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 08/26] clk: amlogic: g12a: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 09/26] clk: amlogic: gxbb-ao: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 10/26] clk: amlogic: gxbb: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 11/26] clk: amlogic: meson8b: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 12/26] clk: amlogic: s4-peripherals: " Jerome Brunet
2025-07-03 3:18 ` Chuan Liu
2025-07-03 7:54 ` Jerome Brunet
2025-07-03 8:00 ` Chuan Liu
2025-07-02 15:26 ` [PATCH 13/26] clk: amlogic: s4-pll: " Jerome Brunet
2025-07-03 3:19 ` Chuan Liu
2025-07-02 15:26 ` [PATCH 14/26] clk: amlogic: meson8-ddr: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 15/26] clk: amlogic: drop meson-clkcee Jerome Brunet
2025-07-02 15:26 ` [PATCH 16/26] clk: amlogic: add probe helper for mmio based controllers Jerome Brunet
2025-07-03 3:29 ` Chuan Liu
2025-07-03 8:35 ` Jerome Brunet
2025-07-02 15:26 ` [PATCH 17/26] clk: amlogic: use probe helper in " Jerome Brunet
2025-07-03 6:29 ` Chuan Liu
2025-07-02 15:26 ` [PATCH 18/26] clk: amlogic: aoclk: use clkc-utils syscon probe Jerome Brunet
2025-07-02 15:26 ` [PATCH 19/26] clk: amlogic: move PCLK definition to clkc-utils Jerome Brunet
2025-07-02 15:26 ` [PATCH 20/26] clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks Jerome Brunet
2025-07-02 15:26 ` [PATCH 21/26] clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED Jerome Brunet
2025-07-03 7:05 ` Chuan Liu
2025-07-02 15:26 ` [PATCH 22/26] clk: amlogic: introduce a common pclk definition Jerome Brunet
2025-07-03 7:10 ` Chuan Liu
2025-07-02 15:26 ` [PATCH 23/26] clk: amlogic: use the " Jerome Brunet
2025-07-03 7:16 ` Chuan Liu [this message]
2025-07-03 8:39 ` Jerome Brunet
2025-07-02 15:26 ` [PATCH 24/26] clk: amlogic: add composite clock helpers Jerome Brunet
2025-07-03 7:24 ` Chuan Liu
2025-07-03 8:39 ` Jerome Brunet
2025-07-02 15:26 ` [PATCH 25/26] clk: amlogic: align s4 and c3 pwm clock descriptions Jerome Brunet
2025-07-03 7:27 ` Chuan Liu
2025-07-02 15:26 ` [PATCH 26/26] clk: amlogic: c3-peripherals: use helper for basic composite clocks Jerome Brunet
2025-07-03 7:56 ` Chuan Liu
2025-07-03 8:44 ` Jerome Brunet
2025-08-06 7:10 ` [PATCH 00/26] clk: amlogic: clock controllers clean-up and factorisation Chuan Liu
2025-08-25 14:24 ` Jerome Brunet
2025-09-21 11:25 ` Mark Brown
2025-09-21 12:21 ` Martin Blumenstingl
2025-09-21 12:59 ` Jerome Brunet
2025-09-22 9:40 ` Mark Brown
2025-09-22 11:02 ` Martin Blumenstingl
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1fcf7e52-b265-4341-a360-93aaf293f131@amlogic.com \
--to=chuan.liu@amlogic.com \
--cc=jbrunet@baylibre.com \
--cc=khilman@baylibre.com \
--cc=linux-amlogic@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=martin.blumenstingl@googlemail.com \
--cc=mturquette@baylibre.com \
--cc=neil.armstrong@linaro.org \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox