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From: Jerome Brunet <jbrunet@baylibre.com>
To: Chuan Liu <chuan.liu@amlogic.com>
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
	 Michael Turquette <mturquette@baylibre.com>,
	 Stephen Boyd <sboyd@kernel.org>,
	 Kevin Hilman <khilman@baylibre.com>,
	 Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	 linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
	 linux-kernel@vger.kernel.org
Subject: Re: [PATCH 05/26] clk: amlogic: c3-peripherals: naming consistency alignment
Date: Thu, 03 Jul 2025 11:02:25 +0200	[thread overview]
Message-ID: <1jtt3tbqam.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <99ba0e33-cec2-4577-b949-010537a8c4df@amlogic.com> (Chuan Liu's message of "Thu, 3 Jul 2025 16:31:12 +0800")

>>>>
>>>> -#define C3_CLK_GATE(_name, _reg, _bit, _fw_name, _ops, _flags)         \
>>>> -struct clk_regmap _name = {                                            \
>>>> +#define C3_PCLK(_name, _reg, _bit, _fw_name, _ops, _flags)             \
>>>> +struct clk_regmap c3_##_name = {                                       \
>>>>           .data = &(struct clk_regmap_gate_data){                         \
>>>>                   .offset = (_reg),                                       \
>>>>                   .bit_idx = (_bit),                                      \
>>>>           },                                                              \
>>>>           .hw.init = &(struct clk_init_data) {                            \
>>>> -               .name = #_name,                                         \
>>>> +               .name = "c3_" #_name,                                   \
>>>
>>> Prefixing variable names with 'SoC' is understandable (to avoid duplicate
>>> definitions and facilitate variable searching), but is it necessary to add
>>> 'SoC' prefixes to clock names?
>> This is part of the description but I'll ellaborate.
>>
>> Some controllers do so, some do not. This is a typical pointless
>> difference that make code sharing difficult and lead to the duplication
>> I'm addressing now.
>
>
> Yes, in fact most clock configurations are consistent across our SoCs. Over
> the years, we've been continuously working to make our driver code more
> 'common'
> and efficient.
>

No they are not consistent at all when it come to this

Controller prefixing the pclks:
* axg-ao
* axg
* g12-ao
* g12
* gxbb
* s4-periphs

Controllers not prefixing the pclks
* gxbb-ao
* a1-periphs
* c3-periphs
* meson8b

I do not want to invent new names to avoid the names clashes if the
prefixes are dropped. I tried that way and it was a mess.

As noted in the description, clock names will not be prefixed with SoC
name, *except* for the pclks for the historic reason explained above.

>
>>
>> Both with and without are fine but picking one a sticking to it helps a
>> lot. I would have preferred to drop the prefix from the pclk clock
>> names, same as the other clock, but:
>
>
> I still prefer adding SoC prefixes to variable names but not to clock names.
> clocks with the same name generally have similar functions across different
> chips.

It is not a matter of preference.

>
>
>> * It would have changed more clock names and I prefer to minimize those
>> changes
>
>
> Your recent patch series has already made significant changes, and this is
> relatively a minor adjustment😉
>
>
>> * It would have caused several name clashes with other clocks.
>>
>> so prefix it is for the peripheral clock.
>>
>> In the end, what matters is consistency.
>>
>>>
>>>>                   .ops = _ops,                                            \
>>>>                   .parent_data = &(const struct clk_parent_data) {        \
>>>> -                       .fw_name = #_fw_name,                           \
>>>> +                       .fw_name = (_fw_name),                          \
>>>>                   },                                                      \
>>>>                   .num_parents = 1,                                       \
>>>>                   .flags = (_flags),                                      \
>>>>           },                                                              \
>>>>    }
>>>
>>> [...]
>> --
>> Jerome

-- 
Jerome

  reply	other threads:[~2025-07-03  9:02 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-02 15:25 [PATCH 00/26] clk: amlogic: clock controllers clean-up and factorisation Jerome Brunet
2025-07-02 15:25 ` [PATCH 01/26] clk: amlogic: a1-peripherals: naming consistency alignment Jerome Brunet
2025-07-02 15:26 ` [PATCH 02/26] clk: amlogic: a1-pll: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 03/26] clk: amlogic: axg-ao: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 04/26] clk: amlogic: axg: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 05/26] clk: amlogic: c3-peripherals: " Jerome Brunet
2025-07-03  2:51   ` Chuan Liu
2025-07-03  7:48     ` Jerome Brunet
2025-07-03  8:31       ` Chuan Liu
2025-07-03  9:02         ` Jerome Brunet [this message]
2025-07-03  9:23           ` Chuan Liu
2025-07-02 15:26 ` [PATCH 06/26] clk: amlogic: c3-pll: " Jerome Brunet
2025-07-03  2:57   ` Chuan Liu
2025-07-02 15:26 ` [PATCH 07/26] clk: amlogic: g12a-ao: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 08/26] clk: amlogic: g12a: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 09/26] clk: amlogic: gxbb-ao: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 10/26] clk: amlogic: gxbb: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 11/26] clk: amlogic: meson8b: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 12/26] clk: amlogic: s4-peripherals: " Jerome Brunet
2025-07-03  3:18   ` Chuan Liu
2025-07-03  7:54     ` Jerome Brunet
2025-07-03  8:00       ` Chuan Liu
2025-07-02 15:26 ` [PATCH 13/26] clk: amlogic: s4-pll: " Jerome Brunet
2025-07-03  3:19   ` Chuan Liu
2025-07-02 15:26 ` [PATCH 14/26] clk: amlogic: meson8-ddr: " Jerome Brunet
2025-07-02 15:26 ` [PATCH 15/26] clk: amlogic: drop meson-clkcee Jerome Brunet
2025-07-02 15:26 ` [PATCH 16/26] clk: amlogic: add probe helper for mmio based controllers Jerome Brunet
2025-07-03  3:29   ` Chuan Liu
2025-07-03  8:35     ` Jerome Brunet
2025-07-02 15:26 ` [PATCH 17/26] clk: amlogic: use probe helper in " Jerome Brunet
2025-07-03  6:29   ` Chuan Liu
2025-07-02 15:26 ` [PATCH 18/26] clk: amlogic: aoclk: use clkc-utils syscon probe Jerome Brunet
2025-07-02 15:26 ` [PATCH 19/26] clk: amlogic: move PCLK definition to clkc-utils Jerome Brunet
2025-07-02 15:26 ` [PATCH 20/26] clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks Jerome Brunet
2025-07-02 15:26 ` [PATCH 21/26] clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED Jerome Brunet
2025-07-03  7:05   ` Chuan Liu
2025-07-02 15:26 ` [PATCH 22/26] clk: amlogic: introduce a common pclk definition Jerome Brunet
2025-07-03  7:10   ` Chuan Liu
2025-07-02 15:26 ` [PATCH 23/26] clk: amlogic: use the " Jerome Brunet
2025-07-03  7:16   ` Chuan Liu
2025-07-03  8:39     ` Jerome Brunet
2025-07-02 15:26 ` [PATCH 24/26] clk: amlogic: add composite clock helpers Jerome Brunet
2025-07-03  7:24   ` Chuan Liu
2025-07-03  8:39     ` Jerome Brunet
2025-07-02 15:26 ` [PATCH 25/26] clk: amlogic: align s4 and c3 pwm clock descriptions Jerome Brunet
2025-07-03  7:27   ` Chuan Liu
2025-07-02 15:26 ` [PATCH 26/26] clk: amlogic: c3-peripherals: use helper for basic composite clocks Jerome Brunet
2025-07-03  7:56   ` Chuan Liu
2025-07-03  8:44     ` Jerome Brunet
2025-08-06  7:10 ` [PATCH 00/26] clk: amlogic: clock controllers clean-up and factorisation Chuan Liu
2025-08-25 14:24 ` Jerome Brunet
2025-09-21 11:25 ` Mark Brown
2025-09-21 12:21   ` Martin Blumenstingl
2025-09-21 12:59     ` Jerome Brunet
2025-09-22  9:40       ` Mark Brown
2025-09-22 11:02         ` Martin Blumenstingl

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