From: Jerome Brunet <jbrunet@baylibre.com>
To: Dmitry Rokosov <ddrokosov@salutedevices.com>
Cc: <neil.armstrong@linaro.org>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <khilman@baylibre.com>,
<martin.blumenstingl@googlemail.com>, <jian.hu@amlogic.com>,
<kernel@sberdevices.ru>, <rockosov@gmail.com>,
<linux-amlogic@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3 0/7] clk: meson: introduce Amlogic A1 SoC Family CPU clock controller driver
Date: Mon, 10 Jun 2024 12:13:41 +0200 [thread overview]
Message-ID: <1jed95p0kq.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <20240515185103.20256-1-ddrokosov@salutedevices.com> (Dmitry Rokosov's message of "Wed, 15 May 2024 21:47:23 +0300")
On Wed 15 May 2024 at 21:47, Dmitry Rokosov <ddrokosov@salutedevices.com> wrote:
> The CPU clock controller plays a general role in the Amlogic A1 SoC
> family by generating CPU clocks. As an APB slave module, it offers the
> capability to inherit the CPU clock from two sources: the internal fixed
> clock known as 'cpu fixed clock' and the external input provided by the
> A1 PLL clock controller, referred to as 'syspll'.
>
> It is important for the driver to handle the cpu_clk rate switching
> effectively by transitioning to the CPU fixed clock to avoid any
> potential execution freezes.
>
Please group your changes, fixes then bindings then driver.
next prev parent reply other threads:[~2024-06-10 10:13 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-15 18:47 [PATCH v3 0/7] clk: meson: introduce Amlogic A1 SoC Family CPU clock controller driver Dmitry Rokosov
2024-05-15 18:47 ` [PATCH v3 1/7] clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL Dmitry Rokosov
2024-05-15 18:47 ` [PATCH v3 2/7] dt-bindings: clock: meson: a1: pll: introduce new syspll bindings Dmitry Rokosov
2024-05-20 19:02 ` Rob Herring (Arm)
2024-05-15 18:47 ` [PATCH v3 3/7] clk: meson: a1: pll: support 'syspll' general-purpose PLL for CPU clock Dmitry Rokosov
2024-06-10 10:03 ` Jerome Brunet
2024-06-10 13:12 ` Dmitry Rokosov
2024-05-15 18:47 ` [PATCH v3 4/7] dt-bindings: clock: meson: a1: peripherals: support sys_pll input Dmitry Rokosov
2024-05-15 19:00 ` Dmitry Rokosov
2024-05-20 19:18 ` Rob Herring (Arm)
2024-05-15 18:47 ` [PATCH v3 5/7] clk: meson: a1: peripherals: support 'sys_pll_div16' clock as GEN input Dmitry Rokosov
2024-05-15 18:47 ` [PATCH v3 6/7] dt-bindings: clock: meson: add A1 CPU clock controller bindings Dmitry Rokosov
2024-06-10 10:04 ` Jerome Brunet
2024-06-10 11:18 ` Dmitry Rokosov
2024-06-10 11:47 ` Jerome Brunet
2024-06-10 12:48 ` Dmitry Rokosov
2024-06-13 9:03 ` Dmitry Rokosov
2024-05-15 18:47 ` [PATCH v3 7/7] clk: meson: a1: add Amlogic A1 CPU clock controller driver Dmitry Rokosov
2024-06-10 10:06 ` Jerome Brunet
2024-06-10 13:08 ` Dmitry Rokosov
2024-06-10 20:10 ` Dmitry Rokosov
2024-05-28 17:41 ` [PATCH v3 0/7] clk: meson: introduce Amlogic A1 SoC Family " Dmitry Rokosov
2024-06-10 10:13 ` Jerome Brunet [this message]
2024-06-10 11:21 ` Dmitry Rokosov
2024-06-10 10:32 ` (subset) " Jerome Brunet
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