[RESEND PATCH v2 0/8] fix and optimize some clock configuration for the RK3399 platfom

[RESEND PATCH v2 0/8] fix and optimize some clock configuration for the RK3399 platfom

[Xing Zheng]

Hi:
  In the development work, we found that some of the previous
incorrect clock configuration on the RK3399 platform, we should
fix and optimize them.

Changes in v2:
- add the patch "fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src"
- add the patch "fix incorrect GATE bits for {c, g}pll_aclk_perihp_src"

Elaine Zhang (1):
  clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie

Xing Zheng (7):
  clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
  clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
  clk: rockchip: rk3399: fix incorrect parent for rk3399's {c,
    g}pll_aclk_perihp_src
  clk: rockchip: rk3399: fix incorrect GATE bits for {c,
    g}pll_aclk_perihp_src
  clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
  clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
  clk: rockchip: rk3399: Add support frac mode frequencies

 drivers/clk/rockchip/clk-rk3399.c      |   41 ++++++++++++++++++++++++--------
 include/dt-bindings/clock/rk3399-cru.h |    2 ++
 2 files changed, 33 insertions(+), 10 deletions(-)

-- 
1.7.9.5

[RESEND PATCH v2 2/8] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1

[Xing Zheng]

Export these source clocks for usbphy.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

---

Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 78e51cb..f55f967f 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -403,9 +403,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 	GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(6), 6, GFLAGS),
 
-	GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
+	GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(13), 12, GFLAGS),
-	GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
+	GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(13), 12, GFLAGS),
 	MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
 			RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
-- 
1.7.9.5

[RESEND PATCH v2 3/8] clk: rockchip: rk3399: fix incorrect parent for rk3399's {c, g}pll_aclk_perihp_src

[Xing Zheng]

There was a typo, swapping 'c' <--> 'g'.
(This patch is updated and am from https://patchwork.kernel.org/patch/9254067/)

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---

Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index f55f967f..2182391 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -832,9 +832,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(13), 1, GFLAGS),
 
 	/* perihp */
-	GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
+	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(5), 0, GFLAGS),
-	GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
+	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(5), 1, GFLAGS),
 	COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
 			RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
-- 
1.7.9.5

Re: [RESEND PATCH v2 3/8] clk: rockchip: rk3399: fix incorrect parent for rk3399's {c, g}pll_aclk_perihp_src

[Brian Norris]

On Mon, Aug 01, 2016 at 05:53:38PM +0800, Xing Zheng wrote:
> There was a typo, swapping 'c' <--> 'g'.
> (This patch is updated and am from https://patchwork.kernel.org/patch/9254067/)
> 
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> ---
> 
> Changes in v2: None

I believe this patch was already applied upstream; otherwise, it
wouldn't make sense to have both this patch and patch 4 -- we would
probably squash them together.

Brian

>  drivers/clk/rockchip/clk-rk3399.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
> index f55f967f..2182391 100644
> --- a/drivers/clk/rockchip/clk-rk3399.c
> +++ b/drivers/clk/rockchip/clk-rk3399.c
> @@ -832,9 +832,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
>  			RK3399_CLKGATE_CON(13), 1, GFLAGS),
>  
>  	/* perihp */
> -	GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
> +	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
>  			RK3399_CLKGATE_CON(5), 0, GFLAGS),
> -	GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
> +	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
>  			RK3399_CLKGATE_CON(5), 1, GFLAGS),
>  	COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
>  			RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
> -- 
> 1.7.9.5
> 
> 

Re: [RESEND PATCH v2 3/8] clk: rockchip: rk3399: fix incorrect parent for rk3399's {c, g}pll_aclk_perihp_src

[Xing Zheng]

Hi Brain,

On 2016年08月02日 04:13, Brian Norris wrote:
> On Mon, Aug 01, 2016 at 05:53:38PM +0800, Xing Zheng wrote:
>> There was a typo, swapping 'c' <--> 'g'.
>> (This patch is updated and am from https://patchwork.kernel.org/patch/9254067/)
>>
>> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
>> Signed-off-by: Brian Norris <briannorris@chromium.org>
>> Reviewed-by: Douglas Anderson <dianders@chromium.org>
>> ---
>>
>> Changes in v2: None
> I believe this patch was already applied upstream; otherwise, it
> wouldn't make sense to have both this patch and patch 4 -- we would
> probably squash them together.
>
> Brian
>
Yes, this patch is applied in mmind/linux-rockchip.git v4.7-clk/fixes, I 
arm sorry to tracked on v4.8-clk/next so that didn't note it.
This patch will be abandoned.

Thanks.

>>   drivers/clk/rockchip/clk-rk3399.c |    4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
>> index f55f967f..2182391 100644
>> --- a/drivers/clk/rockchip/clk-rk3399.c
>> +++ b/drivers/clk/rockchip/clk-rk3399.c
>> @@ -832,9 +832,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
>>   			RK3399_CLKGATE_CON(13), 1, GFLAGS),
>>   
>>   	/* perihp */
>> -	GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
>> +	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
>>   			RK3399_CLKGATE_CON(5), 0, GFLAGS),
>> -	GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
>> +	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
>>   			RK3399_CLKGATE_CON(5), 1, GFLAGS),
>>   	COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
>>   			RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
>> -- 
>> 1.7.9.5
>>
>>
>
>

-- 
- Xing Zheng

[RESEND PATCH v2 4/8] clk: rockchip: rk3399: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src

[Xing Zheng]

Sorry to refer incorrect clock diagram, we double check it that the
bits configuration of the Xpll_aclk_perihp_src need to be fixed:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 2182391..8bf0d19 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -833,9 +833,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 
 	/* perihp */
 	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
-			RK3399_CLKGATE_CON(5), 0, GFLAGS),
-	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(5), 1, GFLAGS),
+	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
+			RK3399_CLKGATE_CON(5), 0, GFLAGS),
 	COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
 			RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
 			RK3399_CLKGATE_CON(5), 2, GFLAGS),
-- 
1.7.9.5

Re: [RESEND PATCH v2 4/8] clk: rockchip: rk3399: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src

[Brian Norris]

On Mon, Aug 01, 2016 at 05:53:39PM +0800, Xing Zheng wrote:
> Sorry to refer incorrect clock diagram, we double check it that the
> bits configuration of the Xpll_aclk_perihp_src need to be fixed:
> bit 1 - shows aclk_perihp_cpll_src_en
> bit 0 - shows aclk_perihp_gpll_src_en

Last time, you confirmed with the IC designers that we had things right.
What's different this time? Have you, for instance, done more thorough
testing, to show that the logical parent structure this driver outputs
is actually what the hardware is doing?

I think maybe this would qualify as:

Fixes: 3bd14ae9da91 ("clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src")

The above is not exactly a pure regression (we really want both
changes), but apparently it wasn't a complete fix.

> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
> ---
> 
> Changes in v2: None

Uhh, isn't this patch brand new in v2? I don't think that means
"Changes ... None".

Brian

>  drivers/clk/rockchip/clk-rk3399.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
> index 2182391..8bf0d19 100644
> --- a/drivers/clk/rockchip/clk-rk3399.c
> +++ b/drivers/clk/rockchip/clk-rk3399.c
> @@ -833,9 +833,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
>  
>  	/* perihp */
>  	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
> -			RK3399_CLKGATE_CON(5), 0, GFLAGS),
> -	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
>  			RK3399_CLKGATE_CON(5), 1, GFLAGS),
> +	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
> +			RK3399_CLKGATE_CON(5), 0, GFLAGS),
>  	COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
>  			RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
>  			RK3399_CLKGATE_CON(5), 2, GFLAGS),
> -- 
> 1.7.9.5
> 
> 

Re: [RESEND PATCH v2 4/8] clk: rockchip: rk3399: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src

[Xing Zheng]

[-- Attachment #1: Type: text/plain, Size: 4284 bytes --]

On 2016?08?02? 04:20, Brian Norris wrote:
> On Mon, Aug 01, 2016 at 05:53:39PM +0800, Xing Zheng wrote:
>> Sorry to refer incorrect clock diagram, we double check it that the
>> bits configuration of the Xpll_aclk_perihp_src need to be fixed:
>> bit 1 - shows aclk_perihp_cpll_src_en
>> bit 0 - shows aclk_perihp_gpll_src_en
> Last time, you confirmed with the IC designers that we had things right.
> What's different this time? Have you, for instance, done more thorough
> testing, to show that the logical parent structure this driver outputs
> is actually what the hardware is doing?
I tried to proof it throught the testing that plug/unplug the USB 
ethernet cable on kevin board.

1. the hclk_host0 and hclk_host1 are endpoint clocks.
cpll --> G5[1] --> aclk_perihp_cpll_src --\                   |--> 
hclk_host0
                                                                 | --> 
... ---> |
gpll --> G5[0] --> aclk_perihp_gpll_src --/                   |--> 
hclk_host1

2. on the kevin, there is no clock below the cpll_aclk_perihp_src, and 
the hclk_hostX are below the gpll_aclk_perihp_src:
     pll_cpll                              1            1   
800000000          0 0
        cpll                               7           19   
800000000          0 0
           cpll_aclk_perihp_src            0            0   
800000000          0 0

...
     pll_gpll                              1            1   
594000000          0 0
        gpll                              10           10   
594000000          0 0
           gpll_aclk_perihp_src            2            2   
594000000          0 0
                 hclk_perihp               5            5    
74250000          0 0
                    hclk_host1_arb           2            2    
74250000          0 0
                    hclk_host1             2            2    
74250000          0 0
                    hclk_host0_arb           2            2    
74250000          0 0
                    hclk_host0             2            2    
74250000          0 0

3. by default, G5[0] and G5[1] are enabled:
localhost ~ # mem r 0xff760314
0x000003e0

4. close the G5[1] (aclk_perihp_cpll_src), and plug/unplug USB ethernet 
cable, the DUT still works well:
localhost ~ # mem w 0xff760314 0xffff03e2
localhost ~ # mem r 0xff760314
0x000003e2
plug/unplug ok

5. close the G5[0] (aclk_perihp_gpll_src), , and plug/unplug USB 
ethernet cable, the DUT will be crashed:
localhost ~ # mem w 0xff760314 0xffff03e1
localhost ~ # mem r 0xff760314
0x000003e1
plug/unplug crashed

Hence:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en

>
> I think maybe this would qualify as:
>
> Fixes: 3bd14ae9da91 ("clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src")
>
> The above is not exactly a pure regression (we really want both
> changes), but apparently it wasn't a complete fix.
OK, I will add the commit message
"Fixes: 3bd14ae9da91 ("clk: rockchip: fix incorrect parent for rk3399's 
{c,g}pll_aclk_perihp_src")"
at next version.
>
>> Signed-off-by: Xing Zheng<zhengxing@rock-chips.com>
>> ---
>>
>> Changes in v2: None
> Uhh, isn't this patch brand new in v2? I don't think that means
> "Changes ... None".
Yes, I will add change log into this patch at next version.

Thanks.
>
> Brian
>
>>   drivers/clk/rockchip/clk-rk3399.c |    4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
>> index 2182391..8bf0d19 100644
>> --- a/drivers/clk/rockchip/clk-rk3399.c
>> +++ b/drivers/clk/rockchip/clk-rk3399.c
>> @@ -833,9 +833,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
>>
>>   	/* perihp */
>>   	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
>> -			RK3399_CLKGATE_CON(5), 0, GFLAGS),
>> -	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
>>   			RK3399_CLKGATE_CON(5), 1, GFLAGS),
>> +	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
>> +			RK3399_CLKGATE_CON(5), 0, GFLAGS),
>>   	COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
>>   			RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
>>   			RK3399_CLKGATE_CON(5), 2, GFLAGS),
>> -- 
>> 1.7.9.5
>>
>>
>
>


-- 
- Xing Zheng


[-- Attachment #2: Type: text/html, Size: 10702 bytes --]

Re: [RESEND PATCH v2 4/8] clk: rockchip: rk3399: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src

[Xing Zheng]

[-- Attachment #1: Type: text/plain, Size: 4674 bytes --]

On 2016?08?02? 11:01, Xing Zheng wrote:
> On 2016?08?02? 04:20, Brian Norris wrote:
>> On Mon, Aug 01, 2016 at 05:53:39PM +0800, Xing Zheng wrote:
>>> Sorry to refer incorrect clock diagram, we double check it that the
>>> bits configuration of the Xpll_aclk_perihp_src need to be fixed:
>>> bit 1 - shows aclk_perihp_cpll_src_en
>>> bit 0 - shows aclk_perihp_gpll_src_en
>> Last time, you confirmed with the IC designers that we had things right.
>> What's different this time? Have you, for instance, done more thorough
>> testing, to show that the logical parent structure this driver outputs
>> is actually what the hardware is doing?
> I tried to proof it throught the testing that plug/unplug the USB 
> ethernet cable on kevin board.
>
> 1. the hclk_host0 and hclk_host1 are endpoint clocks.
> cpll --> G5[1] --> aclk_perihp_cpll_src --\                   |--> 
> hclk_host0
>                                                                 | --> 
> ... ---> |
> gpll --> G5[0] --> aclk_perihp_gpll_src --/                   |--> 
> hclk_host1
>
> 2. on the kevin, there is no clock below the cpll_aclk_perihp_src, and 
> the hclk_hostX are below the gpll_aclk_perihp_src:
>     pll_cpll                              1            1   
> 800000000          0 0
>        cpll                               7           19   
> 800000000          0 0
>           cpll_aclk_perihp_src            0            0   
> 800000000          0 0
>
> ...
>     pll_gpll                              1            1   
> 594000000          0 0
>        gpll                              10           10   
> 594000000          0 0
>           gpll_aclk_perihp_src            2            2   
> 594000000          0 0
>                 hclk_perihp               5            5    
> 74250000          0 0
>                    hclk_host1_arb           2            2    
> 74250000          0 0
>                    hclk_host1             2            2    
> 74250000          0 0
>                    hclk_host0_arb           2            2    
> 74250000          0 0
>                    hclk_host0             2            2    
> 74250000          0 0
>
> 3. by default, G5[0] and G5[1] are enabled:
> localhost ~ # mem r 0xff760314
> 0x000003e0
>
> 4. close the G5[1] (aclk_perihp_cpll_src), and plug/unplug USB 
> ethernet cable, the DUT still works well:
> localhost ~ # mem w 0xff760314 0xffff03e2
> localhost ~ # mem r 0xff760314
> 0x000003e2
> plug/unplug ok
>
> 5. close the G5[0] (aclk_perihp_gpll_src), , and plug/unplug USB 
> ethernet cable, the DUT will be crashed:
> localhost ~ # mem w 0xff760314 0xffff03e1
> localhost ~ # mem r 0xff760314
> 0x000003e1
> plug/unplug crashed
>
> Hence:
> bit 1 - shows aclk_perihp_cpll_src_en
> bit 0 - shows aclk_perihp_gpll_src_en
>
>> I think maybe this would qualify as:
>>
>> Fixes: 3bd14ae9da91 ("clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src")
>>
>> The above is not exactly a pure regression (we really want both
>> changes), but apparently it wasn't a complete fix.
> OK, I will add the commit message
> "Fixes: 3bd14ae9da91 ("clk: rockchip: fix incorrect parent for 
> rk3399's {c,g}pll_aclk_perihp_src")"
> at next version.
>>> Signed-off-by: Xing Zheng<zhengxing@rock-chips.com>
>>> ---
>>>
>>> Changes in v2: None
>> Uhh, isn't this patch brand new in v2? I don't think that means
>> "Changes ... None".
> Yes, I will add change log into this patch at next version.
>
> Thanks. 
Sorry to change my mind. This patch is only started to be added in 
patchset_v2, not be included in my patchset_v1, so I think it should be 
"Changes ... None".

Thanks.
>> Brian
>>
>>>   drivers/clk/rockchip/clk-rk3399.c |    4 ++--
>>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
>>> index 2182391..8bf0d19 100644
>>> --- a/drivers/clk/rockchip/clk-rk3399.c
>>> +++ b/drivers/clk/rockchip/clk-rk3399.c
>>> @@ -833,9 +833,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
>>>
>>>   	/* perihp */
>>>   	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
>>> -			RK3399_CLKGATE_CON(5), 0, GFLAGS),
>>> -	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
>>>   			RK3399_CLKGATE_CON(5), 1, GFLAGS),
>>> +	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
>>> +			RK3399_CLKGATE_CON(5), 0, GFLAGS),
>>>   	COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
>>>   			RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
>>>   			RK3399_CLKGATE_CON(5), 2, GFLAGS),
>>> -- 
>>> 1.7.9.5
>>>
>>>
>>
>
>
> -- 
> - Xing Zheng


-- 
- Xing Zheng


[-- Attachment #2: Type: text/html, Size: 11537 bytes --]

[RESEND PATCH v2 5/8] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits

[Xing Zheng]

Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 8bf0d19..44e673e 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -923,9 +923,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(6), 14, GFLAGS),
 
 	GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
-			RK3399_CLKGATE_CON(6), 12, GFLAGS),
-	GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(6), 13, GFLAGS),
+	GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
+			RK3399_CLKGATE_CON(6), 12, GFLAGS),
 	COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
 			RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
 	GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
-- 
1.7.9.5

[RESEND PATCH v2 6/8] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI

[Xing Zheng]

We need to add more clocks for supporting more display resolution
for HDMI.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 44e673e..580abf1 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -100,8 +100,10 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
 	RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
 	RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
 	RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
+	RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
 	RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
 	RK3036_PLL_RATE(  74250000, 2, 99, 4, 4, 1, 0),
+	RK3036_PLL_RATE(  65000000, 1, 65, 6, 4, 1, 0),
 	RK3036_PLL_RATE(  54000000, 1, 54, 6, 4, 1, 0),
 	RK3036_PLL_RATE(  27000000, 1, 27, 6, 4, 1, 0),
 	{ /* sentinel */ },
-- 
1.7.9.5

[RESEND PATCH v2 7/8] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie

[Xing Zheng]

From: Elaine Zhang <zhangqing@rock-chips.com>

allow aclk_pcie and aclk_perf_pcie disabled when unused.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

---

Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 580abf1..071eb96 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -848,9 +848,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
 			RK3399_CLKGATE_CON(5), 4, GFLAGS),
 
-	GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+	GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
 			RK3399_CLKGATE_CON(20), 2, GFLAGS),
-	GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+	GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
 			RK3399_CLKGATE_CON(20), 10, GFLAGS),
 	GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(20), 12, GFLAGS),
-- 
1.7.9.5

[RESEND PATCH v2 8/8] clk: rockchip: rk3399: Add support frac mode frequencies

[Xing Zheng]

We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

Changes in v2:
- add the patch "fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src"
- add the patch "fix incorrect GATE bits for {c, g}pll_aclk_perihp_src"

 drivers/clk/rockchip/clk-rk3399.c |   21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 071eb96..db8394b 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -109,6 +109,25 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
 	{ /* sentinel */ },
 };
 
+static struct rockchip_pll_rate_table rk3399_pll_frates[] = {
+	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+	RK3036_PLL_RATE( 594000000, 1, 123, 5, 1, 0, 12582912),  /* vco = 2970000000 */
+	RK3036_PLL_RATE( 593406593, 1, 123, 5, 1, 0, 10508804),  /* vco = 2967032965 */
+	RK3036_PLL_RATE( 297000000, 1, 123, 5, 2, 0, 12582912),  /* vco = 2970000000 */
+	RK3036_PLL_RATE( 296703297, 1, 123, 5, 2, 0, 10508807),  /* vco = 2967032970 */
+	RK3036_PLL_RATE( 148500000, 1, 129, 7, 3, 0, 15728640),  /* vco = 3118500000 */
+	RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800),  /* vco = 2967032960 */
+	RK3036_PLL_RATE( 106500000, 1, 124, 7, 4, 0,  4194304),  /* vco = 2982000000 */
+	RK3036_PLL_RATE(  74250000, 1, 129, 7, 6, 0, 15728640),  /* vco = 3118500000 */
+	RK3036_PLL_RATE(  74175824, 1, 129, 7, 6, 0, 13550823),  /* vco = 3115384608 */
+	RK3036_PLL_RATE(  65000000, 1, 113, 7, 6, 0, 12582912),  /* vco = 2730000000 */
+	RK3036_PLL_RATE(  59340659, 1, 121, 7, 7, 0,  2581098),  /* vco = 2907692291 */
+	RK3036_PLL_RATE(  54000000, 1, 110, 7, 7, 0,  4194304),  /* vco = 2646000000 */
+	RK3036_PLL_RATE(  27000000, 1,  55, 7, 7, 0,  2097152),  /* vco = 1323000000 */
+	RK3036_PLL_RATE(  26973027, 1,  55, 7, 7, 0,  1173232),  /* vco = 1321678323 */
+	{ /* sentinel */ },
+};
+
 /* CRU parents */
 PNAME(mux_pll_p)				= { "xin24m", "xin32k" };
 
@@ -229,7 +248,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
 	[npll] = PLL(pll_rk3399, PLL_NPLL, "npll",  mux_pll_p, 0, RK3399_PLL_CON(40),
 		     RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
 	[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll",  mux_pll_p, 0, RK3399_PLL_CON(48),
-		     RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
+		     RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_frates),
 };
 
 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
-- 
1.7.9.5