[PATCH 0/6] Allwinner A33 CPU frequency scaling support

[PATCH 0/6] Allwinner A33 CPU frequency scaling support

[Icenowy Zheng]

This series of patch adds frequency scaling support to Allwinner A33 SoC.

The first two patches fixes some bugs in the A33 CCU code.

The patch 3 and 4 is for enabling the cpufreq-dt driver to work.

The patch 5 is for enabling the voltage adjusting on reference design tablets.

The patch 6 is for enabling the "turbo-mode" of A33. (According to the
"extremity_freq" property in the FEX file. When I tested it with 3.4 BSP, it
really performs as a turbo mode.)

If there's any doubt of safety, the patch 6 can be ignored.

If there's any problem in patch 3, 4 and 5, they can also be temporarily
ignored, but finally we need them ;-)

Although there's now currently no thermal support for A33, many A33 devices
are tablets with battery, and it will be valuable to save some power energy,
so cpufreq support is also useful.

P.S.

Chen-Yu,

Do you want to test the CCU fix and the operating point table on A23?

Regards,
Icenowy

[PATCH 1/6] clk: sunxi-ng: fix PLL_CPUX adjusting on A33

[Icenowy Zheng]

When adjusting PLL_CPUX on A33, the PLL is temporarily driven too high,
and the system hangs.

Add a notifier to avoid this situation by temporarily switching to a
known stable 24 MHz oscillator.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 3cd4190ccd59..0f3e7d2dc19a 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -752,6 +752,13 @@ static const struct sunxi_ccu_desc sun8i_a33_ccu_desc = {
 	.num_resets	= ARRAY_SIZE(sun8i_a33_ccu_resets),
 };
 
+static struct ccu_mux_nb sun8i_a33_cpu_nb = {
+	.common		= &cpux_clk.common,
+	.cm		= &cpux_clk.mux,
+	.delay_us	= 1, /* > 8 clock cycles at 24 MHz */
+	.bypass_index	= 1, /* index of 24 MHz oscillator */
+};
+
 static void __init sun8i_a33_ccu_setup(struct device_node *node)
 {
 	void __iomem *reg;
@@ -775,6 +782,9 @@ static void __init sun8i_a33_ccu_setup(struct device_node *node)
 	writel(val, reg + SUN8I_A33_PLL_MIPI_REG);
 
 	sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc);
+
+	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
+				  &sun8i_a33_cpu_nb);
 }
 CLK_OF_DECLARE(sun8i_a33_ccu, "allwinner,sun8i-a33-ccu",
 	       sun8i_a33_ccu_setup);
-- 
2.11.0

[PATCH 2/6] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33

[Icenowy Zheng]

The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
be changeable by changing the rate of PLL_CPUX.

Add CLK_SET_RATE_PARENT flag to this clock.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 0f3e7d2dc19a..0d513d2674cb 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -170,7 +170,7 @@ static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
 static const char * const cpux_parents[] = { "osc32k", "osc24M",
 					     "pll-cpux" , "pll-cpux" };
 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
-		     0x050, 16, 2, CLK_IS_CRITICAL);
+		     0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
 
 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 
-- 
2.11.0

[PATCH 3/6] ARM: dts: sun8i: add a cpu0 label to cpu@0 node on A23/33

[Icenowy Zheng]

A "cpu0" label is needed on cpu@0 for cpufreq-dt to work.

Add such a label, in order to prepare for cpufreq support of A23/33.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 817747f41288..5931cc4d1567 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -84,7 +84,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <0>;
-- 
2.11.0

[PATCH 4/6] ARM: dts: sun8i: add opp-v2 table for A33

[Icenowy Zheng]

An operating point table is needed for the cpu frequency adjusting to
work.

The operating point table is converted from the common value in
extracted script.fex from many A33 board/tablets.

1.344GHz is set as a turbo-mode operating point, as it's described as
"extremity_freq" in the FEX file. (the "max_freq" is 1.2GHz)

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm/boot/dts/sun8i-a33.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 504996cbee29..035c058324b8 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -46,7 +46,45 @@
 #include <dt-bindings/dma/sun4i-a10.h>
 
 / {
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@648000000 {
+			opp-hz = /bits/ 64 <648000000>;
+			opp-microvolt = <1040000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp@816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp@1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1200000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp@1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1320000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp@1344000000 {
+			opp-hz = /bits/ 64 <1344000000>;
+			opp-microvolt = <1460000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			turbo-mode;
+		};
+	};
+
 	cpus {
+		cpu0: cpu@0 {
+			clocks = <&ccu CLK_CPUX>;
+			clock-names = "cpu";
+			operating-points-v2 = <&cpu0_opp_table>;
+		};
+
 		cpu@2 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
-- 
2.11.0

[PATCH 5/6] ARM: dts: sun8i: set cpu-supply in reference tablet DTSI

[Icenowy Zheng]

All reference design A33 tablets uses DCDC2 of AXP223 as the power
supply of the Cortex-A7 cores.

Set the cpu-supply in the DTSI of sun8i reference tablets.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
index 08cd00143635..7ac8bb4bc95a 100644
--- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
@@ -213,6 +213,10 @@
 	regulator-name = "vcc-rtc";
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
 &r_uart {
 	pinctrl-names = "default";
 	pinctrl-0 = <&r_uart_pins_a>;
-- 
2.11.0

[PATCH 6/6] ARM: dts: sun8i: raise the max voltage of DCDC2 in sun8i reference tablets

[Icenowy Zheng]

The "extremity_freq" frequency described in the original FEX files uses
a voltage of 1.46v, which is beyond the current maximum voltage value of
DCDC2 (Cortex-A7 supply) in the sun8i reference tablet DTSI file.

Raise the maximum value to 1.46v.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
index 7ac8bb4bc95a..325ca5bd67a5 100644
--- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
@@ -180,7 +180,7 @@
 &reg_dcdc2 {
 	regulator-always-on;
 	regulator-min-microvolt = <900000>;
-	regulator-max-microvolt = <1400000>;
+	regulator-max-microvolt = <1460000>;
 	regulator-name = "vdd-sys";
 };
 
-- 
2.11.0

Re: [PATCH 1/6] clk: sunxi-ng: fix PLL_CPUX adjusting on A33

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 462 bytes --]

On Tue, Dec 13, 2016 at 11:22:47PM +0800, Icenowy Zheng wrote:
> When adjusting PLL_CPUX on A33, the PLL is temporarily driven too high,
> and the system hangs.
> 
> Add a notifier to avoid this situation by temporarily switching to a
> known stable 24 MHz oscillator.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]

Re: [PATCH 2/6] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 481 bytes --]

On Tue, Dec 13, 2016 at 11:22:48PM +0800, Icenowy Zheng wrote:
> The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
> be changeable by changing the rate of PLL_CPUX.
> 
> Add CLK_SET_RATE_PARENT flag to this clock.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]

Re: [PATCH 3/6] ARM: dts: sun8i: add a cpu0 label to cpu@0 node on A23/33

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 388 bytes --]

On Tue, Dec 13, 2016 at 11:22:49PM +0800, Icenowy Zheng wrote:
> A "cpu0" label is needed on cpu@0 for cpufreq-dt to work.
> 
> Add such a label, in order to prepare for cpufreq support of A23/33.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]

Re: [PATCH 3/6] ARM: dts: sun8i: add a cpu0 label to cpu@0 node on A23/33

[Sudeep Holla]

On 13/12/16 15:22, Icenowy Zheng wrote:
> A "cpu0" label is needed on cpu@0 for cpufreq-dt to work.
> 

IIUC any label should be fine and I don't see anything in the driver
looking for such label name. All I see is it looks for cpu0 regulator
for *legacy* DTs

> Add such a label, in order to prepare for cpufreq support of A23/33.
> 

You need this as you add the same label in the following patches. The
commit message sounds like cpufreq-dt search for that label by name.

-- 
Regards,
Sudeep

Re: [PATCH 3/6] ARM: dts: sun8i: add a cpu0 label to cpu@0 node on A23/33

[Chen-Yu Tsai]

On Wed, Dec 14, 2016 at 12:09 AM, Sudeep Holla <sudeep.holla@arm.com> wrote:
>
>
> On 13/12/16 15:22, Icenowy Zheng wrote:
>> A "cpu0" label is needed on cpu@0 for cpufreq-dt to work.
>>
>
> IIUC any label should be fine and I don't see anything in the driver
> looking for such label name. All I see is it looks for cpu0 regulator
> for *legacy* DTs
>
>> Add such a label, in order to prepare for cpufreq support of A23/33.
>>
>
> You need this as you add the same label in the following patches. The
> commit message sounds like cpufreq-dt search for that label by name.

I think a more proper explanation would be:

The cpu's supply regulator is specified at the board level, hence we
need to add a label to it to reference it without replicating the whole
tree structure.

ChenYu

Re: [PATCH 3/6] ARM: dts: sun8i: add a cpu0 label to cpu@0 node on A23/33

[Sudeep Holla]

On 13/12/16 16:31, Chen-Yu Tsai wrote:
> On Wed, Dec 14, 2016 at 12:09 AM, Sudeep Holla <sudeep.holla@arm.com> wrote:
>>
>>
>> On 13/12/16 15:22, Icenowy Zheng wrote:
>>> A "cpu0" label is needed on cpu@0 for cpufreq-dt to work.
>>>
>>
>> IIUC any label should be fine and I don't see anything in the driver
>> looking for such label name. All I see is it looks for cpu0 regulator
>> for *legacy* DTs
>>
>>> Add such a label, in order to prepare for cpufreq support of A23/33.
>>>
>>
>> You need this as you add the same label in the following patches. The
>> commit message sounds like cpufreq-dt search for that label by name.
> 
> I think a more proper explanation would be:
> 
> The cpu's supply regulator is specified at the board level, hence we
> need to add a label to it to reference it without replicating the whole
> tree structure.

Thanks for clarifying, was confused based on the commit log.

-- 
Regards,
Sudeep

Re: [PATCH 4/6] ARM: dts: sun8i: add opp-v2 table for A33

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 2286 bytes --]

On Tue, Dec 13, 2016 at 11:22:50PM +0800, Icenowy Zheng wrote:
> An operating point table is needed for the cpu frequency adjusting to
> work.
> 
> The operating point table is converted from the common value in
> extracted script.fex from many A33 board/tablets.
> 
> 1.344GHz is set as a turbo-mode operating point, as it's described as
> "extremity_freq" in the FEX file. (the "max_freq" is 1.2GHz)
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
>  arch/arm/boot/dts/sun8i-a33.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
> index 504996cbee29..035c058324b8 100644
> --- a/arch/arm/boot/dts/sun8i-a33.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a33.dtsi
> @@ -46,7 +46,45 @@
>  #include <dt-bindings/dma/sun4i-a10.h>
>  
>  / {
> +	cpu0_opp_table: opp_table0 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp@648000000 {
> +			opp-hz = /bits/ 64 <648000000>;
> +			opp-microvolt = <1040000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};

Please add new lines between the nodes.

> +		opp@816000000 {
> +			opp-hz = /bits/ 64 <816000000>;
> +			opp-microvolt = <1100000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp@1008000000 {
> +			opp-hz = /bits/ 64 <1008000000>;
> +			opp-microvolt = <1200000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp@1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <1320000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp@1344000000 {
> +			opp-hz = /bits/ 64 <1344000000>;
> +			opp-microvolt = <1460000>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +			turbo-mode;
> +		};

As far as I know, this OPP is not used by Allwinner, is not usable in
any A33 board so far (both the A33-olinuxino and the SinA33 do not
allow such a voltage on their CPU regulator), and overvolting and
overclocking is something that is very risky, and might lead to
stability issues.

Please remove this OPP.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]

Re: [PATCH 5/6] ARM: dts: sun8i: set cpu-supply in reference tablet DTSI

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 422 bytes --]

On Tue, Dec 13, 2016 at 11:22:51PM +0800, Icenowy Zheng wrote:
> All reference design A33 tablets uses DCDC2 of AXP223 as the power
> supply of the Cortex-A7 cores.
> 
> Set the cpu-supply in the DTSI of sun8i reference tablets.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Applied, thanks

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]

Re: [PATCH 6/6] ARM: dts: sun8i: raise the max voltage of DCDC2 in sun8i reference tablets

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1168 bytes --]

On Tue, Dec 13, 2016 at 11:22:52PM +0800, Icenowy Zheng wrote:
> The "extremity_freq" frequency described in the original FEX files uses
> a voltage of 1.46v, which is beyond the current maximum voltage value of
> DCDC2 (Cortex-A7 supply) in the sun8i reference tablet DTSI file.
> 
> Raise the maximum value to 1.46v.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
>  arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
> index 7ac8bb4bc95a..325ca5bd67a5 100644
> --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
> +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
> @@ -180,7 +180,7 @@
>  &reg_dcdc2 {
>  	regulator-always-on;
>  	regulator-min-microvolt = <900000>;
> -	regulator-max-microvolt = <1400000>;
> +	regulator-max-microvolt = <1460000>;

This is outside of the voltage range tolerated by the CPU. NAK.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]

Re: [PATCH 4/6] ARM: dts: sun8i: add opp-v2 table for A33

[Icenowy Zheng]

CjIwMTblubQxMuaciDE05pelIDAzOjEy5LqOIE1heGltZSBSaXBhcmQgPG1heGltZS5yaXBhcmRA
ZnJlZS1lbGVjdHJvbnMuY29tPuWGmemBk++8mgo+Cj4gT24gVHVlLCBEZWMgMTMsIDIwMTYgYXQg
MTE6MjI6NTBQTSArMDgwMCwgSWNlbm93eSBaaGVuZyB3cm90ZTogCj4gPiBBbiBvcGVyYXRpbmcg
cG9pbnQgdGFibGUgaXMgbmVlZGVkIGZvciB0aGUgY3B1IGZyZXF1ZW5jeSBhZGp1c3RpbmcgdG8g
Cj4gPiB3b3JrLiAKPiA+IAo+ID4gVGhlIG9wZXJhdGluZyBwb2ludCB0YWJsZSBpcyBjb252ZXJ0
ZWQgZnJvbSB0aGUgY29tbW9uIHZhbHVlIGluIAo+ID4gZXh0cmFjdGVkIHNjcmlwdC5mZXggZnJv
bSBtYW55IEEzMyBib2FyZC90YWJsZXRzLiAKPiA+IAo+ID4gMS4zNDRHSHogaXMgc2V0IGFzIGEg
dHVyYm8tbW9kZSBvcGVyYXRpbmcgcG9pbnQsIGFzIGl0J3MgZGVzY3JpYmVkIGFzIAo+ID4gImV4
dHJlbWl0eV9mcmVxIiBpbiB0aGUgRkVYIGZpbGUuICh0aGUgIm1heF9mcmVxIiBpcyAxLjJHSHop
IAo+ID4gCj4gPiBTaWduZWQtb2ZmLWJ5OiBJY2Vub3d5IFpoZW5nIDxpY2Vub3d5QGFvc2MueHl6
PiAKPiA+IC0tLSAKPiA+wqAgYXJjaC9hcm0vYm9vdC9kdHMvc3VuOGktYTMzLmR0c2kgfCAzOCAr
KysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKyAKPiA+wqAgMSBmaWxlIGNoYW5n
ZWQsIDM4IGluc2VydGlvbnMoKykgCj4gPiAKPiA+IGRpZmYgLS1naXQgYS9hcmNoL2FybS9ib290
L2R0cy9zdW44aS1hMzMuZHRzaSBiL2FyY2gvYXJtL2Jvb3QvZHRzL3N1bjhpLWEzMy5kdHNpIAo+
ID4gaW5kZXggNTA0OTk2Y2JlZTI5Li4wMzVjMDU4MzI0YjggMTAwNjQ0IAo+ID4gLS0tIGEvYXJj
aC9hcm0vYm9vdC9kdHMvc3VuOGktYTMzLmR0c2kgCj4gPiArKysgYi9hcmNoL2FybS9ib290L2R0
cy9zdW44aS1hMzMuZHRzaSAKPiA+IEBAIC00Niw3ICs0Niw0NSBAQCAKPiA+wqAgI2luY2x1ZGUg
PGR0LWJpbmRpbmdzL2RtYS9zdW40aS1hMTAuaD4gCj4gPsKgIAo+ID7CoCAvIHsgCj4gPiArIGNw
dTBfb3BwX3RhYmxlOiBvcHBfdGFibGUwIHsgCj4gPiArIGNvbXBhdGlibGUgPSAib3BlcmF0aW5n
LXBvaW50cy12MiI7IAo+ID4gKyBvcHAtc2hhcmVkOyAKPiA+ICsgCj4gPiArIG9wcEA2NDgwMDAw
MDAgeyAKPiA+ICsgb3BwLWh6ID0gL2JpdHMvIDY0IDw2NDgwMDAwMDA+OyAKPiA+ICsgb3BwLW1p
Y3Jvdm9sdCA9IDwxMDQwMDAwPjsgCj4gPiArIGNsb2NrLWxhdGVuY3ktbnMgPSA8MjQ0MTQ0Pjsg
LyogOCAzMmsgcGVyaW9kcyAqLyAKPiA+ICsgfTsgCj4KPiBQbGVhc2UgYWRkIG5ldyBsaW5lcyBi
ZXR3ZWVuIHRoZSBub2Rlcy4gCj4KPiA+ICsgb3BwQDgxNjAwMDAwMCB7IAo+ID4gKyBvcHAtaHog
PSAvYml0cy8gNjQgPDgxNjAwMDAwMD47IAo+ID4gKyBvcHAtbWljcm92b2x0ID0gPDExMDAwMDA+
OyAKPiA+ICsgY2xvY2stbGF0ZW5jeS1ucyA9IDwyNDQxNDQ+OyAvKiA4IDMyayBwZXJpb2RzICov
IAo+ID4gKyB9OyAKPiA+ICsgb3BwQDEwMDgwMDAwMDAgeyAKPiA+ICsgb3BwLWh6ID0gL2JpdHMv
IDY0IDwxMDA4MDAwMDAwPjsgCj4gPiArIG9wcC1taWNyb3ZvbHQgPSA8MTIwMDAwMD47IAo+ID4g
KyBjbG9jay1sYXRlbmN5LW5zID0gPDI0NDE0ND47IC8qIDggMzJrIHBlcmlvZHMgKi8gCj4gPiAr
IH07IAo+ID4gKyBvcHBAMTIwMDAwMDAwMCB7IAo+ID4gKyBvcHAtaHogPSAvYml0cy8gNjQgPDEy
MDAwMDAwMDA+OyAKPiA+ICsgb3BwLW1pY3Jvdm9sdCA9IDwxMzIwMDAwPjsgCj4gPiArIGNsb2Nr
LWxhdGVuY3ktbnMgPSA8MjQ0MTQ0PjsgLyogOCAzMmsgcGVyaW9kcyAqLyAKPiA+ICsgfTsgCj4g
PiArIG9wcEAxMzQ0MDAwMDAwIHsgCj4gPiArIG9wcC1oeiA9IC9iaXRzLyA2NCA8MTM0NDAwMDAw
MD47IAo+ID4gKyBvcHAtbWljcm92b2x0ID0gPDE0NjAwMDA+OyAKPiA+ICsgY2xvY2stbGF0ZW5j
eS1ucyA9IDwyNDQxNDQ+OyAvKiA4IDMyayBwZXJpb2RzICovIAo+ID4gKyB0dXJiby1tb2RlOyAK
PiA+ICsgfTsgCj4KPiBBcyBmYXIgYXMgSSBrbm93LCB0aGlzIE9QUCBpcyBub3QgdXNlZCBieSBB
bGx3aW5uZXIsIGlzIG5vdCB1c2FibGUgaW4gCj4gYW55IEEzMyBib2FyZCBzbyBmYXIgKGJvdGgg
dGhlIEEzMy1vbGludXhpbm8gYW5kIHRoZSBTaW5BMzMgZG8gbm90IAo+IGFsbG93IHN1Y2ggYSB2
b2x0YWdlIG9uIHRoZWlyIENQVSByZWd1bGF0b3IpLCBhbmQgb3ZlcnZvbHRpbmcgYW5kIAo+IG92
ZXJjbG9ja2luZyBpcyBzb21ldGhpbmcgdGhhdCBpcyB2ZXJ5IHJpc2t5LCBhbmQgbWlnaHQgbGVh
ZCB0byAKPiBzdGFiaWxpdHkgaXNzdWVzLiAKCkl0IGNhbiBiZSB1c2VkIG9uIG15IEEzMyB0YWJs
ZXQsIGFsdGhvdWdoIG5vdCBmb3IgbG9uZy10ZXJtIHJ1bi4KCkFuZCBpdCdzIGRlc2lnbmVkIHRv
IGJlICJ0dXJiby1tb2RlIiwgd2hpY2ggaXMgdGhlIHJlYXNvbiB0aGF0IEkgYWRkIHRoaXMgcHJv
cGVydHkuCgo+Cj4gUGxlYXNlIHJlbW92ZSB0aGlzIE9QUC4gCj4KPiBNYXhpbWUgCj4KPiAtLSAK
PiBNYXhpbWUgUmlwYXJkLCBGcmVlIEVsZWN0cm9ucyAKPiBFbWJlZGRlZCBMaW51eCBhbmQgS2Vy
bmVsIGVuZ2luZWVyaW5nIAo+IGh0dHA6Ly9mcmVlLWVsZWN0cm9ucy5jb20gCg==

Re: [PATCH 4/6] ARM: dts: sun8i: add opp-v2 table for A33

[Icenowy Zheng]

CjIwMTblubQxMuaciDE05pelIDAzOjEy5LqOIE1heGltZSBSaXBhcmQgPG1heGltZS5yaXBhcmRA
ZnJlZS1lbGVjdHJvbnMuY29tPuWGmemBk++8mgo+Cj4gT24gVHVlLCBEZWMgMTMsIDIwMTYgYXQg
MTE6MjI6NTBQTSArMDgwMCwgSWNlbm93eSBaaGVuZyB3cm90ZTogCj4gPiBBbiBvcGVyYXRpbmcg
cG9pbnQgdGFibGUgaXMgbmVlZGVkIGZvciB0aGUgY3B1IGZyZXF1ZW5jeSBhZGp1c3RpbmcgdG8g
Cj4gPiB3b3JrLiAKPiA+IAo+ID4gVGhlIG9wZXJhdGluZyBwb2ludCB0YWJsZSBpcyBjb252ZXJ0
ZWQgZnJvbSB0aGUgY29tbW9uIHZhbHVlIGluIAo+ID4gZXh0cmFjdGVkIHNjcmlwdC5mZXggZnJv
bSBtYW55IEEzMyBib2FyZC90YWJsZXRzLiAKPiA+IAo+ID4gMS4zNDRHSHogaXMgc2V0IGFzIGEg
dHVyYm8tbW9kZSBvcGVyYXRpbmcgcG9pbnQsIGFzIGl0J3MgZGVzY3JpYmVkIGFzIAo+ID4gImV4
dHJlbWl0eV9mcmVxIiBpbiB0aGUgRkVYIGZpbGUuICh0aGUgIm1heF9mcmVxIiBpcyAxLjJHSHop
IAo+ID4gCj4gPiBTaWduZWQtb2ZmLWJ5OiBJY2Vub3d5IFpoZW5nIDxpY2Vub3d5QGFvc2MueHl6
PiAKPiA+IC0tLSAKPiA+wqAgYXJjaC9hcm0vYm9vdC9kdHMvc3VuOGktYTMzLmR0c2kgfCAzOCAr
KysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKyAKPiA+wqAgMSBmaWxlIGNoYW5n
ZWQsIDM4IGluc2VydGlvbnMoKykgCj4gPiAKPiA+IGRpZmYgLS1naXQgYS9hcmNoL2FybS9ib290
L2R0cy9zdW44aS1hMzMuZHRzaSBiL2FyY2gvYXJtL2Jvb3QvZHRzL3N1bjhpLWEzMy5kdHNpIAo+
ID4gaW5kZXggNTA0OTk2Y2JlZTI5Li4wMzVjMDU4MzI0YjggMTAwNjQ0IAo+ID4gLS0tIGEvYXJj
aC9hcm0vYm9vdC9kdHMvc3VuOGktYTMzLmR0c2kgCj4gPiArKysgYi9hcmNoL2FybS9ib290L2R0
cy9zdW44aS1hMzMuZHRzaSAKPiA+IEBAIC00Niw3ICs0Niw0NSBAQCAKPiA+wqAgI2luY2x1ZGUg
PGR0LWJpbmRpbmdzL2RtYS9zdW40aS1hMTAuaD4gCj4gPsKgIAo+ID7CoCAvIHsgCj4gPiArIGNw
dTBfb3BwX3RhYmxlOiBvcHBfdGFibGUwIHsgCj4gPiArIGNvbXBhdGlibGUgPSAib3BlcmF0aW5n
LXBvaW50cy12MiI7IAo+ID4gKyBvcHAtc2hhcmVkOyAKPiA+ICsgCj4gPiArIG9wcEA2NDgwMDAw
MDAgeyAKPiA+ICsgb3BwLWh6ID0gL2JpdHMvIDY0IDw2NDgwMDAwMDA+OyAKPiA+ICsgb3BwLW1p
Y3Jvdm9sdCA9IDwxMDQwMDAwPjsgCj4gPiArIGNsb2NrLWxhdGVuY3ktbnMgPSA8MjQ0MTQ0Pjsg
LyogOCAzMmsgcGVyaW9kcyAqLyAKPiA+ICsgfTsgCj4KPiBQbGVhc2UgYWRkIG5ldyBsaW5lcyBi
ZXR3ZWVuIHRoZSBub2Rlcy4gCj4KPiA+ICsgb3BwQDgxNjAwMDAwMCB7IAo+ID4gKyBvcHAtaHog
PSAvYml0cy8gNjQgPDgxNjAwMDAwMD47IAo+ID4gKyBvcHAtbWljcm92b2x0ID0gPDExMDAwMDA+
OyAKPiA+ICsgY2xvY2stbGF0ZW5jeS1ucyA9IDwyNDQxNDQ+OyAvKiA4IDMyayBwZXJpb2RzICov
IAo+ID4gKyB9OyAKPiA+ICsgb3BwQDEwMDgwMDAwMDAgeyAKPiA+ICsgb3BwLWh6ID0gL2JpdHMv
IDY0IDwxMDA4MDAwMDAwPjsgCj4gPiArIG9wcC1taWNyb3ZvbHQgPSA8MTIwMDAwMD47IAo+ID4g
KyBjbG9jay1sYXRlbmN5LW5zID0gPDI0NDE0ND47IC8qIDggMzJrIHBlcmlvZHMgKi8gCj4gPiAr
IH07IAo+ID4gKyBvcHBAMTIwMDAwMDAwMCB7IAo+ID4gKyBvcHAtaHogPSAvYml0cy8gNjQgPDEy
MDAwMDAwMDA+OyAKPiA+ICsgb3BwLW1pY3Jvdm9sdCA9IDwxMzIwMDAwPjsgCj4gPiArIGNsb2Nr
LWxhdGVuY3ktbnMgPSA8MjQ0MTQ0PjsgLyogOCAzMmsgcGVyaW9kcyAqLyAKPiA+ICsgfTsgCj4g
PiArIG9wcEAxMzQ0MDAwMDAwIHsgCj4gPiArIG9wcC1oeiA9IC9iaXRzLyA2NCA8MTM0NDAwMDAw
MD47IAo+ID4gKyBvcHAtbWljcm92b2x0ID0gPDE0NjAwMDA+OyAKPiA+ICsgY2xvY2stbGF0ZW5j
eS1ucyA9IDwyNDQxNDQ+OyAvKiA4IDMyayBwZXJpb2RzICovIAo+ID4gKyB0dXJiby1tb2RlOyAK
PiA+ICsgfTsgCj4KPiBBcyBmYXIgYXMgSSBrbm93LCB0aGlzIE9QUCBpcyBub3QgdXNlZCBieSBB
bGx3aW5uZXIsIGlzIG5vdCB1c2FibGUgaW4gCj4gYW55IEEzMyBib2FyZCBzbyBmYXIgKGJvdGgg
dGhlIEEzMy1vbGludXhpbm8gYW5kIHRoZSBTaW5BMzMgZG8gbm90IAo+IGFsbG93IHN1Y2ggYSB2
b2x0YWdlIG9uIHRoZWlyIENQVSByZWd1bGF0b3IpLCBhbmQgb3ZlcnZvbHRpbmcgYW5kIAo+IG92
ZXJjbG9ja2luZyBpcyBzb21ldGhpbmcgdGhhdCBpcyB2ZXJ5IHJpc2t5LCBhbmQgbWlnaHQgbGVh
ZCB0byAKPiBzdGFiaWxpdHkgaXNzdWVzLiAKPgo+IFBsZWFzZSByZW1vdmUgdGhpcyBPUFAuIAoK
U29ycnksIHJlY2hlY2tlZCB1bmRlciBBbmRyb2lkIGFuZCBmb3VuZCB0aGlzIGZyZXFlbmN5IG5v
dCB1c2FibGUgd2hpbGUgZXhpc3RzLgoKV2lsbCByZW1vdmUgdGhpcyBPUFAuCgo+Cj4gTWF4aW1l
IAo+Cj4gLS0gCj4gTWF4aW1lIFJpcGFyZCwgRnJlZSBFbGVjdHJvbnMgCj4gRW1iZWRkZWQgTGlu
dXggYW5kIEtlcm5lbCBlbmdpbmVlcmluZyAKPiBodHRwOi8vZnJlZS1lbGVjdHJvbnMuY29tIAo=

Re: [PATCH 2/6] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33

[Icenowy Zheng]

13.12.2016, 23:44, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> On Tue, Dec 13, 2016 at 11:22:48PM +0800, Icenowy Zheng wrote:
>>  The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
>>  be changeable by changing the rate of PLL_CPUX.
>>
>>  Add CLK_SET_RATE_PARENT flag to this clock.
>>
>>  Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Excuse me, have you merged this patch?

If merged, I won't contain it in my PATCH v2, thus the PATCH v2 will contain
only an updated OPP patch.

>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com

Re: [PATCH 2/6] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 733 bytes --]

On Wed, Dec 14, 2016 at 04:54:14AM +0800, Icenowy Zheng wrote:
> 
> 
> 13.12.2016, 23:44, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> > On Tue, Dec 13, 2016 at 11:22:48PM +0800, Icenowy Zheng wrote:
> >>  The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
> >>  be changeable by changing the rate of PLL_CPUX.
> >>
> >>  Add CLK_SET_RATE_PARENT flag to this clock.
> >>
> >>  Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >
> > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Excuse me, have you merged this patch?

Yes, sorry, that's what I meant :)

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]