[PATCHv2 0/5] Support for Marvell switches with integrated CPUs

[PATCHv2 0/5] Support for Marvell switches with integrated CPUs

[Chris Packham]

The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
integrated CPUs. They CPU block is common within these product lines and
(as far as I can tell/have been told) is based on the Armada XP. There
are a few differences due to the fact they have to squeeze the CPU into
the same package as the switch.

Chris Packham (4):
  clk: mvebu: support for 98DX3236 SoC
  arm: mvebu: support for SMP on 98DX3336 SoC
  arm: mvebu: Add device tree for 98DX3236 SoCs
  arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards

Kalyan Kinthada (1):
  pinctrl: mvebu: pinctrl driver for 98DX3236 SoC

 Documentation/devicetree/bindings/arm/cpus.txt     |   1 +
 .../bindings/arm/marvell/98dx3236-resume-ctrl.txt  |  18 ++
 .../devicetree/bindings/arm/marvell/98dx3236.txt   |  23 ++
 .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |   1 +
 .../pinctrl/marvell,armada-98dx3236-pinctrl.txt    |  46 ++++
 arch/arm/boot/dts/armada-xp-98dx3236.dtsi          | 247 +++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-98dx3336.dtsi          |  78 +++++++
 arch/arm/boot/dts/armada-xp-98dx4251.dtsi          |  92 ++++++++
 arch/arm/boot/dts/db-dxbc2.dts                     | 159 +++++++++++++
 arch/arm/boot/dts/db-xc3-24g4xg.dts                | 155 +++++++++++++
 arch/arm/mach-mvebu/Makefile                       |   1 +
 arch/arm/mach-mvebu/common.h                       |   1 +
 arch/arm/mach-mvebu/platsmp.c                      |  43 ++++
 arch/arm/mach-mvebu/pmsu-98dx3236.c                |  69 ++++++
 drivers/clk/mvebu/Makefile                         |   2 +-
 drivers/clk/mvebu/armada-xp.c                      |  42 ++++
 drivers/clk/mvebu/clk-cpu.c                        |  33 ++-
 drivers/clk/mvebu/mv98dx3236-corediv.c             | 207 +++++++++++++++++
 drivers/pinctrl/mvebu/pinctrl-armada-xp.c          | 155 +++++++++++++
 19 files changed, 1369 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
 create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
 create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
 create mode 100644 arch/arm/mach-mvebu/pmsu-98dx3236.c
 create mode 100644 drivers/clk/mvebu/mv98dx3236-corediv.c

-- 
2.11.0.24.ge6920cf

[PATCHv2 1/5] clk: mvebu: support for 98DX3236 SoC

[Chris Packham]

The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.

The clock gating options are a subset of those on the Armada XP.

The core clock divider is different to the Armada XP also.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Changes in v2:
- Update devicetree binding documentation for new compatible string

 .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |   1 +
 drivers/clk/mvebu/Makefile                         |   2 +-
 drivers/clk/mvebu/armada-xp.c                      |  42 +++++
 drivers/clk/mvebu/clk-cpu.c                        |  33 +++-
 drivers/clk/mvebu/mv98dx3236-corediv.c             | 207 +++++++++++++++++++++
 5 files changed, 281 insertions(+), 4 deletions(-)
 create mode 100644 drivers/clk/mvebu/mv98dx3236-corediv.c

diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
index 99c214660bdc..7f28506eaee7 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
@@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
 Required properties:
 - compatible : shall be one of the following:
 	"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
+	"marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
 - reg : Address and length of the clock complex register set, followed
         by address and length of the PMU DFS registers
 - #clock-cells : should be set to 1.
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index d9ae97fb43c4..6a3681e3d6db 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_ARMADA_39X_CLK)	+= armada-39x.o
 obj-$(CONFIG_ARMADA_37XX_CLK)	+= armada-37xx-xtal.o
 obj-$(CONFIG_ARMADA_37XX_CLK)	+= armada-37xx-tbg.o
 obj-$(CONFIG_ARMADA_37XX_CLK)	+= armada-37xx-periph.o
-obj-$(CONFIG_ARMADA_XP_CLK)	+= armada-xp.o
+obj-$(CONFIG_ARMADA_XP_CLK)	+= armada-xp.o mv98dx3236-corediv.o
 obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o
 obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o
 obj-$(CONFIG_DOVE_CLK)		+= dove.o dove-divider.o
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
index b3094315a3c0..0413bf8284e0 100644
--- a/drivers/clk/mvebu/armada-xp.c
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -52,6 +52,12 @@ static u32 __init axp_get_tclk_freq(void __iomem *sar)
 	return 250000000;
 }
 
+/* MV98DX3236 TCLK frequency is fixed to 200MHz */
+static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar)
+{
+	return 200000000;
+}
+
 static const u32 axp_cpu_freqs[] __initconst = {
 	1000000000,
 	1066000000,
@@ -89,6 +95,12 @@ static u32 __init axp_get_cpu_freq(void __iomem *sar)
 	return cpu_freq;
 }
 
+/* MV98DX3236 CLK frequency is fixed to 800MHz */
+static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar)
+{
+	return 800000000;
+}
+
 static const int axp_nbclk_ratios[32][2] __initconst = {
 	{0, 1}, {1, 2}, {2, 2}, {2, 2},
 	{1, 2}, {1, 2}, {1, 1}, {2, 3},
@@ -158,6 +170,14 @@ static const struct coreclk_soc_desc axp_coreclks = {
 	.num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
 };
 
+static const struct coreclk_soc_desc mv98dx3236_coreclks = {
+	.get_tclk_freq = mv98dx3236_get_tclk_freq,
+	.get_cpu_freq = mv98dx3236_get_cpu_freq,
+	.get_clk_ratio = NULL,
+	.ratios = NULL,
+	.num_ratios = 0,
+};
+
 /*
  * Clock Gating Control
  */
@@ -195,6 +215,15 @@ static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
 	{ }
 };
 
+static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {
+	{ "ge1", NULL, 3, 0 },
+	{ "ge0", NULL, 4, 0 },
+	{ "pex00", NULL, 5, 0 },
+	{ "sdio", NULL, 17, 0 },
+	{ "xor0", NULL, 22, 0 },
+	{ }
+};
+
 static void __init axp_clk_init(struct device_node *np)
 {
 	struct device_node *cgnp =
@@ -206,3 +235,16 @@ static void __init axp_clk_init(struct device_node *np)
 		mvebu_clk_gating_setup(cgnp, axp_gating_desc);
 }
 CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);
+
+static void __init mv98dx3236_clk_init(struct device_node *np)
+{
+	struct device_node *cgnp =
+		of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
+
+	mvebu_coreclk_setup(np, &mv98dx3236_coreclks);
+
+	if (cgnp)
+		mvebu_clk_gating_setup(cgnp, mv98dx3236_gating_desc);
+}
+CLK_OF_DECLARE(mv98dx3236_clk, "marvell,mv98dx3236-core-clock",
+	       mv98dx3236_clk_init);
diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
index 5837eb8a212f..29f295e7a36b 100644
--- a/drivers/clk/mvebu/clk-cpu.c
+++ b/drivers/clk/mvebu/clk-cpu.c
@@ -165,7 +165,9 @@ static const struct clk_ops cpu_ops = {
 	.set_rate = clk_cpu_set_rate,
 };
 
-static void __init of_cpu_clk_setup(struct device_node *node)
+/* Add parameter to allow this to support different clock operations. */
+static void __init _of_cpu_clk_setup(struct device_node *node,
+			const struct clk_ops *cpu_clk_ops)
 {
 	struct cpu_clk *cpuclk;
 	void __iomem *clock_complex_base = of_iomap(node, 0);
@@ -218,7 +220,7 @@ static void __init of_cpu_clk_setup(struct device_node *node)
 		cpuclk[cpu].hw.init = &init;
 
 		init.name = cpuclk[cpu].clk_name;
-		init.ops = &cpu_ops;
+		init.ops = cpu_clk_ops;
 		init.flags = 0;
 		init.parent_names = &cpuclk[cpu].parent_name;
 		init.num_parents = 1;
@@ -243,5 +245,30 @@ static void __init of_cpu_clk_setup(struct device_node *node)
 	iounmap(clock_complex_base);
 }
 
+/* Use this function to call the generic setup with the correct
+ * clock operation
+ */
+static void __init of_cpu_clk_setup(struct device_node *node)
+{
+	_of_cpu_clk_setup(node, &cpu_ops);
+}
+
 CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
-					 of_cpu_clk_setup);
+					of_cpu_clk_setup);
+
+/* Define the clock and operations for the mv98dx3236 - it cannot perform
+ * any operations.
+ */
+static const struct clk_ops mv98dx3236_cpu_ops = {
+	.recalc_rate = NULL,
+	.round_rate = NULL,
+	.set_rate = NULL,
+};
+
+static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
+{
+	_of_cpu_clk_setup(node, &mv98dx3236_cpu_ops);
+}
+
+CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
+					 of_mv98dx3236_cpu_clk_setup);
diff --git a/drivers/clk/mvebu/mv98dx3236-corediv.c b/drivers/clk/mvebu/mv98dx3236-corediv.c
new file mode 100644
index 000000000000..3060764a8e5d
--- /dev/null
+++ b/drivers/clk/mvebu/mv98dx3236-corediv.c
@@ -0,0 +1,207 @@
+/*
+ * MV98DX3236 Core divider clock
+ *
+ * Copyright (C) 2015 Allied Telesis Labs
+ *
+ * Based on armada-xp-corediv.c
+ * Copyright (C) 2015 Marvell
+ *
+ * John Thompson <john.thompson@alliedtelesis.co.nz>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include "common.h"
+
+#define CORE_CLK_DIV_RATIO_MASK		0xff
+
+#define CLK_DIV_RATIO_NAND_MASK 0x0f
+#define CLK_DIV_RATIO_NAND_OFFSET 6
+#define CLK_DIV_RATIO_NAND_FORCE_RELOAD_BIT 26
+
+#define RATIO_RELOAD_BIT BIT(10)
+#define RATIO_REG_OFFSET 0x08
+
+/*
+ * This structure represents one core divider clock for the clock
+ * framework, and is dynamically allocated for each core divider clock
+ * existing in the current SoC.
+ */
+struct clk_corediv {
+	struct clk_hw hw;
+	void __iomem *reg;
+	spinlock_t lock;
+};
+
+static struct clk_onecell_data clk_data;
+
+
+#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
+
+static int mv98dx3236_corediv_is_enabled(struct clk_hw *hwclk)
+{
+	/* Core divider is always active */
+	return 1;
+}
+
+static int mv98dx3236_corediv_enable(struct clk_hw *hwclk)
+{
+	/* always succeeds */
+	return 0;
+}
+
+static void mv98dx3236_corediv_disable(struct clk_hw *hwclk)
+{
+	/* can't be disabled so is left alone */
+}
+
+static unsigned long mv98dx3236_corediv_recalc_rate(struct clk_hw *hwclk,
+					 unsigned long parent_rate)
+{
+	struct clk_corediv *corediv = to_corediv_clk(hwclk);
+	u32 reg, div;
+
+	reg = readl(corediv->reg + RATIO_REG_OFFSET);
+	div = (reg >> CLK_DIV_RATIO_NAND_OFFSET) & CLK_DIV_RATIO_NAND_MASK;
+	return parent_rate / div;
+}
+
+static long mv98dx3236_corediv_round_rate(struct clk_hw *hwclk,
+			       unsigned long rate, unsigned long *parent_rate)
+{
+	/* Valid ratio are 1:4, 1:5, 1:6 and 1:8 */
+	u32 div;
+
+	div = *parent_rate / rate;
+	if (div < 4)
+		div = 4;
+	else if (div > 6)
+		div = 8;
+
+	return *parent_rate / div;
+}
+
+static int mv98dx3236_corediv_set_rate(struct clk_hw *hwclk, unsigned long rate,
+			    unsigned long parent_rate)
+{
+	struct clk_corediv *corediv = to_corediv_clk(hwclk);
+	unsigned long flags = 0;
+	u32 reg, div;
+
+	div = parent_rate / rate;
+
+	spin_lock_irqsave(&corediv->lock, flags);
+
+	/* Write new divider to the divider ratio register */
+	reg = readl(corediv->reg + RATIO_REG_OFFSET);
+	reg &= ~(CLK_DIV_RATIO_NAND_MASK << CLK_DIV_RATIO_NAND_OFFSET);
+	reg |= (div & CLK_DIV_RATIO_NAND_MASK) << CLK_DIV_RATIO_NAND_OFFSET;
+	writel(reg, corediv->reg + RATIO_REG_OFFSET);
+
+	/* Set reload-force for this clock */
+	reg = readl(corediv->reg) | BIT(CLK_DIV_RATIO_NAND_FORCE_RELOAD_BIT);
+	writel(reg, corediv->reg);
+
+	/* Now trigger the clock update */
+	reg = readl(corediv->reg + RATIO_REG_OFFSET) | RATIO_RELOAD_BIT;
+	writel(reg, corediv->reg + RATIO_REG_OFFSET);
+
+	/*
+	 * Wait for clocks to settle down, and then clear all the
+	 * ratios request and the reload request.
+	 */
+	udelay(1000);
+	reg &= ~(CORE_CLK_DIV_RATIO_MASK | RATIO_RELOAD_BIT);
+	writel(reg, corediv->reg + RATIO_REG_OFFSET);
+	udelay(1000);
+
+	spin_unlock_irqrestore(&corediv->lock, flags);
+
+	return 0;
+}
+
+static const struct clk_ops ops = {
+	.enable = mv98dx3236_corediv_enable,
+	.disable = mv98dx3236_corediv_disable,
+	.is_enabled = mv98dx3236_corediv_is_enabled,
+	.recalc_rate = mv98dx3236_corediv_recalc_rate,
+	.round_rate = mv98dx3236_corediv_round_rate,
+	.set_rate = mv98dx3236_corediv_set_rate,
+};
+
+static void __init mv98dx3236_corediv_clk_init(struct device_node *node)
+{
+	struct clk_init_data init;
+	struct clk_corediv *corediv;
+	struct clk **clks;
+	void __iomem *base;
+	const __be32 *off;
+	const char *parent_name;
+	const char *clk_name;
+	int len;
+	struct device_node *dfx_node;
+
+	dfx_node = of_parse_phandle(node, "base", 0);
+	if (WARN_ON(!dfx_node))
+		return;
+
+	off = of_get_property(node, "reg", &len);
+	if (WARN_ON(!off))
+		return;
+
+	base = of_iomap(dfx_node, 0);
+	if (WARN_ON(!base))
+		return;
+
+	of_node_put(dfx_node);
+
+	parent_name = of_clk_get_parent_name(node, 0);
+
+	clk_data.clk_num = 1;
+
+	/* clks holds the clock array */
+	clks = kcalloc(clk_data.clk_num, sizeof(struct clk *),
+				GFP_KERNEL);
+	if (WARN_ON(!clks))
+		goto err_unmap;
+	/* corediv holds the clock specific array */
+	corediv = kcalloc(clk_data.clk_num, sizeof(struct clk_corediv),
+				GFP_KERNEL);
+	if (WARN_ON(!corediv))
+		goto err_free_clks;
+
+	spin_lock_init(&corediv->lock);
+
+	of_property_read_string_index(node, "clock-output-names",
+					  0, &clk_name);
+
+	init.num_parents = 1;
+	init.parent_names = &parent_name;
+	init.name = clk_name;
+	init.ops = &ops;
+	init.flags = 0;
+
+	corediv[0].reg = (void *)((int)base + be32_to_cpu(*off));
+	corediv[0].hw.init = &init;
+
+	clks[0] = clk_register(NULL, &corediv[0].hw);
+	WARN_ON(IS_ERR(clks[0]));
+
+	clk_data.clks = clks;
+	of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
+	return;
+
+err_free_clks:
+	kfree(clks);
+err_unmap:
+	iounmap(base);
+}
+
+CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
+	       mv98dx3236_corediv_clk_init);
-- 
2.11.0.24.ge6920cf

Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs

[Florian Fainelli]

Le 01/04/17 à 19:36, Chris Packham a écrit :
> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
> integrated CPUs. They CPU block is common within these product lines and
> (as far as I can tell/have been told) is based on the Armada XP. There
> are a few differences due to the fact they have to squeeze the CPU into
> the same package as the switch.

It's really great to see these changes, do you have a plan to also add
support for the integrated switch using a DSA/switchdev driver?

Thanks!
-- 
Florian

Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs

[Chris Packham]

On 05/01/17 17:07, Florian Fainelli wrote:=0A=
> Le 01/04/17 =E0 19:36, Chris Packham a =E9crit :=0A=
>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with=0A=
>> integrated CPUs. They CPU block is common within these product lines and=
=0A=
>> (as far as I can tell/have been told) is based on the Armada XP. There=
=0A=
>> are a few differences due to the fact they have to squeeze the CPU into=
=0A=
>> the same package as the switch.=0A=
>=0A=
> It's really great to see these changes, do you have a plan to also add=0A=
> support for the integrated switch using a DSA/switchdev driver?=0A=
=0A=
I'd love to see a switchdev driver but it's a huge task (and no I'm not =0A=
committing to writing it). As it stands Marvell ship a switch SDK =0A=
largely executes in userspace with a small kernel module providing some =0A=
linkage to the underlying hardware.=0A=
=0A=
We (a few of us here at Allied Telesis NZ) have discussed switchdev and =0A=
how we get from using Marvell's SDK in our products to using switchdev =0A=
proper.=0A=
=0A=
The first step would probably be some kind of trampoline driver which =0A=
communicates with a userspace helper to do the actual work. =0A=
Alternatively there is some support in Marvell's SDK for compilation as =0A=
a binary blob so a proprietary kernel module is another option. Neither =0A=
of these are particularly nice in a free software world.=0A=
=0A=
A full "free" implementation would be a large undertaking. Ideally I'd =0A=
like to see Marvell involved with producing one but so far they've not =0A=
been interested whenever I've brought it up.=0A=
=0A=

Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs

[Andrew Lunn]

> I'd love to see a switchdev driver but it's a huge task (and no I'm not 
> committing to writing it). As it stands Marvell ship a switch SDK 
> largely executes in userspace with a small kernel module providing some 
> linkage to the underlying hardware.

Is there any similarity to the mv88e6xxx family?

If it was similar registers, just a different access mechanising, we
could probably extend the mv88e6xxx to support MMIO as well as MDIO.

   Andrew

Re: [PATCHv2 1/5] clk: mvebu: support for 98DX3236 SoC

[Mark Rutland]

On Thu, Jan 05, 2017 at 04:36:37PM +1300, Chris Packham wrote:
> The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
> the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
> 
> The clock gating options are a subset of those on the Armada XP.
> 
> The core clock divider is different to the Armada XP also.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
> Changes in v2:
> - Update devicetree binding documentation for new compatible string
> 
>  .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |   1 +
>  drivers/clk/mvebu/Makefile                         |   2 +-
>  drivers/clk/mvebu/armada-xp.c                      |  42 +++++
>  drivers/clk/mvebu/clk-cpu.c                        |  33 +++-
>  drivers/clk/mvebu/mv98dx3236-corediv.c             | 207 +++++++++++++++++++++
>  5 files changed, 281 insertions(+), 4 deletions(-)
>  create mode 100644 drivers/clk/mvebu/mv98dx3236-corediv.c


It looks like you also need to update
Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt for the
addition of "marvell,mv98dx3236-corediv-clock".

> 
> diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
> index 99c214660bdc..7f28506eaee7 100644
> --- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
> @@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
>  Required properties:
>  - compatible : shall be one of the following:
>  	"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
> +	"marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
>  - reg : Address and length of the clock complex register set, followed
>          by address and length of the PMU DFS registers
>  - #clock-cells : should be set to 1.

[...]

> +static void __init mv98dx3236_corediv_clk_init(struct device_node *node)
> +{
> +	struct clk_init_data init;
> +	struct clk_corediv *corediv;
> +	struct clk **clks;
> +	void __iomem *base;
> +	const __be32 *off;
> +	const char *parent_name;
> +	const char *clk_name;
> +	int len;
> +	struct device_node *dfx_node;
> +
> +	dfx_node = of_parse_phandle(node, "base", 0);
> +	if (WARN_ON(!dfx_node))

What's going on here? The existing bingings don't mention a "base"
phandle, and nothing was added to describe it.

> +		return;
> +
> +	off = of_get_property(node, "reg", &len);
> +	if (WARN_ON(!off))
> +		return;

Please don't use of_get_property directly; generally you should use the
existing higher-level helpers like of_proeprty_read_u32().

> +
> +	base = of_iomap(dfx_node, 0);
> +	if (WARN_ON(!base))
> +		return;
> +
> +	of_node_put(dfx_node);
> +
> +	parent_name = of_clk_get_parent_name(node, 0);
> +
> +	clk_data.clk_num = 1;
> +
> +	/* clks holds the clock array */
> +	clks = kcalloc(clk_data.clk_num, sizeof(struct clk *),
> +				GFP_KERNEL);
> +	if (WARN_ON(!clks))
> +		goto err_unmap;
> +	/* corediv holds the clock specific array */
> +	corediv = kcalloc(clk_data.clk_num, sizeof(struct clk_corediv),
> +				GFP_KERNEL);
> +	if (WARN_ON(!corediv))
> +		goto err_free_clks;
> +
> +	spin_lock_init(&corediv->lock);
> +
> +	of_property_read_string_index(node, "clock-output-names",
> +					  0, &clk_name);
> +
> +	init.num_parents = 1;
> +	init.parent_names = &parent_name;
> +	init.name = clk_name;
> +	init.ops = &ops;
> +	init.flags = 0;
> +
> +	corediv[0].reg = (void *)((int)base + be32_to_cpu(*off));

I don't understand this, but I guess this has something to do with that
base phandle. Is the corediv clock a sub-component of some "base" clock?
I don't think this binding is the best way of describing that.

Thanks,
Mark.

Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs

[Marcin Wojtas]

Hi Andrew,

2017-01-05 14:09 GMT+01:00 Andrew Lunn <andrew@lunn.ch>:
>> I'd love to see a switchdev driver but it's a huge task (and no I'm not
>> committing to writing it). As it stands Marvell ship a switch SDK
>> largely executes in userspace with a small kernel module providing some
>> linkage to the underlying hardware.
>
> Is there any similarity to the mv88e6xxx family?

Prestera switches (they are sold as standalone devices and with
integrated CPU's, like ones submitted) are as far from mv88e6xxx as
possible. There are various mix of 1/2.5/10/40G ports, depending on
model.

>
> If it was similar registers, just a different access mechanising, we
> could probably extend the mv88e6xxx to support MMIO as well as MDIO.
>

The difference is huge, nothing existing in the mainline can fit. The
driver, that exposes resources to the userspace SDK (called CPSS, it's
huge and complex piece of code) is existing in Marvell internal
branches (kernel v4.4 is the latest one), but I doubt such solution
(despite it's really small) is upstreamable. I believe it can be
shipped to the customers along with the SDK as a kernel module. Having
the CPU's support in the mainline is IMO sufficient.

Best regards,
Marcin

Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs

[Marcin Wojtas]

Hi Chris,

Thanks a lot for your work and v2. Can you please add changelog
between patchset versions in your cover letter?

Best regards,
Marcin

2017-01-05 4:36 GMT+01:00 Chris Packham <chris.packham@alliedtelesis.co.nz>:
> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
> integrated CPUs. They CPU block is common within these product lines and
> (as far as I can tell/have been told) is based on the Armada XP. There
> are a few differences due to the fact they have to squeeze the CPU into
> the same package as the switch.
>
> Chris Packham (4):
>   clk: mvebu: support for 98DX3236 SoC
>   arm: mvebu: support for SMP on 98DX3336 SoC
>   arm: mvebu: Add device tree for 98DX3236 SoCs
>   arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
>
> Kalyan Kinthada (1):
>   pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
>
>  Documentation/devicetree/bindings/arm/cpus.txt     |   1 +
>  .../bindings/arm/marvell/98dx3236-resume-ctrl.txt  |  18 ++
>  .../devicetree/bindings/arm/marvell/98dx3236.txt   |  23 ++
>  .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |   1 +
>  .../pinctrl/marvell,armada-98dx3236-pinctrl.txt    |  46 ++++
>  arch/arm/boot/dts/armada-xp-98dx3236.dtsi          | 247 +++++++++++++++++++++
>  arch/arm/boot/dts/armada-xp-98dx3336.dtsi          |  78 +++++++
>  arch/arm/boot/dts/armada-xp-98dx4251.dtsi          |  92 ++++++++
>  arch/arm/boot/dts/db-dxbc2.dts                     | 159 +++++++++++++
>  arch/arm/boot/dts/db-xc3-24g4xg.dts                | 155 +++++++++++++
>  arch/arm/mach-mvebu/Makefile                       |   1 +
>  arch/arm/mach-mvebu/common.h                       |   1 +
>  arch/arm/mach-mvebu/platsmp.c                      |  43 ++++
>  arch/arm/mach-mvebu/pmsu-98dx3236.c                |  69 ++++++
>  drivers/clk/mvebu/Makefile                         |   2 +-
>  drivers/clk/mvebu/armada-xp.c                      |  42 ++++
>  drivers/clk/mvebu/clk-cpu.c                        |  33 ++-
>  drivers/clk/mvebu/mv98dx3236-corediv.c             | 207 +++++++++++++++++
>  drivers/pinctrl/mvebu/pinctrl-armada-xp.c          | 155 +++++++++++++
>  19 files changed, 1369 insertions(+), 4 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
>  create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
>  create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
>  create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
>  create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>  create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
>  create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
>  create mode 100644 arch/arm/mach-mvebu/pmsu-98dx3236.c
>  create mode 100644 drivers/clk/mvebu/mv98dx3236-corediv.c
>
> --
> 2.11.0.24.ge6920cf
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs

[Chris Packham]

On 06/01/17 02:10, Andrew Lunn wrote:=0A=
>> I'd love to see a switchdev driver but it's a huge task (and no I'm not=
=0A=
>> committing to writing it). As it stands Marvell ship a switch SDK=0A=
>> largely executes in userspace with a small kernel module providing some=
=0A=
>> linkage to the underlying hardware.=0A=
>=0A=
> Is there any similarity to the mv88e6xxx family?=0A=
>=0A=
> If it was similar registers, just a different access mechanising, we=0A=
> could probably extend the mv88e6xxx to support MMIO as well as MDIO.=0A=
=0A=
No the prestera family of devices are considerably more powerful (and =0A=
complex) than the linkstreet devices.=0A=

Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs

[Florian Fainelli]

On 01/05/2017 11:46 AM, Chris Packham wrote:
> On 06/01/17 02:10, Andrew Lunn wrote:
>>> I'd love to see a switchdev driver but it's a huge task (and no I'm not
>>> committing to writing it). As it stands Marvell ship a switch SDK
>>> largely executes in userspace with a small kernel module providing some
>>> linkage to the underlying hardware.
>>
>> Is there any similarity to the mv88e6xxx family?
>>
>> If it was similar registers, just a different access mechanising, we
>> could probably extend the mv88e6xxx to support MMIO as well as MDIO.
> 
> No the prestera family of devices are considerably more powerful (and 
> complex) than the linkstreet devices.

I see, we have a similar situation with some of the Broadcom SoCs, the
BCM534xx/BCM5334x have a completely different integrated switching
engine that is not roboswitch compatible.

Thanks for the information, this is still valuable to have this
supported upstream.
-- 
Florian

Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs

[Chris Packham]

On 06/01/17 03:09, Marcin Wojtas wrote:=0A=
> Hi Chris,=0A=
>=0A=
> Thanks a lot for your work and v2. Can you please add changelog=0A=
> between patchset versions in your cover letter?=0A=
=0A=
Will do for v3. I did actually include a changelog in the individual =0A=
patches but I can collate that here.=0A=
=0A=
clk: mvebu: support for 98DX3236 SoC=0A=
- Update devicetree binding documentation for new compatible string=0A=
arm: mvebu: support for SMP on 98DX3336 SoC=0A=
- Document new enable-method value=0A=
- Correct some references from 98DX4521 to 98DX3236=0A=
pinctrl: mvebu: pinctrl driver for 98DX3236 SoC=0A=
- include sdio support for the 98DX4251=0A=
arm: mvebu: Add device tree for 98DX3236 SoCs=0A=
- Update devicetree binding documentation to reflect that 98DX3336 and=0A=
   984251 are supersets of 98DX3236.=0A=
- disable crypto block=0A=
- disable sdio for 98DX3236, enable for 98DX4251=0A=
arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards=0A=
- None=0A=
=0A=
Here's the interdiff=0A=
=0A=
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt =0A=
b/Documentation/devicetree/bindings/arm/cpus.txt=0A=
index a1bcfeed5f24..3c2fd72d0bf9 100644=0A=
--- a/Documentation/devicetree/bindings/arm/cpus.txt=0A=
+++ b/Documentation/devicetree/bindings/arm/cpus.txt=0A=
@@ -202,6 +202,7 @@ nodes to be present and contain the properties =0A=
described below.=0A=
                             "marvell,armada-380-smp"=0A=
                             "marvell,armada-390-smp"=0A=
                             "marvell,armada-xp-smp"=0A=
+                           "marvell,98dx3236-smp"=0A=
                             "mediatek,mt6589-smp"=0A=
                             "mediatek,mt81xx-tz-smp"=0A=
                             "qcom,gcc-msm8660"=0A=
diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt =0A=
b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt=0A=
index e7dc9b2dd90b..64e8c73fc5ab 100644=0A=
--- a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt=0A=
+++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt=0A=
@@ -6,5 +6,18 @@ shall have the following property:=0A=
=0A=
  Required root node property:=0A=
=0A=
-compatible: one of "marvell,armadaxp-98dx3236", "marvell,armadaxp-98dx3336=
"=0A=
-            or "marvell,armadaxp-98dx4251"=0A=
+compatible: must contain "marvell,armadaxp-98dx3236"=0A=
+=0A=
+In addition, boards using the Marvell 98DX3336 SoC shall have the=0A=
+following property:=0A=
+=0A=
+Required root node property:=0A=
+=0A=
+compatible: must contain "marvell,armadaxp-98dx3336"=0A=
+=0A=
+In addition, boards using the Marvell 98DX4251 SoC shall have the=0A=
+following property:=0A=
+=0A=
+Required root node property:=0A=
+=0A=
+compatible: must contain "marvell,armadaxp-98dx4251"=0A=
diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt =
=0A=
b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt=0A=
index 99c214660bdc..7f28506eaee7 100644=0A=
--- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt=0A=
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt=0A=
@@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU =0A=
platforms=0A=
  Required properties:=0A=
  - compatible : shall be one of the following:=0A=
         "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP=0A=
+       "marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC=0A=
  - reg : Address and length of the clock complex register set, followed=0A=
          by address and length of the PMU DFS registers=0A=
  - #clock-cells : should be set to 1.=0A=
diff --git =0A=
a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl=
.txt =0A=
b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl=
.txt=0A=
index 34c1e380adaa..d4e6ecdfc853 100644=0A=
--- =0A=
a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl=
.txt=0A=
+++ =0A=
b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl=
.txt=0A=
@@ -4,7 +4,7 @@ Please refer to marvell,mvebu-pinctrl.txt in this =0A=
directory for common binding=0A=
  part and usage=0A=
=0A=
  Required properties:=0A=
-- compatible: "marvell,98dx3236-pinctrl"=0A=
+- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"=0A=
  - reg: register specifier of MPP registers=0A=
=0A=
  This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants=0A=
@@ -16,12 +16,12 @@ mpp1          1        gpio, spi0(miso), dev(ad9)=0A=
  mpp2          2        gpio, spi0(sck), dev(ad10)=0A=
  mpp3          3        gpio, spi0(cs0), dev(ad11)=0A=
  mpp4          4        gpio, spi0(cs1), smi(mdc), dev(cs0)=0A=
-mpp5          5        gpio, pex(rsto), dev(bootcs)=0A=
-mpp6          6        gpio, dev(a2)=0A=
-mpp7          7        gpio, dev(ale0)=0A=
-mpp8          8        gpio, dev(ale1)=0A=
-mpp9          9        gpio, dev(ready0)=0A=
-mpp10         10       gpio, dev(ad12)=0A=
+mpp5          5        gpio, pex(rsto), sd0(cmd), dev(bootcs)=0A=
+mpp6          6        gpio, sd0(clk), dev(a2)=0A=
+mpp7          7        gpio, sd0(d0), dev(ale0)=0A=
+mpp8          8        gpio, sd0(d1), dev(ale1)=0A=
+mpp9          9        gpio, sd0(d2), dev(ready0)=0A=
+mpp10         10       gpio, sd0(d3), dev(ad12)=0A=
  mpp11         11       gpio, uart1(rxd), uart0(cts), dev(ad13)=0A=
  mpp12         12       gpio, uart1(txd), uart0(rts), dev(ad14)=0A=
  mpp13         13       gpio, intr(out), dev(ad15)=0A=
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi =0A=
b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi=0A=
index bac53f8b44af..61bd3acc5cfe 100644=0A=
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi=0A=
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi=0A=
@@ -138,6 +138,10 @@=0A=
                                 status =3D "disabled";=0A=
                         };=0A=
=0A=
+                       crypto@90000 {=0A=
+                               status =3D "disabled";=0A=
+                       };=0A=
+=0A=
                         xor@f0900 {=0A=
                                 status =3D "disabled";=0A=
                         };=0A=
@@ -229,3 +233,15 @@=0A=
                 marvell,function =3D "spi0";=0A=
         };=0A=
  };=0A=
+=0A=
+&sdio {=0A=
+       status =3D "disabled";=0A=
+};=0A=
+=0A=
+&crypto_sram0 {=0A=
+       status =3D "disabled";=0A=
+};=0A=
+=0A=
+&crypto_sram1 {=0A=
+       status =3D "disabled";=0A=
+};=0A=
diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi =0A=
b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi=0A=
index 5d1da8513fae..5f7edc23d5ae 100644=0A=
--- a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi=0A=
+++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi=0A=
@@ -76,3 +76,17 @@=0A=
                 };=0A=
         };=0A=
  };=0A=
+=0A=
+&sdio {=0A=
+       status =3D "okay";=0A=
+};=0A=
+=0A=
+&pinctrl {=0A=
+       compatible =3D "marvell,98dx4251-pinctrl";=0A=
+=0A=
+       sdio_pins: sdio-pins {=0A=
+               marvell,pins =3D "mpp5", "mpp6", "mpp7",=0A=
+                              "mpp8", "mpp9", "mpp10";=0A=
+               marvell,function =3D "sd0";=0A=
+       };=0A=
+};=0A=
diff --git a/arch/arm/mach-mvebu/pmsu-98dx3236.c =0A=
b/arch/arm/mach-mvebu/pmsu-98dx3236.c=0A=
index fadc81d0c051..87ca42ef40c7 100644=0A=
--- a/arch/arm/mach-mvebu/pmsu-98dx3236.c=0A=
+++ b/arch/arm/mach-mvebu/pmsu-98dx3236.c=0A=
@@ -1,5 +1,5 @@=0A=
  /**=0A=
- * CPU resume support for 98DX4521 internal CPU (a.k.a. MSYS).=0A=
+ * CPU resume support for 98DX3236 internal CPU (a.k.a. MSYS).=0A=
   */=0A=
=0A=
  #define pr_fmt(fmt) "mv98dx3236-resume: " fmt=0A=
@@ -38,7 +38,7 @@ static int __init mv98dx3236_resume_init(void)=0A=
         if (!np)=0A=
                 return 0;=0A=
=0A=
-       pr_info("Initializing 98DX4521 Resume\n");=0A=
+       pr_info("Initializing 98DX3236 Resume\n");=0A=
=0A=
         if (of_address_to_resource(np, 0, &res)) {=0A=
                 pr_err("unable to get resource\n");=0A=
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c =0A=
b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c=0A=
index 2586903c59f0..554eeae8cd21 100644=0A=
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c=0A=
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c=0A=
@@ -389,21 +389,27 @@ static struct mvebu_mpp_mode =0A=
mv98dx3236_mpp_modes[] =3D {=0A=
         MPP_MODE(5,=0A=
                  MPP_VAR_FUNCTION(0x0, "gpio", NULL, =0A=
V_98DX3236_PLUS),=0A=
                  MPP_VAR_FUNCTION(0x1, "pex", "rsto", =0A=
V_98DX3236_PLUS),=0A=
+                MPP_VAR_FUNCTION(0x2, "sd0", "cmd",         V_98DX4251),=
=0A=
                  MPP_VAR_FUNCTION(0x4, "dev", "bootcs0", =0A=
V_98DX3236_PLUS)),=0A=
         MPP_MODE(6,=0A=
                  MPP_VAR_FUNCTION(0x0, "gpo", NULL, =0A=
V_98DX3236_PLUS),=0A=
+                MPP_VAR_FUNCTION(0x2, "sd0", "clk",         V_98DX4251),=
=0A=
                  MPP_VAR_FUNCTION(0x4, "dev", "a2", =0A=
V_98DX3236_PLUS)),=0A=
         MPP_MODE(7,=0A=
                  MPP_VAR_FUNCTION(0x0, "gpio", NULL, =0A=
V_98DX3236_PLUS),=0A=
+                MPP_VAR_FUNCTION(0x2, "sd0", "d0",          V_98DX4251),=
=0A=
                  MPP_VAR_FUNCTION(0x4, "dev", "ale0", =0A=
V_98DX3236_PLUS)),=0A=
         MPP_MODE(8,=0A=
                  MPP_VAR_FUNCTION(0x0, "gpio", NULL, =0A=
V_98DX3236_PLUS),=0A=
+                MPP_VAR_FUNCTION(0x2, "sd0", "d1",          V_98DX4251),=
=0A=
                  MPP_VAR_FUNCTION(0x4, "dev", "ale1", =0A=
V_98DX3236_PLUS)),=0A=
         MPP_MODE(9,=0A=
                  MPP_VAR_FUNCTION(0x0, "gpio", NULL, =0A=
V_98DX3236_PLUS),=0A=
+                MPP_VAR_FUNCTION(0x2, "sd0", "d2",          V_98DX4251),=
=0A=
                  MPP_VAR_FUNCTION(0x4, "dev", "ready0", =0A=
V_98DX3236_PLUS)),=0A=
         MPP_MODE(10,=0A=
                  MPP_VAR_FUNCTION(0x0, "gpio", NULL, =0A=
V_98DX3236_PLUS),=0A=
+                MPP_VAR_FUNCTION(0x2, "sd0", "d3",          V_98DX4251),=
=0A=
                  MPP_VAR_FUNCTION(0x4, "dev", "ad12", =0A=
V_98DX3236_PLUS)),=0A=
         MPP_MODE(11,=0A=
                  MPP_VAR_FUNCTION(0x0, "gpio", NULL, =0A=
V_98DX3236_PLUS),=0A=
@@ -501,6 +507,10 @@ static const struct of_device_id =0A=
armada_xp_pinctrl_of_match[] =3D {=0A=
                 .compatible =3D "marvell,98dx3236-pinctrl",=0A=
                 .data       =3D (void *) V_98DX3236,=0A=
         },=0A=
+       {=0A=
+               .compatible =3D "marvell,98dx4251-pinctrl",=0A=
+               .data       =3D (void *) V_98DX4251,=0A=
+       },=0A=
         { },=0A=
  };=0A=
=0A=
=0A=
=0A=
>=0A=
> Best regards,=0A=
> Marcin=0A=
>=0A=
> 2017-01-05 4:36 GMT+01:00 Chris Packham <chris.packham@alliedtelesis.co.n=
z>:=0A=
>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with=0A=
>> integrated CPUs. They CPU block is common within these product lines and=
=0A=
>> (as far as I can tell/have been told) is based on the Armada XP. There=
=0A=
>> are a few differences due to the fact they have to squeeze the CPU into=
=0A=
>> the same package as the switch.=0A=
>>=0A=
>> Chris Packham (4):=0A=
>>   clk: mvebu: support for 98DX3236 SoC=0A=
>>   arm: mvebu: support for SMP on 98DX3336 SoC=0A=
>>   arm: mvebu: Add device tree for 98DX3236 SoCs=0A=
>>   arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards=0A=
>>=0A=
>> Kalyan Kinthada (1):=0A=
>>   pinctrl: mvebu: pinctrl driver for 98DX3236 SoC=0A=
>>=0A=
>>  Documentation/devicetree/bindings/arm/cpus.txt     |   1 +=0A=
>>  .../bindings/arm/marvell/98dx3236-resume-ctrl.txt  |  18 ++=0A=
>>  .../devicetree/bindings/arm/marvell/98dx3236.txt   |  23 ++=0A=
>>  .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |   1 +=0A=
>>  .../pinctrl/marvell,armada-98dx3236-pinctrl.txt    |  46 ++++=0A=
>>  arch/arm/boot/dts/armada-xp-98dx3236.dtsi          | 247 ++++++++++++++=
+++++++=0A=
>>  arch/arm/boot/dts/armada-xp-98dx3336.dtsi          |  78 +++++++=0A=
>>  arch/arm/boot/dts/armada-xp-98dx4251.dtsi          |  92 ++++++++=0A=
>>  arch/arm/boot/dts/db-dxbc2.dts                     | 159 +++++++++++++=
=0A=
>>  arch/arm/boot/dts/db-xc3-24g4xg.dts                | 155 +++++++++++++=
=0A=
>>  arch/arm/mach-mvebu/Makefile                       |   1 +=0A=
>>  arch/arm/mach-mvebu/common.h                       |   1 +=0A=
>>  arch/arm/mach-mvebu/platsmp.c                      |  43 ++++=0A=
>>  arch/arm/mach-mvebu/pmsu-98dx3236.c                |  69 ++++++=0A=
>>  drivers/clk/mvebu/Makefile                         |   2 +-=0A=
>>  drivers/clk/mvebu/armada-xp.c                      |  42 ++++=0A=
>>  drivers/clk/mvebu/clk-cpu.c                        |  33 ++-=0A=
>>  drivers/clk/mvebu/mv98dx3236-corediv.c             | 207 ++++++++++++++=
+++=0A=
>>  drivers/pinctrl/mvebu/pinctrl-armada-xp.c          | 155 +++++++++++++=
=0A=
>>  19 files changed, 1369 insertions(+), 4 deletions(-)=0A=
>>  create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx32=
36-resume-ctrl.txt=0A=
>>  create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx32=
36.txt=0A=
>>  create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,ar=
mada-98dx3236-pinctrl.txt=0A=
>>  create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi=0A=
>>  create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi=0A=
>>  create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi=0A=
>>  create mode 100644 arch/arm/boot/dts/db-dxbc2.dts=0A=
>>  create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts=0A=
>>  create mode 100644 arch/arm/mach-mvebu/pmsu-98dx3236.c=0A=
>>  create mode 100644 drivers/clk/mvebu/mv98dx3236-corediv.c=0A=
>>=0A=
>> --=0A=
>> 2.11.0.24.ge6920cf=0A=
>>=0A=
>>=0A=
>> _______________________________________________=0A=
>> linux-arm-kernel mailing list=0A=
>> linux-arm-kernel@lists.infradead.org=0A=
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel=0A=
>=0A=
=0A=

Re: [PATCHv2 1/5] clk: mvebu: support for 98DX3236 SoC

[Chris Packham]

On 06/01/17 03:01, Mark Rutland wrote:=0A=
> On Thu, Jan 05, 2017 at 04:36:37PM +1300, Chris Packham wrote:=0A=
>> The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from=
=0A=
>> the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.=
=0A=
>>=0A=
>> The clock gating options are a subset of those on the Armada XP.=0A=
>>=0A=
>> The core clock divider is different to the Armada XP also.=0A=
>>=0A=
>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>=0A=
>> ---=0A=
>> Changes in v2:=0A=
>> - Update devicetree binding documentation for new compatible string=0A=
>>=0A=
>>  .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |   1 +=0A=
>>  drivers/clk/mvebu/Makefile                         |   2 +-=0A=
>>  drivers/clk/mvebu/armada-xp.c                      |  42 +++++=0A=
>>  drivers/clk/mvebu/clk-cpu.c                        |  33 +++-=0A=
>>  drivers/clk/mvebu/mv98dx3236-corediv.c             | 207 ++++++++++++++=
+++++++=0A=
>>  5 files changed, 281 insertions(+), 4 deletions(-)=0A=
>>  create mode 100644 drivers/clk/mvebu/mv98dx3236-corediv.c=0A=
>=0A=
>=0A=
> It looks like you also need to update=0A=
> Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt for the=
=0A=
> addition of "marvell,mv98dx3236-corediv-clock".=0A=
=0A=
Will do.=0A=
=0A=
>=0A=
>>=0A=
>> diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt=
 b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt=0A=
>> index 99c214660bdc..7f28506eaee7 100644=0A=
>> --- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt=0A=
>> +++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt=0A=
>> @@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU =
platforms=0A=
>>  Required properties:=0A=
>>  - compatible : shall be one of the following:=0A=
>>  	"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP=0A=
>> +	"marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC=0A=
>>  - reg : Address and length of the clock complex register set, followed=
=0A=
>>          by address and length of the PMU DFS registers=0A=
>>  - #clock-cells : should be set to 1.=0A=
>=0A=
> [...]=0A=
>=0A=
>> +static void __init mv98dx3236_corediv_clk_init(struct device_node *node=
)=0A=
>> +{=0A=
>> +	struct clk_init_data init;=0A=
>> +	struct clk_corediv *corediv;=0A=
>> +	struct clk **clks;=0A=
>> +	void __iomem *base;=0A=
>> +	const __be32 *off;=0A=
>> +	const char *parent_name;=0A=
>> +	const char *clk_name;=0A=
>> +	int len;=0A=
>> +	struct device_node *dfx_node;=0A=
>> +=0A=
>> +	dfx_node =3D of_parse_phandle(node, "base", 0);=0A=
>> +	if (WARN_ON(!dfx_node))=0A=
>=0A=
> What's going on here? The existing bingings don't mention a "base"=0A=
> phandle, and nothing was added to describe it.=0A=
>=0A=
>> +		return;=0A=
>> +=0A=
>> +	off =3D of_get_property(node, "reg", &len);=0A=
>> +	if (WARN_ON(!off))=0A=
>> +		return;=0A=
>=0A=
> Please don't use of_get_property directly; generally you should use the=
=0A=
> existing higher-level helpers like of_proeprty_read_u32().=0A=
>=0A=
>> +=0A=
>> +	base =3D of_iomap(dfx_node, 0);=0A=
>> +	if (WARN_ON(!base))=0A=
>> +		return;=0A=
>> +=0A=
>> +	of_node_put(dfx_node);=0A=
>> +=0A=
>> +	parent_name =3D of_clk_get_parent_name(node, 0);=0A=
>> +=0A=
>> +	clk_data.clk_num =3D 1;=0A=
>> +=0A=
>> +	/* clks holds the clock array */=0A=
>> +	clks =3D kcalloc(clk_data.clk_num, sizeof(struct clk *),=0A=
>> +				GFP_KERNEL);=0A=
>> +	if (WARN_ON(!clks))=0A=
>> +		goto err_unmap;=0A=
>> +	/* corediv holds the clock specific array */=0A=
>> +	corediv =3D kcalloc(clk_data.clk_num, sizeof(struct clk_corediv),=0A=
>> +				GFP_KERNEL);=0A=
>> +	if (WARN_ON(!corediv))=0A=
>> +		goto err_free_clks;=0A=
>> +=0A=
>> +	spin_lock_init(&corediv->lock);=0A=
>> +=0A=
>> +	of_property_read_string_index(node, "clock-output-names",=0A=
>> +					  0, &clk_name);=0A=
>> +=0A=
>> +	init.num_parents =3D 1;=0A=
>> +	init.parent_names =3D &parent_name;=0A=
>> +	init.name =3D clk_name;=0A=
>> +	init.ops =3D &ops;=0A=
>> +	init.flags =3D 0;=0A=
>> +=0A=
>> +	corediv[0].reg =3D (void *)((int)base + be32_to_cpu(*off));=0A=
>=0A=
> I don't understand this, but I guess this has something to do with that=
=0A=
> base phandle. Is the corediv clock a sub-component of some "base" clock?=
=0A=
> I don't think this binding is the best way of describing that.=0A=
=0A=
Actually once I've got things setup correctly via the dts I only need =0A=
some minor modification to mvebu/clk-corediv.c to handle the differences =
=0A=
in the bit fields used.=0A=
=0A=
>=0A=
> Thanks,=0A=
> Mark.=0A=
>=0A=
=0A=

[PATCHv2 0/5] Support for Marvell switches with integrated CPUs

[Chris Packham]

The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
integrated CPUs. They CPU block is common within these product lines and
(as far as I can tell/have been told) is based on the Armada XP. There
are a few differences due to the fact they have to squeeze the CPU into
the same package as the switch.

Chris Packham (4):
  clk: mvebu: support for 98DX3236 SoC
    Changes in v2:
    - Update devicetree binding documentation for new compatible string
    Changes in v3:
    - Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a
      new driver.
    - Document mv98dx3236-corediv-clock binding
  arm: mvebu: support for SMP on 98DX3336 SoC
    Changes in v2:
    - Document new enable-method value
    - Correct some references from 98DX4521 to 98DX3236
    Changes in v3:
    - Simplify mv98dx3236_resume_init by using of_io_request_and_map()
  arm: mvebu: Add device tree for 98DX3236 SoCs
    Changes in v2:
    - Update devicetree binding documentation to reflect that 98DX3336 and
      984251 are supersets of 98DX3236.
    - disable crypto block
    - disable sdio for 98DX3236, enable for 98DX4251
    Changes in v3:
    - fix typo 4521 -> 4251
    - document prestera bindings
    - rework corediv-clock binding
    - add label to packet processor node
    - add new compativle string for DFX server
  arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
    Changes in v2/v3:
    - none

Kalyan Kinthada (1):
  pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
    Changes in v2:
    - include sdio support for the 98DX4251
    Changes in v3:
    - None


 Documentation/devicetree/bindings/arm/cpus.txt     |   1 +
 .../bindings/arm/marvell/98dx3236-resume-ctrl.txt  |  18 ++
 .../devicetree/bindings/arm/marvell/98dx3236.txt   |  23 ++
 .../bindings/clock/mvebu-corediv-clock.txt         |   1 +
 .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |   1 +
 .../devicetree/bindings/net/marvell,prestera.txt   |  50 ++++
 .../pinctrl/marvell,armada-98dx3236-pinctrl.txt    |  46 ++++
 arch/arm/boot/dts/armada-xp-98dx3236.dtsi          | 254 +++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-98dx3336.dtsi          |  76 ++++++
 arch/arm/boot/dts/armada-xp-98dx4251.dtsi          |  90 ++++++++
 arch/arm/boot/dts/db-dxbc2.dts                     | 159 +++++++++++++
 arch/arm/boot/dts/db-xc3-24g4xg.dts                | 155 +++++++++++++
 arch/arm/mach-mvebu/Makefile                       |   1 +
 arch/arm/mach-mvebu/common.h                       |   1 +
 arch/arm/mach-mvebu/platsmp.c                      |  43 ++++
 arch/arm/mach-mvebu/pmsu-98dx3236.c                |  52 +++++
 drivers/clk/mvebu/armada-xp.c                      |  42 ++++
 drivers/clk/mvebu/clk-corediv.c                    |  23 ++
 drivers/clk/mvebu/clk-cpu.c                        |  31 ++-
 drivers/pinctrl/mvebu/pinctrl-armada-xp.c          | 155 +++++++++++++
 20 files changed, 1220 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
 create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
 create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
 create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
 create mode 100644 arch/arm/mach-mvebu/pmsu-98dx3236.c

Interdiff to v2:

diff --git
a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
index 520562a7dc2a..c7b4e3a6b2c6 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
@@ -7,6 +7,7 @@ Required properties:
 - compatible : must be "marvell,armada-370-corediv-clock",
                       "marvell,armada-375-corediv-clock",
                       "marvell,armada-380-corediv-clock",
+                       "marvell,mv98dx3236-corediv-clock",
 
 - reg : must be the register address of Core Divider control register
 - #clock-cells : from common clock binding; shall be set to 1
diff --git a/Documentation/devicetree/bindings/net/marvell,prestera.txt
b/Documentation/devicetree/bindings/net/marvell,prestera.txt
new file mode 100644
index 000000000000..5fbab29718e8
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/marvell,prestera.txt
@@ -0,0 +1,50 @@
+Marvell Prestera Switch Chip bindings
+-------------------------------------
+
+Required properties:
+- compatible: one of the following
+       "marvell,prestera-98dx3236",
+       "marvell,prestera-98dx3336",
+       "marvell,prestera-98dx4251",
+- reg: address and length of the register set for the device.
+- interrupts: interrupt for the device
+
+Optional properties:
+- dfx: phandle reference to the "DFX Server" node
+
+Example:
+
+switch {
+       compatible = "simple-bus";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
+
+       packet-processor@0 {
+               compatible = "marvell,prestera-98dx3236";
+               reg = <0 0x4000000>;
+               interrupts = <33>, <34>, <35>;
+               dfx = <&dfx>;
+       };
+};
+
+DFX Server bindings
+-------------------
+
+Required properties:
+- compatible: must be "marvell,dfx-server"
+- reg: address and length of the register set for the device.
+
+Example:
+
+dfx-registers {
+       compatible = "simple-bus";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
+
+       dfx: dfx@0 {
+               compatible = "marvell,dfx-server";
+               reg = <0 0x100000>;
+       };
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index 61bd3acc5cfe..4b7b2fe3b682 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -126,12 +126,7 @@
                        };
 
                        corediv-clock@18740 {
-                               compatible =
                                "marvell,mv98dx3236-corediv-clock";
-                               reg = <0xf8268 0xc>;
-                               base = <&dfx>;
-                               #clock-cells = <1>;
-                               clocks = <&mainpll>;
-                               clock-output-names = "nand";
+                               status = "disabled";
                        };
 
                        xor@60900 {
@@ -194,6 +189,10 @@
                                #interrupt-cells = <2>;
                                interrupts = <87>;
                        };
+
+                       nand: nand@d0000 {
+                               clocks = <&dfx_coredivclk 0>;
+                       };
                };
 
                dfx-registers {
@@ -202,8 +201,16 @@
                        #size-cells = <1>;
                        ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
 
+                        dfx_coredivclk: corediv-clock@f8268 {
+                                compatible =
"marvell,mv98dx3236-corediv-clock";
+                                reg = <0xf8268 0xc>;
+                                #clock-cells = <1>;
+                                clocks = <&mainpll>;
+                                clock-output-names = "nand";
+                        };
+
                        dfx: dfx@0 {
-                               compatible = "simple-bus";
+                               compatible = "marvell,dfx-server";
                                reg = <0 0x100000>;
                        };
                };
@@ -214,7 +221,7 @@
                        #size-cells = <1>;
                        ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
 
-                       packet-processor@0 {
+                       pp0: packet-processor@0 {
                                compatible =
"marvell,prestera-98dx3236";
                                reg = <0 0x4000000>;
                                interrupts = <33>, <34>, <35>;
diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
index 9c9aa565fd82..a9b0f47f8df9 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
@@ -68,11 +68,9 @@
                                reg = <0x20980 0x10>;
                        };
                };
-
-               switch {
-                       packet-processor@0 {
-                               compatible =
                                "marvell,prestera-98dx3336";
-                       };
-               };
        };
 };
+
+&pp0 {
+       compatible = "marvell,prestera-98dx3336";
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
index 5f7edc23d5ae..446e6e65ec59 100644
--- a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
@@ -68,12 +68,6 @@
                                reg = <0x20980 0x10>;
                        };
                };
-
-               switch {
-                       packet-processor@0 {
-                               compatible =
                                "marvell,prestera-98dx4521";
-                       };
-               };
        };
 };
 
@@ -90,3 +84,7 @@
                marvell,function = "sd0";
        };
 };
+
+&pp0 {
+       compatible = "marvell,prestera-98dx4251";
+};
diff --git a/arch/arm/mach-mvebu/pmsu-98dx3236.c
b/arch/arm/mach-mvebu/pmsu-98dx3236.c
index 87ca42ef40c7..1052674dd439 100644
--- a/arch/arm/mach-mvebu/pmsu-98dx3236.c
+++ b/arch/arm/mach-mvebu/pmsu-98dx3236.c
@@ -31,39 +31,22 @@ void mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu,
void *boot_addr)
 static int __init mv98dx3236_resume_init(void)
 {
        struct device_node *np;
-       struct resource res;
-       int ret = 0;
+       void __iomem *base;
 
        np = of_find_matching_node(NULL, of_mv98dx3236_resume_table);
        if (!np)
                return 0;
 
-       pr_info("Initializing 98DX3236 Resume\n");
-
-       if (of_address_to_resource(np, 0, &res)) {
-               pr_err("unable to get resource\n");
-               ret = -ENOENT;
-               goto out;
-       }
-
-       if (!request_mem_region(res.start, resource_size(&res),
-                               np->full_name)) {
-               pr_err("unable to request region\n");
-               ret = -EBUSY;
-               goto out;
-       }
-
-       mv98dx3236_resume_base = ioremap(res.start,
        resource_size(&res));
-       if (!mv98dx3236_resume_base) {
+       base = of_io_request_and_map(np, 0, of_node_full_name(np));
+       if (IS_ERR(base)) {
                pr_err("unable to map registers\n");
-               release_mem_region(res.start, resource_size(&res));
-               ret = -ENOMEM;
-               goto out;
+               of_node_put(np);
+               return PTR_ERR(mv98dx3236_resume_base);
        }
 
-out:
+       mv98dx3236_resume_base = base;
        of_node_put(np);
-       return ret;
+       return 0;
 }
 
 early_initcall(mv98dx3236_resume_init);
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 6a3681e3d6db..d9ae97fb43c4 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_ARMADA_39X_CLK)    += armada-39x.o
 obj-$(CONFIG_ARMADA_37XX_CLK)  += armada-37xx-xtal.o
 obj-$(CONFIG_ARMADA_37XX_CLK)  += armada-37xx-tbg.o
 obj-$(CONFIG_ARMADA_37XX_CLK)  += armada-37xx-periph.o
-obj-$(CONFIG_ARMADA_XP_CLK)    += armada-xp.o mv98dx3236-corediv.o
+obj-$(CONFIG_ARMADA_XP_CLK)    += armada-xp.o
 obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o
 obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o
 obj-$(CONFIG_DOVE_CLK)         += dove.o dove-divider.o
diff --git a/drivers/clk/mvebu/clk-corediv.c
b/drivers/clk/mvebu/clk-corediv.c
index d1e5863d3375..8491979f4096 100644
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -71,6 +71,10 @@ static const struct clk_corediv_desc
mvebu_corediv_desc[] = {
        { .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */
 };
 
+static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = {
+       { .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */
+};
+
 #define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
 
 static int clk_corediv_is_enabled(struct clk_hw *hwclk)
@@ -232,6 +236,18 @@ static const struct clk_corediv_soc_desc
armada375_corediv_soc = {
        .ratio_offset = 0x4,
 };
 
+static const struct clk_corediv_soc_desc mv98dx3236_corediv_soc = {
+       .descs = mv98dx3236_corediv_desc,
+       .ndescs = ARRAY_SIZE(mv98dx3236_corediv_desc),
+       .ops = {
+               .recalc_rate = clk_corediv_recalc_rate,
+               .round_rate = clk_corediv_round_rate,
+               .set_rate = clk_corediv_set_rate,
+       },
+       .ratio_reload = BIT(10),
+       .ratio_offset = 0x8,
+};
+
 static void __init
 mvebu_corediv_clk_init(struct device_node *node,
                       const struct clk_corediv_soc_desc *soc_desc)
@@ -313,3 +329,10 @@ static void __init
armada380_corediv_clk_init(struct device_node *node)
 }
 CLK_OF_DECLARE(armada380_corediv_clk,
"marvell,armada-380-corediv-clock",
               armada380_corediv_clk_init);
+
+static void __init mv98dx3236_corediv_clk_init(struct device_node
*node)
+{
+       return mvebu_corediv_clk_init(node, &mv98dx3236_corediv_soc);
+}
+CLK_OF_DECLARE(mv98dx3236_corediv_clk,
"marvell,mv98dx3236-corediv-clock",
+              mv98dx3236_corediv_clk_init);
diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
index 29f295e7a36b..3b8f0e14fa01 100644
--- a/drivers/clk/mvebu/clk-cpu.c
+++ b/drivers/clk/mvebu/clk-cpu.c
@@ -254,7 +254,7 @@ static void __init of_cpu_clk_setup(struct
device_node *node)
 }
 
 CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
-                                       of_cpu_clk_setup);
+                                        of_cpu_clk_setup);
 
 /* Define the clock and operations for the mv98dx3236 - it cannot
 * perform
  * any operations.
diff --git a/drivers/clk/mvebu/mv98dx3236-corediv.c
b/drivers/clk/mvebu/mv98dx3236-corediv.c
deleted file mode 100644
index 3060764a8e5d..000000000000
--- a/drivers/clk/mvebu/mv98dx3236-corediv.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * MV98DX3236 Core divider clock
- *
- * Copyright (C) 2015 Allied Telesis Labs
- *
- * Based on armada-xp-corediv.c
- * Copyright (C) 2015 Marvell
- *
- * John Thompson <john.thompson@alliedtelesis.co.nz>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/clk-provider.h>
-#include <linux/of_address.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include "common.h"
-
-#define CORE_CLK_DIV_RATIO_MASK                0xff
-
-#define CLK_DIV_RATIO_NAND_MASK 0x0f
-#define CLK_DIV_RATIO_NAND_OFFSET 6
-#define CLK_DIV_RATIO_NAND_FORCE_RELOAD_BIT 26
-
-#define RATIO_RELOAD_BIT BIT(10)
-#define RATIO_REG_OFFSET 0x08
-
-/*
- * This structure represents one core divider clock for the clock
- * framework, and is dynamically allocated for each core divider clock
- * existing in the current SoC.
- */
-struct clk_corediv {
-       struct clk_hw hw;
-       void __iomem *reg;
-       spinlock_t lock;
-};
-
-static struct clk_onecell_data clk_data;
-
-
-#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
-
-static int mv98dx3236_corediv_is_enabled(struct clk_hw *hwclk)
-{
-       /* Core divider is always active */
-       return 1;
-}
-
-static int mv98dx3236_corediv_enable(struct clk_hw *hwclk)
-{
-       /* always succeeds */
-       return 0;
-}
-
-static void mv98dx3236_corediv_disable(struct clk_hw *hwclk)
-{
-       /* can't be disabled so is left alone */
-}
-
-static unsigned long mv98dx3236_corediv_recalc_rate(struct clk_hw
*hwclk,
-                                        unsigned long parent_rate)
-{
-       struct clk_corediv *corediv = to_corediv_clk(hwclk);
-       u32 reg, div;
-
-       reg = readl(corediv->reg + RATIO_REG_OFFSET);
-       div = (reg >> CLK_DIV_RATIO_NAND_OFFSET) &
        CLK_DIV_RATIO_NAND_MASK;
-       return parent_rate / div;
-}
-
-static long mv98dx3236_corediv_round_rate(struct clk_hw *hwclk,
-                              unsigned long rate, unsigned long
                               *parent_rate)
-{
-       /* Valid ratio are 1:4, 1:5, 1:6 and 1:8 */
-       u32 div;
-
-       div = *parent_rate / rate;
-       if (div < 4)
-               div = 4;
-       else if (div > 6)
-               div = 8;
-
-       return *parent_rate / div;
-}
-
-static int mv98dx3236_corediv_set_rate(struct clk_hw *hwclk, unsigned
long rate,
-                           unsigned long parent_rate)
-{
-       struct clk_corediv *corediv = to_corediv_clk(hwclk);
-       unsigned long flags = 0;
-       u32 reg, div;
-
-       div = parent_rate / rate;
-
-       spin_lock_irqsave(&corediv->lock, flags);
-
-       /* Write new divider to the divider ratio register */
-       reg = readl(corediv->reg + RATIO_REG_OFFSET);
-       reg &= ~(CLK_DIV_RATIO_NAND_MASK << CLK_DIV_RATIO_NAND_OFFSET);
-       reg |= (div & CLK_DIV_RATIO_NAND_MASK) <<
        CLK_DIV_RATIO_NAND_OFFSET;
-       writel(reg, corediv->reg + RATIO_REG_OFFSET);
-
-       /* Set reload-force for this clock */
-       reg = readl(corediv->reg) |
        BIT(CLK_DIV_RATIO_NAND_FORCE_RELOAD_BIT);
-       writel(reg, corediv->reg);
-
-       /* Now trigger the clock update */
-       reg = readl(corediv->reg + RATIO_REG_OFFSET) | RATIO_RELOAD_BIT;
-       writel(reg, corediv->reg + RATIO_REG_OFFSET);
-
-       /*
-        * Wait for clocks to settle down, and then clear all the
-        * ratios request and the reload request.
-        */
-       udelay(1000);
-       reg &= ~(CORE_CLK_DIV_RATIO_MASK | RATIO_RELOAD_BIT);
-       writel(reg, corediv->reg + RATIO_REG_OFFSET);
-       udelay(1000);
-
-       spin_unlock_irqrestore(&corediv->lock, flags);
-
-       return 0;
-}
-
-static const struct clk_ops ops = {
-       .enable = mv98dx3236_corediv_enable,
-       .disable = mv98dx3236_corediv_disable,
-       .is_enabled = mv98dx3236_corediv_is_enabled,
-       .recalc_rate = mv98dx3236_corediv_recalc_rate,
-       .round_rate = mv98dx3236_corediv_round_rate,
-       .set_rate = mv98dx3236_corediv_set_rate,
-};
-
-static void __init mv98dx3236_corediv_clk_init(struct device_node
*node)
-{
-       struct clk_init_data init;
-       struct clk_corediv *corediv;
-       struct clk **clks;
-       void __iomem *base;
-       const __be32 *off;
-       const char *parent_name;
-       const char *clk_name;
-       int len;
-       struct device_node *dfx_node;
-
-       dfx_node = of_parse_phandle(node, "base", 0);
-       if (WARN_ON(!dfx_node))
-               return;
-
-       off = of_get_property(node, "reg", &len);
-       if (WARN_ON(!off))
-               return;
-
-       base = of_iomap(dfx_node, 0);
-       if (WARN_ON(!base))
-               return;
-
-       of_node_put(dfx_node);
-
-       parent_name = of_clk_get_parent_name(node, 0);
-
-       clk_data.clk_num = 1;
-
-       /* clks holds the clock array */
-       clks = kcalloc(clk_data.clk_num, sizeof(struct clk *),
-                               GFP_KERNEL);
-       if (WARN_ON(!clks))
-               goto err_unmap;
-       /* corediv holds the clock specific array */
-       corediv = kcalloc(clk_data.clk_num, sizeof(struct clk_corediv),
-                               GFP_KERNEL);
-       if (WARN_ON(!corediv))
-               goto err_free_clks;
-
-       spin_lock_init(&corediv->lock);
-
-       of_property_read_string_index(node, "clock-output-names",
-                                         0, &clk_name);
-
-       init.num_parents = 1;
-       init.parent_names = &parent_name;
-       init.name = clk_name;
-       init.ops = &ops;
-       init.flags = 0;
-
-       corediv[0].reg = (void *)((int)base + be32_to_cpu(*off));
-       corediv[0].hw.init = &init;
-
-       clks[0] = clk_register(NULL, &corediv[0].hw);
-       WARN_ON(IS_ERR(clks[0]));
-
-       clk_data.clks = clks;
-       of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data);
-       return;
-
-err_free_clks:
-       kfree(clks);
-err_unmap:
-       iounmap(base);
-}
-
-CLK_OF_DECLARE(mv98dx3236_corediv_clk,
"marvell,mv98dx3236-corediv-clock",
-              mv98dx3236_corediv_clk_init);


-- 
2.11.0.24.ge6920cf

[PATCHv3 1/5] clk: mvebu: support for 98DX3236 SoC

[Chris Packham]

The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.

The clock gating options are a subset of those on the Armada XP.

The core clock divider is different to the Armada XP also.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
    Changes in v2:
    - Update devicetree binding documentation for new compatible string
    
    Changes in v3:
    - Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new
      driver.
    - Document mv98dx3236-corediv-clock binding

 .../bindings/clock/mvebu-corediv-clock.txt         |  1 +
 .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |  1 +
 drivers/clk/mvebu/armada-xp.c                      | 42 ++++++++++++++++++++++
 drivers/clk/mvebu/clk-corediv.c                    | 23 ++++++++++++
 drivers/clk/mvebu/clk-cpu.c                        | 31 ++++++++++++++--
 5 files changed, 96 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
index 520562a7dc2a..c7b4e3a6b2c6 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
@@ -7,6 +7,7 @@ Required properties:
 - compatible : must be "marvell,armada-370-corediv-clock",
 		       "marvell,armada-375-corediv-clock",
 		       "marvell,armada-380-corediv-clock",
+                       "marvell,mv98dx3236-corediv-clock",
 
 - reg : must be the register address of Core Divider control register
 - #clock-cells : from common clock binding; shall be set to 1
diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
index 99c214660bdc..7f28506eaee7 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
@@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
 Required properties:
 - compatible : shall be one of the following:
 	"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
+	"marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
 - reg : Address and length of the clock complex register set, followed
         by address and length of the PMU DFS registers
 - #clock-cells : should be set to 1.
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
index b3094315a3c0..0413bf8284e0 100644
--- a/drivers/clk/mvebu/armada-xp.c
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -52,6 +52,12 @@ static u32 __init axp_get_tclk_freq(void __iomem *sar)
 	return 250000000;
 }
 
+/* MV98DX3236 TCLK frequency is fixed to 200MHz */
+static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar)
+{
+	return 200000000;
+}
+
 static const u32 axp_cpu_freqs[] __initconst = {
 	1000000000,
 	1066000000,
@@ -89,6 +95,12 @@ static u32 __init axp_get_cpu_freq(void __iomem *sar)
 	return cpu_freq;
 }
 
+/* MV98DX3236 CLK frequency is fixed to 800MHz */
+static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar)
+{
+	return 800000000;
+}
+
 static const int axp_nbclk_ratios[32][2] __initconst = {
 	{0, 1}, {1, 2}, {2, 2}, {2, 2},
 	{1, 2}, {1, 2}, {1, 1}, {2, 3},
@@ -158,6 +170,14 @@ static const struct coreclk_soc_desc axp_coreclks = {
 	.num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
 };
 
+static const struct coreclk_soc_desc mv98dx3236_coreclks = {
+	.get_tclk_freq = mv98dx3236_get_tclk_freq,
+	.get_cpu_freq = mv98dx3236_get_cpu_freq,
+	.get_clk_ratio = NULL,
+	.ratios = NULL,
+	.num_ratios = 0,
+};
+
 /*
  * Clock Gating Control
  */
@@ -195,6 +215,15 @@ static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
 	{ }
 };
 
+static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {
+	{ "ge1", NULL, 3, 0 },
+	{ "ge0", NULL, 4, 0 },
+	{ "pex00", NULL, 5, 0 },
+	{ "sdio", NULL, 17, 0 },
+	{ "xor0", NULL, 22, 0 },
+	{ }
+};
+
 static void __init axp_clk_init(struct device_node *np)
 {
 	struct device_node *cgnp =
@@ -206,3 +235,16 @@ static void __init axp_clk_init(struct device_node *np)
 		mvebu_clk_gating_setup(cgnp, axp_gating_desc);
 }
 CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);
+
+static void __init mv98dx3236_clk_init(struct device_node *np)
+{
+	struct device_node *cgnp =
+		of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
+
+	mvebu_coreclk_setup(np, &mv98dx3236_coreclks);
+
+	if (cgnp)
+		mvebu_clk_gating_setup(cgnp, mv98dx3236_gating_desc);
+}
+CLK_OF_DECLARE(mv98dx3236_clk, "marvell,mv98dx3236-core-clock",
+	       mv98dx3236_clk_init);
diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
index d1e5863d3375..8491979f4096 100644
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -71,6 +71,10 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = {
 	{ .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */
 };
 
+static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = {
+	{ .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */
+};
+
 #define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
 
 static int clk_corediv_is_enabled(struct clk_hw *hwclk)
@@ -232,6 +236,18 @@ static const struct clk_corediv_soc_desc armada375_corediv_soc = {
 	.ratio_offset = 0x4,
 };
 
+static const struct clk_corediv_soc_desc mv98dx3236_corediv_soc = {
+	.descs = mv98dx3236_corediv_desc,
+	.ndescs = ARRAY_SIZE(mv98dx3236_corediv_desc),
+	.ops = {
+		.recalc_rate = clk_corediv_recalc_rate,
+		.round_rate = clk_corediv_round_rate,
+		.set_rate = clk_corediv_set_rate,
+	},
+	.ratio_reload = BIT(10),
+	.ratio_offset = 0x8,
+};
+
 static void __init
 mvebu_corediv_clk_init(struct device_node *node,
 		       const struct clk_corediv_soc_desc *soc_desc)
@@ -313,3 +329,10 @@ static void __init armada380_corediv_clk_init(struct device_node *node)
 }
 CLK_OF_DECLARE(armada380_corediv_clk, "marvell,armada-380-corediv-clock",
 	       armada380_corediv_clk_init);
+
+static void __init mv98dx3236_corediv_clk_init(struct device_node *node)
+{
+	return mvebu_corediv_clk_init(node, &mv98dx3236_corediv_soc);
+}
+CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",
+	       mv98dx3236_corediv_clk_init);
diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
index 5837eb8a212f..3b8f0e14fa01 100644
--- a/drivers/clk/mvebu/clk-cpu.c
+++ b/drivers/clk/mvebu/clk-cpu.c
@@ -165,7 +165,9 @@ static const struct clk_ops cpu_ops = {
 	.set_rate = clk_cpu_set_rate,
 };
 
-static void __init of_cpu_clk_setup(struct device_node *node)
+/* Add parameter to allow this to support different clock operations. */
+static void __init _of_cpu_clk_setup(struct device_node *node,
+			const struct clk_ops *cpu_clk_ops)
 {
 	struct cpu_clk *cpuclk;
 	void __iomem *clock_complex_base = of_iomap(node, 0);
@@ -218,7 +220,7 @@ static void __init of_cpu_clk_setup(struct device_node *node)
 		cpuclk[cpu].hw.init = &init;
 
 		init.name = cpuclk[cpu].clk_name;
-		init.ops = &cpu_ops;
+		init.ops = cpu_clk_ops;
 		init.flags = 0;
 		init.parent_names = &cpuclk[cpu].parent_name;
 		init.num_parents = 1;
@@ -243,5 +245,30 @@ static void __init of_cpu_clk_setup(struct device_node *node)
 	iounmap(clock_complex_base);
 }
 
+/* Use this function to call the generic setup with the correct
+ * clock operation
+ */
+static void __init of_cpu_clk_setup(struct device_node *node)
+{
+	_of_cpu_clk_setup(node, &cpu_ops);
+}
+
 CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
 					 of_cpu_clk_setup);
+
+/* Define the clock and operations for the mv98dx3236 - it cannot perform
+ * any operations.
+ */
+static const struct clk_ops mv98dx3236_cpu_ops = {
+	.recalc_rate = NULL,
+	.round_rate = NULL,
+	.set_rate = NULL,
+};
+
+static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
+{
+	_of_cpu_clk_setup(node, &mv98dx3236_cpu_ops);
+}
+
+CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",
+					 of_mv98dx3236_cpu_clk_setup);
-- 
2.11.0.24.ge6920cf

Re: [PATCHv3 1/5] clk: mvebu: support for 98DX3236 SoC

[Rob Herring]

On Fri, Jan 06, 2017 at 05:14:58PM +1300, Chris Packham wrote:
> The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
> the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
> 
> The clock gating options are a subset of those on the Armada XP.
> 
> The core clock divider is different to the Armada XP also.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
>     Changes in v2:
>     - Update devicetree binding documentation for new compatible string
>     
>     Changes in v3:
>     - Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new
>       driver.
>     - Document mv98dx3236-corediv-clock binding
> 
>  .../bindings/clock/mvebu-corediv-clock.txt         |  1 +
>  .../devicetree/bindings/clock/mvebu-cpu-clock.txt  |  1 +

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/clk/mvebu/armada-xp.c                      | 42 ++++++++++++++++++++++
>  drivers/clk/mvebu/clk-corediv.c                    | 23 ++++++++++++
>  drivers/clk/mvebu/clk-cpu.c                        | 31 ++++++++++++++--
>  5 files changed, 96 insertions(+), 2 deletions(-)