* [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs
@ 2017-01-24 2:32 Chen-Yu Tsai
2017-01-24 2:32 ` [PATCH 01/11] clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers Chen-Yu Tsai
` (11 more replies)
0 siblings, 12 replies; 33+ messages in thread
From: Chen-Yu Tsai @ 2017-01-24 2:32 UTC (permalink / raw)
To: Maxime Ripard, Rob Herring, Mark Rutland, Michael Turquette,
Stephen Boyd
Cc: Chen-Yu Tsai, linux-clk, linux-arm-kernel, devicetree,
linux-kernel, linux-sunxi
Hi everyone,
This series adds new "sunxi-ng" style drivers for the CCUs found in the
Allwinner A80 SoC. The A80 contains 1 main clock control unit, and some
subsystem specific clock control units at separate addresses. These
include the USB, display engine, and MMC.
- The MMC clocks can be supported by the old clock drivers,
hence here we do not add a new driver for it.
- The old USB clock driver is intertwined with other SoCs,
requires old style bindings with clock-output-names and
CLK_OF_DECLARE for its parents. It is easier to switch
to a new binding and driver.
- The display engine (DE) CCU was not supported in the past.
The A80 CCU also has some quirks about its design. It has
- Separate registers for PLL lock status
- P1, P2 dividers, which are power-of-2 and only 1 bit wide
The first 3 patches fix and extend the behavior of sunxi-ng's
mux clock type, based on the behavior of the clk subsystem's
basic mux clock.
The fourth patch adds support for checking PLL lock status
bits in separate registers, as opposed to within the PLL's
config register.
Patches 5 through 7 add drivers for the CCU blocks.
Patches 8 through 10 do some cleanup of the sunxi/allwinner dts
files prior to switching sun9i dts to the new sunxi-ng clock
bindings. These are independent of the clk stuff, but touch the
same lines for sun9i. Including them should make it easier to
apply and test patches.
Patch 11 has sun9i switch over to the new clock bindings.
Please take a look and let me know what you think.
I also have a series adding support for the first display pipeline
of the A80 with RGB LCD panel output which I will send out later
on.
Regards
ChenYu
Chen-Yu Tsai (11):
clk: sunxi-ng: mux: Fix determine_rate for mux clocks with
pre-dividers
clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag
clk: sunxi-ng: mux: Get closest parent rate possible with
CLK_SET_RATE_PARENT
clk: sunxi-ng: Support separately grouped PLL lock status register
clk: sunxi-ng: Add A80 CCU
clk: sunxi-ng: Add A80 USB CCU
clk: sunxi-ng: Add A80 Display Engine CCU
ARM: dts: sun8i-a23-q8-tablet: Drop pinmux setting for codec PA gpio
ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h header
arm64: dts: allwinner: Remove no longer used pinctrl/sun4i-a10.h
header
ARM: dts: sun9i: Switch to new clock bindings
.../devicetree/bindings/clock/sun9i-de.txt | 28 +
.../devicetree/bindings/clock/sun9i-usb.txt | 24 +
.../devicetree/bindings/clock/sunxi-ccu.txt | 1 +
arch/arm/boot/dts/sun4i-a10-a1000.dts | 1 -
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 1 -
arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 1 -
arch/arm/boot/dts/sun4i-a10-hackberry.dts | 1 -
arch/arm/boot/dts/sun4i-a10-inet1.dts | 1 -
arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 1 -
arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts | 1 -
arch/arm/boot/dts/sun4i-a10-marsboard.dts | 1 -
arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 1 -
arch/arm/boot/dts/sun4i-a10-mk802.dts | 1 -
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 1 -
arch/arm/boot/dts/sun4i-a10-pcduino.dts | 1 -
arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 1 -
arch/arm/boot/dts/sun4i-a10.dtsi | 1 -
arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 1 -
arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 1 -
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 1 -
arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 1 -
arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 1 -
arch/arm/boot/dts/sun5i-a10s.dtsi | 1 -
.../boot/dts/sun5i-a13-empire-electronix-d709.dts | 1 -
arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 1 -
arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 1 -
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 1 -
arch/arm/boot/dts/sun5i-a13.dtsi | 1 -
arch/arm/boot/dts/sun5i-gr8.dtsi | 1 -
arch/arm/boot/dts/sun5i.dtsi | 1 -
arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 1 -
arch/arm/boot/dts/sun6i-a31-colombus.dts | 1 -
arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 1 -
arch/arm/boot/dts/sun6i-a31-i7.dts | 1 -
arch/arm/boot/dts/sun6i-a31-m9.dts | 1 -
arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 1 -
arch/arm/boot/dts/sun6i-a31.dtsi | 1 -
arch/arm/boot/dts/sun6i-a31s-cs908.dts | 2 -
arch/arm/boot/dts/sun6i-a31s-primo81.dts | 1 -
arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 1 -
.../dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | 1 -
.../boot/dts/sun6i-reference-design-tablet.dtsi | 1 -
arch/arm/boot/dts/sun7i-a20-bananapi.dts | 1 -
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 1 -
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 1 -
arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 1 -
arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 1 -
arch/arm/boot/dts/sun7i-a20-icnova-swac.dts | 1 -
arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 1 -
arch/arm/boot/dts/sun7i-a20-m3.dts | 1 -
arch/arm/boot/dts/sun7i-a20-mk808c.dts | 1 -
arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 1 -
arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 1 -
arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 1 -
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 1 -
arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 1 -
arch/arm/boot/dts/sun7i-a20-orangepi.dts | 1 -
arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 1 -
arch/arm/boot/dts/sun7i-a20.dtsi | 1 -
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 1 -
arch/arm/boot/dts/sun8i-a23-evb.dts | 1 -
arch/arm/boot/dts/sun8i-a23-q8-tablet.dts | 10 -
arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 1 -
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 -
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 1 -
arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 1 -
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 1 -
arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 1 -
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 1 -
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 1 -
arch/arm/boot/dts/sun8i-h3.dtsi | 1 -
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 1 -
arch/arm/boot/dts/sun9i-a80-optimus.dts | 1 -
arch/arm/boot/dts/sun9i-a80.dtsi | 404 ++-----
arch/arm/boot/dts/sunxi-common-regulators.dtsi | 1 -
.../boot/dts/sunxi-reference-design-tablet.dtsi | 1 -
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 -
drivers/clk/sunxi-ng/Kconfig | 10 +
drivers/clk/sunxi-ng/Makefile | 3 +
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 283 +++++
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h | 33 +
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c | 144 +++
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h | 25 +
drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 1223 ++++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun9i-a80.h | 57 +
drivers/clk/sunxi-ng/ccu_common.c | 8 +-
drivers/clk/sunxi-ng/ccu_common.h | 2 +
drivers/clk/sunxi-ng/ccu_mux.c | 35 +-
include/dt-bindings/clock/sun9i-a80-ccu.h | 162 +++
.../dt-bindings/clock/sun9i-a80-de.h | 73 +-
.../dt-bindings/clock/sun9i-a80-usb.h | 44 +-
.../dt-bindings/reset/sun9i-a80-ccu.h | 91 +-
.../dt-bindings/reset/sun9i-a80-de.h | 45 +-
.../dt-bindings/reset/sun9i-a80-usb.h | 41 +-
94 files changed, 2270 insertions(+), 550 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt
create mode 100644 Documentation/devicetree/bindings/clock/sun9i-usb.txt
create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h
create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h
create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80.h
create mode 100644 include/dt-bindings/clock/sun9i-a80-ccu.h
copy arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi => include/dt-bindings/clock/sun9i-a80-de.h (67%)
copy arch/arm/boot/dts/sun8i-a23-q8-tablet.dts => include/dt-bindings/clock/sun9i-a80-usb.h (73%)
copy arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi => include/dt-bindings/reset/sun9i-a80-ccu.h (56%)
copy arch/arm/boot/dts/sun8i-a23-q8-tablet.dts => include/dt-bindings/reset/sun9i-a80-de.h (73%)
copy arch/arm/boot/dts/sun8i-a23-q8-tablet.dts => include/dt-bindings/reset/sun9i-a80-usb.h (73%)
--
2.11.0
^ permalink raw reply [flat|nested] 33+ messages in thread* [PATCH 01/11] clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers 2017-01-24 2:32 [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai @ 2017-01-24 2:32 ` Chen-Yu Tsai 2017-01-26 9:55 ` Maxime Ripard 2017-01-24 2:32 ` [PATCH 02/11] clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag Chen-Yu Tsai ` (10 subsequent siblings) 11 siblings, 1 reply; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-24 2:32 UTC (permalink / raw) To: Maxime Ripard, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd Cc: Chen-Yu Tsai, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi The determine_rate helper used ccu_mux_helper_adjust_parent_for_prediv() to adjust the parent_rate to account for pre-dividers, but then passed the pristine parent clock rate from clk_hw_get_rate() to the round() callback, thereby ignoring the pre-divider adjustment. In addition, it was saving the adjusted parent rate back into struct clk_rate_request. This patch fixes this by saving the pristine parent clock rate, and adding a copy that is adjusted and passed to the round() callback. The pristine copy, if it is the best solution, would be saved back to struct clk_rate_request. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/clk/sunxi-ng/ccu_mux.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c index 858a48621631..3445041894e7 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.c +++ b/drivers/clk/sunxi-ng/ccu_mux.c @@ -71,7 +71,7 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common, unsigned int i; for (i = 0; i < clk_hw_get_num_parents(hw); i++) { - unsigned long tmp_rate, parent_rate; + unsigned long tmp_rate, parent_rate, adj_parent_rate; struct clk_hw *parent; parent = clk_hw_get_parent_by_index(hw, i); @@ -79,10 +79,11 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common, continue; parent_rate = clk_hw_get_rate(parent); + adj_parent_rate = parent_rate; ccu_mux_helper_adjust_parent_for_prediv(common, cm, i, - &parent_rate); + &adj_parent_rate); - tmp_rate = round(cm, clk_hw_get_rate(parent), req->rate, data); + tmp_rate = round(cm, parent_rate, req->rate, data); if (tmp_rate == req->rate) { best_parent = parent; best_parent_rate = parent_rate; -- 2.11.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH 01/11] clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers 2017-01-24 2:32 ` [PATCH 01/11] clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers Chen-Yu Tsai @ 2017-01-26 9:55 ` Maxime Ripard 2017-01-26 11:22 ` Chen-Yu Tsai 0 siblings, 1 reply; 33+ messages in thread From: Maxime Ripard @ 2017-01-26 9:55 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 2022 bytes --] Hi Chen-Yu, On Tue, Jan 24, 2017 at 10:32:20AM +0800, Chen-Yu Tsai wrote: > The determine_rate helper used ccu_mux_helper_adjust_parent_for_prediv() > to adjust the parent_rate to account for pre-dividers, but then passed > the pristine parent clock rate from clk_hw_get_rate() to the round() > callback, thereby ignoring the pre-divider adjustment. In addition, > it was saving the adjusted parent rate back into struct > clk_rate_request. > > This patch fixes this by saving the pristine parent clock rate, and > adding a copy that is adjusted and passed to the round() callback. > The pristine copy, if it is the best solution, would be saved back > to struct clk_rate_request. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > drivers/clk/sunxi-ng/ccu_mux.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c > index 858a48621631..3445041894e7 100644 > --- a/drivers/clk/sunxi-ng/ccu_mux.c > +++ b/drivers/clk/sunxi-ng/ccu_mux.c > @@ -71,7 +71,7 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common, > unsigned int i; > > for (i = 0; i < clk_hw_get_num_parents(hw); i++) { > - unsigned long tmp_rate, parent_rate; > + unsigned long tmp_rate, parent_rate, adj_parent_rate; > struct clk_hw *parent; > > parent = clk_hw_get_parent_by_index(hw, i); > @@ -79,10 +79,11 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common, > continue; > > parent_rate = clk_hw_get_rate(parent); > + adj_parent_rate = parent_rate; > ccu_mux_helper_adjust_parent_for_prediv(common, cm, i, > - &parent_rate); > + &adj_parent_rate); > > - tmp_rate = round(cm, clk_hw_get_rate(parent), req->rate, data); > + tmp_rate = round(cm, parent_rate, req->rate, data); Shouldn't you use the adjusted rate here too? Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 801 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 01/11] clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers 2017-01-26 9:55 ` Maxime Ripard @ 2017-01-26 11:22 ` Chen-Yu Tsai 0 siblings, 0 replies; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-26 11:22 UTC (permalink / raw) To: Maxime Ripard Cc: Chen-Yu Tsai, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi On Thu, Jan 26, 2017 at 5:55 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Hi Chen-Yu, > > On Tue, Jan 24, 2017 at 10:32:20AM +0800, Chen-Yu Tsai wrote: >> The determine_rate helper used ccu_mux_helper_adjust_parent_for_prediv() >> to adjust the parent_rate to account for pre-dividers, but then passed >> the pristine parent clock rate from clk_hw_get_rate() to the round() >> callback, thereby ignoring the pre-divider adjustment. In addition, >> it was saving the adjusted parent rate back into struct >> clk_rate_request. >> >> This patch fixes this by saving the pristine parent clock rate, and >> adding a copy that is adjusted and passed to the round() callback. >> The pristine copy, if it is the best solution, would be saved back >> to struct clk_rate_request. >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> >> --- >> drivers/clk/sunxi-ng/ccu_mux.c | 7 ++++--- >> 1 file changed, 4 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c >> index 858a48621631..3445041894e7 100644 >> --- a/drivers/clk/sunxi-ng/ccu_mux.c >> +++ b/drivers/clk/sunxi-ng/ccu_mux.c >> @@ -71,7 +71,7 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common, >> unsigned int i; >> >> for (i = 0; i < clk_hw_get_num_parents(hw); i++) { >> - unsigned long tmp_rate, parent_rate; >> + unsigned long tmp_rate, parent_rate, adj_parent_rate; >> struct clk_hw *parent; >> >> parent = clk_hw_get_parent_by_index(hw, i); >> @@ -79,10 +79,11 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common, >> continue; >> >> parent_rate = clk_hw_get_rate(parent); >> + adj_parent_rate = parent_rate; >> ccu_mux_helper_adjust_parent_for_prediv(common, cm, i, >> - &parent_rate); >> + &adj_parent_rate); >> >> - tmp_rate = round(cm, clk_hw_get_rate(parent), req->rate, data); >> + tmp_rate = round(cm, parent_rate, req->rate, data); > > Shouldn't you use the adjusted rate here too? You're right. Thanks! ChenYu ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 02/11] clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag 2017-01-24 2:32 [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai 2017-01-24 2:32 ` [PATCH 01/11] clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers Chen-Yu Tsai @ 2017-01-24 2:32 ` Chen-Yu Tsai 2017-01-24 2:32 ` [PATCH 03/11] clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT Chen-Yu Tsai ` (9 subsequent siblings) 11 siblings, 0 replies; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-24 2:32 UTC (permalink / raw) To: Maxime Ripard, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd Cc: Chen-Yu Tsai, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi This patch adds support for the CLK_SET_RATE_NO_REPARENT flag to the mux determine_rate helper, based on examples from clk-composite and clk-mux. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/clk/sunxi-ng/ccu_mux.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c index 3445041894e7..7cee17cf9c19 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.c +++ b/drivers/clk/sunxi-ng/ccu_mux.c @@ -70,6 +70,21 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common, struct clk_hw *best_parent, *hw = &common->hw; unsigned int i; + if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { + unsigned long adj_parent_rate; + + best_parent = clk_hw_get_parent(hw); + best_parent_rate = clk_hw_get_rate(best_parent); + + adj_parent_rate = best_parent_rate; + ccu_mux_helper_adjust_parent_for_prediv(common, cm, -1, + &adj_parent_rate); + + best_rate = round(cm, adj_parent_rate, req->rate, data); + + goto out; + } + for (i = 0; i < clk_hw_get_num_parents(hw); i++) { unsigned long tmp_rate, parent_rate, adj_parent_rate; struct clk_hw *parent; -- 2.11.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 03/11] clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT 2017-01-24 2:32 [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai 2017-01-24 2:32 ` [PATCH 01/11] clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers Chen-Yu Tsai 2017-01-24 2:32 ` [PATCH 02/11] clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag Chen-Yu Tsai @ 2017-01-24 2:32 ` Chen-Yu Tsai 2017-01-24 2:32 ` [PATCH 04/11] clk: sunxi-ng: Support separately grouped PLL lock status register Chen-Yu Tsai ` (8 subsequent siblings) 11 siblings, 0 replies; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-24 2:32 UTC (permalink / raw) To: Maxime Ripard, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd Cc: Chen-Yu Tsai, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi If the CLK_SET_RATE_PARENT flag is set, we want to try getting the closest parent rate. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/clk/sunxi-ng/ccu_mux.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c index 7cee17cf9c19..c6e83ba47fa4 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.c +++ b/drivers/clk/sunxi-ng/ccu_mux.c @@ -93,7 +93,18 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common, if (!parent) continue; - parent_rate = clk_hw_get_rate(parent); + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { + struct clk_rate_request parent_req = *req; + int ret = __clk_determine_rate(parent, &parent_req); + + if (ret) + continue; + + parent_rate = parent_req.rate; + } else { + parent_rate = clk_hw_get_rate(parent); + } + adj_parent_rate = parent_rate; ccu_mux_helper_adjust_parent_for_prediv(common, cm, i, &adj_parent_rate); -- 2.11.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH 04/11] clk: sunxi-ng: Support separately grouped PLL lock status register 2017-01-24 2:32 [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai ` (2 preceding siblings ...) 2017-01-24 2:32 ` [PATCH 03/11] clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT Chen-Yu Tsai @ 2017-01-24 2:32 ` Chen-Yu Tsai 2017-01-26 9:57 ` Maxime Ripard 2017-01-24 2:32 ` [PATCH 05/11] clk: sunxi-ng: Add A80 CCU Chen-Yu Tsai ` (7 subsequent siblings) 11 siblings, 1 reply; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-24 2:32 UTC (permalink / raw) To: Maxime Ripard, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd Cc: Chen-Yu Tsai, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi On the Allwinner A80 SoC, the PLL lock status indicators are grouped together in a separate register, as opposed to being scattered in each PLL's configuration register. Add a flag to support this. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/clk/sunxi-ng/ccu_common.c | 8 ++++++-- drivers/clk/sunxi-ng/ccu_common.h | 2 ++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c index 51d4bac97ab3..3fd0c3331aff 100644 --- a/drivers/clk/sunxi-ng/ccu_common.c +++ b/drivers/clk/sunxi-ng/ccu_common.c @@ -25,13 +25,17 @@ static DEFINE_SPINLOCK(ccu_lock); void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock) { + void __iomem *addr; u32 reg; if (!lock) return; - WARN_ON(readl_relaxed_poll_timeout(common->base + common->reg, reg, - reg & lock, 100, 70000)); + addr = common->base + common->reg; + if (common->features & CCU_FEATURE_LOCK_REG) + addr = common->base + common->lock_reg; + + WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 70000)); } int sunxi_ccu_probe(struct device_node *node, void __iomem *reg, diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h index cdd69eb2e0b9..73d81dc58fc5 100644 --- a/drivers/clk/sunxi-ng/ccu_common.h +++ b/drivers/clk/sunxi-ng/ccu_common.h @@ -22,6 +22,7 @@ #define CCU_FEATURE_FIXED_PREDIV BIT(2) #define CCU_FEATURE_FIXED_POSTDIV BIT(3) #define CCU_FEATURE_ALL_PREDIV BIT(4) +#define CCU_FEATURE_LOCK_REG BIT(5) struct device_node; @@ -57,6 +58,7 @@ struct device_node; struct ccu_common { void __iomem *base; u16 reg; + u16 lock_reg; u32 prediv; unsigned long features; -- 2.11.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH 04/11] clk: sunxi-ng: Support separately grouped PLL lock status register 2017-01-24 2:32 ` [PATCH 04/11] clk: sunxi-ng: Support separately grouped PLL lock status register Chen-Yu Tsai @ 2017-01-26 9:57 ` Maxime Ripard 0 siblings, 0 replies; 33+ messages in thread From: Maxime Ripard @ 2017-01-26 9:57 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 1364 bytes --] Hi, On Tue, Jan 24, 2017 at 10:32:23AM +0800, Chen-Yu Tsai wrote: > On the Allwinner A80 SoC, the PLL lock status indicators are grouped > together in a separate register, as opposed to being scattered in each > PLL's configuration register. > > Add a flag to support this. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > drivers/clk/sunxi-ng/ccu_common.c | 8 ++++++-- > drivers/clk/sunxi-ng/ccu_common.h | 2 ++ > 2 files changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c > index 51d4bac97ab3..3fd0c3331aff 100644 > --- a/drivers/clk/sunxi-ng/ccu_common.c > +++ b/drivers/clk/sunxi-ng/ccu_common.c > @@ -25,13 +25,17 @@ static DEFINE_SPINLOCK(ccu_lock); > > void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock) > { > + void __iomem *addr; > u32 reg; > > if (!lock) > return; > > - WARN_ON(readl_relaxed_poll_timeout(common->base + common->reg, reg, > - reg & lock, 100, 70000)); > + addr = common->base + common->reg; > + if (common->features & CCU_FEATURE_LOCK_REG) > + addr = common->base + common->lock_reg; I'd rather have an else here (but it's really just a nitpick). Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 801 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 05/11] clk: sunxi-ng: Add A80 CCU 2017-01-24 2:32 [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai ` (3 preceding siblings ...) 2017-01-24 2:32 ` [PATCH 04/11] clk: sunxi-ng: Support separately grouped PLL lock status register Chen-Yu Tsai @ 2017-01-24 2:32 ` Chen-Yu Tsai 2017-01-27 21:13 ` Rob Herring 2017-01-24 2:32 ` [PATCH 06/11] clk: sunxi-ng: Add A80 USB CCU Chen-Yu Tsai ` (6 subsequent siblings) 11 siblings, 1 reply; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-24 2:32 UTC (permalink / raw) To: Maxime Ripard, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd Cc: Chen-Yu Tsai, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi Add support for the main clock unit found in the A80. Note that on the A80, some subsystems have separate clock controllers downstream of the main clock unit. These include the MMC, USB, and display engine subsystems. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 1223 ++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun9i-a80.h | 57 + include/dt-bindings/clock/sun9i-a80-ccu.h | 162 +++ include/dt-bindings/reset/sun9i-a80-ccu.h | 102 ++ 7 files changed, 1556 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80.h create mode 100644 include/dt-bindings/clock/sun9i-a80-ccu.h create mode 100644 include/dt-bindings/reset/sun9i-a80-ccu.h diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt index f6032cf63f12..bae5668cf427 100644 --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt @@ -8,6 +8,7 @@ Required properties : - "allwinner,sun8i-a33-ccu" - "allwinner,sun8i-h3-ccu" - "allwinner,sun8i-v3s-ccu" + - "allwinner,sun9i-a80-ccu" - "allwinner,sun50i-a64-ccu" - reg: Must contain the registers base address and length diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 71f11cd1647b..67659091860d 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -130,4 +130,14 @@ config SUN8I_V3S_CCU select SUNXI_CCU_PHASE default MACH_SUN8I +config SUN9I_A80_CCU + bool "Support for the Allwinner A80 CCU" + select SUNXI_CCU_DIV + select SUNXI_CCU_GATE + select SUNXI_CCU_NKMP + select SUNXI_CCU_NM + select SUNXI_CCU_MP + select SUNXI_CCU_PHASE + default MACH_SUN9I + endif diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index a8afdf9c7668..126bb7c1c3f7 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -25,3 +25,4 @@ obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c new file mode 100644 index 000000000000..5626e4674f48 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c @@ -0,0 +1,1223 @@ +/* + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-sun9i-a80.h" + +#define CCU_SUN9I_LOCK_REG 0x09c + +static struct clk_div_table pll_cpux_p_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 4 }, + { /* Sentinel */ }, +}; + +/* + * The CPU PLLs are actually NP clocks, but P is /1 or /4, so here we + * use the NM clocks with a divider table for M. + */ +static struct ccu_nm pll_c0cpux_clk = { + .enable = BIT(31), + .lock = BIT(0), + .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .m = _SUNXI_CCU_DIV_TABLE(16, 1, pll_cpux_p_div_table), + .common = { + .reg = 0x000, + .lock_reg = CCU_SUN9I_LOCK_REG, + .features = CCU_FEATURE_LOCK_REG, + .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M", + &ccu_nm_ops, CLK_SET_RATE_UNGATE), + }, +}; + +static struct ccu_nm pll_c1cpux_clk = { + .enable = BIT(31), + .lock = BIT(1), + .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .m = _SUNXI_CCU_DIV_TABLE(16, 1, pll_cpux_p_div_table), + .common = { + .reg = 0x004, + .lock_reg = CCU_SUN9I_LOCK_REG, + .features = CCU_FEATURE_LOCK_REG, + .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M", + &ccu_nm_ops, CLK_SET_RATE_UNGATE), + }, +}; + +/* + * The Audio PLL has d1, d2 dividers in addition to the usual N, M + * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz + * and 24.576 MHz, ignore them for now. Enforce the default for them, + * which is d1 = 0, d2 = 1. + */ +#define SUN9I_A80_PLL_AUDIO_REG 0x008 + +static struct ccu_nm pll_audio_clk = { + .enable = BIT(31), + .lock = BIT(2), + .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .m = _SUNXI_CCU_DIV_OFFSET(0, 6, 0), + .common = { + .reg = 0x008, + .lock_reg = CCU_SUN9I_LOCK_REG, + .features = CCU_FEATURE_LOCK_REG, + .hw.init = CLK_HW_INIT("pll-audio", "osc24M", + &ccu_nm_ops, CLK_SET_RATE_UNGATE), + }, +}; + +/* Some PLLs are input * N / div1 / div2. Model them as NKMP with no K */ +static struct ccu_nkmp pll_periph0_clk = { + .enable = BIT(31), + .lock = BIT(3), + .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ + .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ + .common = { + .reg = 0x00c, + .lock_reg = CCU_SUN9I_LOCK_REG, + .features = CCU_FEATURE_LOCK_REG, + .hw.init = CLK_HW_INIT("pll-periph0", "osc24M", + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +static struct ccu_nkmp pll_ve_clk = { + .enable = BIT(31), + .lock = BIT(4), + .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ + .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ + .common = { + .reg = 0x010, + .lock_reg = CCU_SUN9I_LOCK_REG, + .features = CCU_FEATURE_LOCK_REG, + .hw.init = CLK_HW_INIT("pll-ve", "osc24M", + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +static struct ccu_nkmp pll_ddr_clk = { + .enable = BIT(31), + .lock = BIT(5), + .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ + .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ + .common = { + .reg = 0x014, + .lock_reg = CCU_SUN9I_LOCK_REG, + .features = CCU_FEATURE_LOCK_REG, + .hw.init = CLK_HW_INIT("pll-ddr", "osc24M", + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +static struct ccu_nm pll_video0_clk = { + .enable = BIT(31), + .lock = BIT(6), + .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ + .common = { + .reg = 0x018, + .lock_reg = CCU_SUN9I_LOCK_REG, + .features = CCU_FEATURE_LOCK_REG, + .hw.init = CLK_HW_INIT("pll-video0", "osc24M", + &ccu_nm_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +static struct ccu_nkmp pll_video1_clk = { + .enable = BIT(31), + .lock = BIT(7), + .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ + .p = _SUNXI_CCU_DIV(0, 2), /* external divider p */ + .common = { + .reg = 0x01c, + .lock_reg = CCU_SUN9I_LOCK_REG, + .features = CCU_FEATURE_LOCK_REG, + .hw.init = CLK_HW_INIT("pll-video1", "osc24M", + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +static struct ccu_nkmp pll_gpu_clk = { + .enable = BIT(31), + .lock = BIT(8), + .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ + .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ + .common = { + .reg = 0x020, + .lock_reg = CCU_SUN9I_LOCK_REG, + .features = CCU_FEATURE_LOCK_REG, + .hw.init = CLK_HW_INIT("pll-gpu", "osc24M", + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +static struct ccu_nkmp pll_de_clk = { + .enable = BIT(31), + .lock = BIT(9), + .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ + .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ + .common = { + .reg = 0x024, + .lock_reg = CCU_SUN9I_LOCK_REG, + .features = CCU_FEATURE_LOCK_REG, + .hw.init = CLK_HW_INIT("pll-de", "osc24M", + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +static struct ccu_nkmp pll_isp_clk = { + .enable = BIT(31), + .lock = BIT(10), + .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ + .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ + .common = { + .reg = 0x028, + .lock_reg = CCU_SUN9I_LOCK_REG, + .features = CCU_FEATURE_LOCK_REG, + .hw.init = CLK_HW_INIT("pll-isp", "osc24M", + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +static struct ccu_nkmp pll_periph1_clk = { + .enable = BIT(31), + .lock = BIT(11), + .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ + .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ + .common = { + .reg = 0x028, + .lock_reg = CCU_SUN9I_LOCK_REG, + .features = CCU_FEATURE_LOCK_REG, + .hw.init = CLK_HW_INIT("pll-periph1", "osc24M", + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, +}; + +static const char * const c0cpux_parents[] = { "osc24M", "pll-c0cpux" }; +static SUNXI_CCU_MUX(c0cpux_clk, "c0cpux", c0cpux_parents, + 0x50, 0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); + +static const char * const c1cpux_parents[] = { "osc24M", "pll-c1cpux" }; +static SUNXI_CCU_MUX(c1cpux_clk, "c1cpux", c1cpux_parents, + 0x50, 8, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); + +static struct clk_div_table axi_div_table[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 3 }, + { .val = 3, .div = 4 }, + { .val = 4, .div = 4 }, + { .val = 5, .div = 4 }, + { .val = 6, .div = 4 }, + { .val = 7, .div = 4 }, + { /* Sentinel */ }, +}; + +static SUNXI_CCU_M(atb0_clk, "atb0", "c0cpux", 0x054, 8, 2, 0); + +static SUNXI_CCU_DIV_TABLE(axi0_clk, "axi0", "c0cpux", + 0x054, 0, 3, axi_div_table, 0); + +static SUNXI_CCU_M(atb1_clk, "atb1", "c1cpux", 0x058, 8, 2, 0); + +static SUNXI_CCU_DIV_TABLE(axi1_clk, "axi1", "c1cpux", + 0x058, 0, 3, axi_div_table, 0); + +static const char * const gtbus_parents[] = { "osc24M", "pll-periph0", + "pll-periph1", "pll-periph1" }; +static SUNXI_CCU_M_WITH_MUX(gtbus_clk, "gtbus", gtbus_parents, + 0x05c, 0, 2, 24, 2, CLK_IS_CRITICAL); + +static const char * const ahb_parents[] = { "gtbus", "pll-periph0", + "pll-periph1", "pll-periph1" }; +static struct ccu_div ahb0_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), + .mux = _SUNXI_CCU_MUX(24, 2), + .common = { + .reg = 0x060, + .hw.init = CLK_HW_INIT_PARENTS("ahb0", + ahb_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div ahb1_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), + .mux = _SUNXI_CCU_MUX(24, 2), + .common = { + .reg = 0x064, + .hw.init = CLK_HW_INIT_PARENTS("ahb1", + ahb_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div ahb2_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), + .mux = _SUNXI_CCU_MUX(24, 2), + .common = { + .reg = 0x068, + .hw.init = CLK_HW_INIT_PARENTS("ahb2", + ahb_parents, + &ccu_div_ops, + 0), + }, +}; + +static const char * const apb_parents[] = { "osc24M", "pll-periph0" }; + +static struct ccu_div apb0_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), + .mux = _SUNXI_CCU_MUX(24, 1), + .common = { + .reg = 0x070, + .hw.init = CLK_HW_INIT_PARENTS("apb0", + apb_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div apb1_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), + .mux = _SUNXI_CCU_MUX(24, 1), + .common = { + .reg = 0x074, + .hw.init = CLK_HW_INIT_PARENTS("apb1", + apb_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div cci400_clk = { + .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), + .mux = _SUNXI_CCU_MUX(24, 2), + .common = { + .reg = 0x078, + .hw.init = CLK_HW_INIT_PARENTS("cci400", + ahb_parents, + &ccu_div_ops, + CLK_IS_CRITICAL), + }, +}; + +static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", apb_parents, + 0x080, 0, 3, 24, 2, BIT(31), 0); + +static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", apb_parents, + 0x084, 0, 3, 24, 2, BIT(31), 0); + +static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" }; +static const struct ccu_mux_fixed_prediv out_prediv = { + .index = 0, .div = 750 +}; + +static struct ccu_mp out_a_clk = { + .enable = BIT(31), + .m = _SUNXI_CCU_DIV(8, 5), + .p = _SUNXI_CCU_DIV(20, 2), + .mux = { + .shift = 24, + .width = 4, + .fixed_predivs = &out_prediv, + .n_predivs = 1, + }, + .common = { + .reg = 0x180, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("out-a", + out_parents, + &ccu_mp_ops, + 0), + }, +}; + +static struct ccu_mp out_b_clk = { + .enable = BIT(31), + .m = _SUNXI_CCU_DIV(8, 5), + .p = _SUNXI_CCU_DIV(20, 2), + .mux = { + .shift = 24, + .width = 4, + .fixed_predivs = &out_prediv, + .n_predivs = 1, + }, + .common = { + .reg = 0x184, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("out-b", + out_parents, + &ccu_mp_ops, + 0), + }, +}; + +static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0" }; + +static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_0_clk, "nand0-0", mod0_default_parents, + 0x400, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_1_clk, "nand0-1", mod0_default_parents, + 0x404, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_0_clk, "nand1-0", mod0_default_parents, + 0x408, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_1_clk, "nand1-1", mod0_default_parents, + 0x40c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, + 0x410, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0", + 0x410, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0", + 0x410, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, + 0x414, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1", + 0x414, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1", + 0x414, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, + 0x418, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2", + 0x418, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2", + 0x418, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, + 0x41c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3-sample", "mmc3", + 0x41c, 20, 3, 0); +static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3-output", "mmc3", + 0x41c, 8, 3, 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, + 0x428, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static const char * const ss_parents[] = { "osc24M", "pll-periph", + "pll-periph1" }; +static const u8 ss_table[] = { 0, 1, 13 }; +static struct ccu_mp ss_clk = { + .enable = BIT(31), + .m = _SUNXI_CCU_DIV(0, 4), + .p = _SUNXI_CCU_DIV(16, 2), + .mux = _SUNXI_CCU_MUX_TABLE(24, 4, ss_table), + .common = { + .reg = 0x42c, + .hw.init = CLK_HW_INIT_PARENTS("ss", + ss_parents, + &ccu_mp_ops, + 0), + }, +}; + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, + 0x430, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, + 0x434, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, + 0x438, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, + 0x43c, + 0, 4, /* M */ + 16, 2, /* P */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio", + 0x440, 0, 4, BIT(31), CLK_SET_RATE_PARENT); +static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio", + 0x444, 0, 4, BIT(31), CLK_SET_RATE_PARENT); +static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", + 0x44c, 0, 4, BIT(31), CLK_SET_RATE_PARENT); + +static const char * const sdram_parents[] = { "pll-periph0", "pll-ddr" }; +static const u8 sdram_table[] = { 0, 3 }; + +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(sdram_clk, "sdram", + sdram_parents, sdram_table, + 0x484, + 8, 4, /* M */ + 12, 4, /* mux */ + 0, /* no gate */ + CLK_IS_CRITICAL); + +static SUNXI_CCU_M_WITH_GATE(de_clk, "de", "pll-de", 0x490, + 0, 4, BIT(31), CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE(edp_clk, "edp", "osc24M", 0x494, BIT(31), 0); + +static const char * const mp_parents[] = { "pll-video1", "pll-gpu", "pll-de" }; +static const u8 mp_table[] = { 9, 10, 11 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mp_clk, "mp", mp_parents, mp_table, + 0x498, + 0, 4, /* M */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static const char * const display_parents[] = { "pll-video0", "pll-video1" }; +static const u8 display_table[] = { 8, 9 }; + +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd0_clk, "lcd0", + display_parents, display_table, + 0x49c, + 0, 4, /* M */ + 24, 4, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_NO_REPARENT | + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd1_clk, "lcd1", + display_parents, display_table, + 0x4a0, + 0, 4, /* M */ + 24, 4, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_NO_REPARENT | + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0", + display_parents, display_table, + 0x4a8, + 0, 4, /* M */ + 24, 4, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const char * const mipi_dsi1_parents[] = { "osc24M", "pll-video1" }; +static const u8 mipi_dsi1_table[] = { 0, 9 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1", + mipi_dsi1_parents, mipi_dsi1_table, + 0x4ac, + 0, 4, /* M */ + 24, 4, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi_clk, "hdmi", + display_parents, display_table, + 0x4b0, + 0, 4, /* M */ + 24, 4, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_NO_REPARENT | + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x4b4, BIT(31), 0); + +static SUNXI_CCU_M_WITH_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x4bc, + 0, 4, BIT(31), 0); + +static SUNXI_CCU_M_WITH_GATE(csi_isp_clk, "csi-isp", "pll-isp", 0x4c0, + 0, 4, BIT(31), CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x4c0, BIT(16), 0); + +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_mclk_clk, "csi0-mclk", + mipi_dsi1_parents, mipi_dsi1_table, + 0x4c4, + 0, 4, /* M */ + 24, 4, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_mclk_clk, "csi1-mclk", + mipi_dsi1_parents, mipi_dsi1_table, + 0x4c8, + 0, 4, /* M */ + 24, 4, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const char * const fd_parents[] = { "pll-periph0", "pll-isp" }; +static const u8 fd_table[] = { 1, 12 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(fd_clk, "fd", fd_parents, fd_table, + 0x4cc, + 0, 4, /* M */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x4d0, + 16, 3, BIT(31), CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x4d4, BIT(31), 0); + +static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x4f0, + 0, 3, BIT(31), CLK_SET_RATE_PARENT); +static SUNXI_CCU_M_WITH_GATE(gpu_memory_clk, "gpu-memory", "pll-gpu", 0x4f4, + 0, 3, BIT(31), CLK_SET_RATE_PARENT); + +static const char * const gpu_axi_parents[] = { "pll-periph0", "pll-gpu" }; +static const u8 gpu_axi_table[] = { 1, 10 }; +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_axi_clk, "gpu-axi", + gpu_axi_parents, gpu_axi_table, + 0x4f8, + 0, 4, /* M */ + 24, 4, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_M_WITH_GATE(sata_clk, "sata", "pll-periph0", 0x500, + 0, 4, BIT(31), 0); + +static SUNXI_CCU_M_WITH_GATE(ac97_clk, "ac97", "pll-audio", + 0x504, 0, 4, BIT(31), CLK_SET_RATE_PARENT); + +static SUNXI_CCU_M_WITH_MUX_GATE(mipi_hsi_clk, "mipi-hsi", + mod0_default_parents, 0x508, + 0, 4, /* M */ + 24, 4, /* mux */ + BIT(31), /* gate */ + 0); + +static const char * const gpadc_parents[] = { "osc24M", "pll-audio", "osc32k" }; +static const u8 gpadc_table[] = { 0, 4, 7 }; +static struct ccu_mp gpadc_clk = { + .enable = BIT(31), + .m = _SUNXI_CCU_DIV(0, 4), + .p = _SUNXI_CCU_DIV(16, 2), + .mux = _SUNXI_CCU_MUX_TABLE(24, 4, gpadc_table), + .common = { + .reg = 0x50c, + .hw.init = CLK_HW_INIT_PARENTS("gpadc", + gpadc_parents, + &ccu_mp_ops, + 0), + }, +}; + +static const char * const cir_tx_parents[] = { "osc24M", "osc32k" }; +static const u8 cir_tx_table[] = { 0, 7 }; +static struct ccu_mp cir_tx_clk = { + .enable = BIT(31), + .m = _SUNXI_CCU_DIV(0, 4), + .p = _SUNXI_CCU_DIV(16, 2), + .mux = _SUNXI_CCU_MUX_TABLE(24, 4, cir_tx_table), + .common = { + .reg = 0x510, + .hw.init = CLK_HW_INIT_PARENTS("cir-tx", + cir_tx_parents, + &ccu_mp_ops, + 0), + }, +}; + +/* AHB0 bus gates */ +static SUNXI_CCU_GATE(bus_fd_clk, "bus-fd", "ahb0", + 0x580, BIT(0), 0); +static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb0", + 0x580, BIT(1), 0); +static SUNXI_CCU_GATE(bus_gpu_ctrl_clk, "bus-gpu-ctrl", "ahb0", + 0x580, BIT(3), 0); +static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb0", + 0x580, BIT(5), 0); +static SUNXI_CCU_GATE(bus_mmc_clk, "bus-mmc", "ahb0", + 0x580, BIT(8), 0); +static SUNXI_CCU_GATE(bus_nand0_clk, "bus-nand0", "ahb0", + 0x580, BIT(12), 0); +static SUNXI_CCU_GATE(bus_nand1_clk, "bus-nand1", "ahb0", + 0x580, BIT(13), 0); +static SUNXI_CCU_GATE(bus_sdram_clk, "bus-sdram", "ahb0", + 0x580, BIT(14), 0); +static SUNXI_CCU_GATE(bus_mipi_hsi_clk, "bus-mipi-hsi", "ahb0", + 0x580, BIT(15), 0); +static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb0", + 0x580, BIT(16), 0); +static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb0", + 0x580, BIT(18), 0); +static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb0", + 0x580, BIT(20), 0); +static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb0", + 0x580, BIT(21), 0); +static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb0", + 0x580, BIT(22), 0); +static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb0", + 0x580, BIT(23), 0); + +/* AHB1 bus gates */ +static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", + 0x584, BIT(0), 0); +static SUNXI_CCU_GATE(bus_usb_clk, "bus-usb", "ahb1", + 0x584, BIT(1), 0); +static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1", + 0x584, BIT(17), 0); +static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", + 0x584, BIT(21), 0); +static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", + 0x584, BIT(22), 0); +static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", + 0x584, BIT(23), 0); +static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", + 0x584, BIT(24), 0); + +/* AHB2 bus gates */ +static SUNXI_CCU_GATE(bus_lcd0_clk, "bus-lcd0", "ahb2", + 0x588, BIT(0), 0); +static SUNXI_CCU_GATE(bus_lcd1_clk, "bus-lcd1", "ahb2", + 0x588, BIT(1), 0); +static SUNXI_CCU_GATE(bus_edp_clk, "bus-edp", "ahb2", + 0x588, BIT(2), 0); +static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb2", + 0x588, BIT(4), 0); +static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb2", + 0x588, BIT(5), 0); +static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb2", + 0x588, BIT(7), 0); +static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb2", + 0x588, BIT(8), 0); +static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb2", + 0x588, BIT(11), 0); + +/* APB0 bus gates */ +static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb0", + 0x590, BIT(1), 0); +static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb0", + 0x590, BIT(5), 0); +static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb0", + 0x590, BIT(11), 0); +static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb0", + 0x590, BIT(12), 0); +static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb0", + 0x590, BIT(13), 0); +static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "apb0", + 0x590, BIT(15), 0); +static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb0", + 0x590, BIT(17), 0); +static SUNXI_CCU_GATE(bus_twd_clk, "bus-twd", "apb0", + 0x590, BIT(18), 0); +static SUNXI_CCU_GATE(bus_cir_tx_clk, "bus-cir-tx", "apb0", + 0x590, BIT(19), 0); + +/* APB1 bus gates */ +static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb1", + 0x594, BIT(0), 0); +static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb1", + 0x594, BIT(1), 0); +static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb1", + 0x594, BIT(2), 0); +static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb1", + 0x594, BIT(3), 0); +static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb1", + 0x594, BIT(4), 0); +static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb1", + 0x594, BIT(16), 0); +static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb1", + 0x594, BIT(17), 0); +static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb1", + 0x594, BIT(18), 0); +static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb1", + 0x594, BIT(19), 0); +static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb1", + 0x594, BIT(20), 0); +static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb1", + 0x594, BIT(21), 0); + +static struct ccu_common *sun9i_a80_ccu_clks[] = { + &pll_c0cpux_clk.common, + &pll_c1cpux_clk.common, + &pll_audio_clk.common, + &pll_periph0_clk.common, + &pll_ve_clk.common, + &pll_ddr_clk.common, + &pll_video0_clk.common, + &pll_video1_clk.common, + &pll_gpu_clk.common, + &pll_de_clk.common, + &pll_isp_clk.common, + &pll_periph1_clk.common, + &c0cpux_clk.common, + &c1cpux_clk.common, + &atb0_clk.common, + &axi0_clk.common, + &atb1_clk.common, + &axi1_clk.common, + >bus_clk.common, + &ahb0_clk.common, + &ahb1_clk.common, + &ahb2_clk.common, + &apb0_clk.common, + &apb1_clk.common, + &cci400_clk.common, + &ats_clk.common, + &trace_clk.common, + + &out_a_clk.common, + &out_b_clk.common, + + /* module clocks */ + &nand0_0_clk.common, + &nand0_1_clk.common, + &nand1_0_clk.common, + &nand1_1_clk.common, + &mmc0_clk.common, + &mmc0_sample_clk.common, + &mmc0_output_clk.common, + &mmc1_clk.common, + &mmc1_sample_clk.common, + &mmc1_output_clk.common, + &mmc2_clk.common, + &mmc2_sample_clk.common, + &mmc2_output_clk.common, + &mmc3_clk.common, + &mmc3_sample_clk.common, + &mmc3_output_clk.common, + &ts_clk.common, + &ss_clk.common, + &spi0_clk.common, + &spi1_clk.common, + &spi2_clk.common, + &spi3_clk.common, + &i2s0_clk.common, + &i2s1_clk.common, + &spdif_clk.common, + &sdram_clk.common, + &de_clk.common, + &edp_clk.common, + &mp_clk.common, + &lcd0_clk.common, + &lcd1_clk.common, + &mipi_dsi0_clk.common, + &mipi_dsi1_clk.common, + &hdmi_clk.common, + &hdmi_slow_clk.common, + &mipi_csi_clk.common, + &csi_isp_clk.common, + &csi_misc_clk.common, + &csi0_mclk_clk.common, + &csi1_mclk_clk.common, + &fd_clk.common, + &ve_clk.common, + &avs_clk.common, + &gpu_core_clk.common, + &gpu_memory_clk.common, + &gpu_axi_clk.common, + &sata_clk.common, + &ac97_clk.common, + &mipi_hsi_clk.common, + &gpadc_clk.common, + &cir_tx_clk.common, + + /* AHB0 bus gates */ + &bus_fd_clk.common, + &bus_ve_clk.common, + &bus_gpu_ctrl_clk.common, + &bus_ss_clk.common, + &bus_mmc_clk.common, + &bus_nand0_clk.common, + &bus_nand1_clk.common, + &bus_sdram_clk.common, + &bus_mipi_hsi_clk.common, + &bus_sata_clk.common, + &bus_ts_clk.common, + &bus_spi0_clk.common, + &bus_spi1_clk.common, + &bus_spi2_clk.common, + &bus_spi3_clk.common, + + /* AHB1 bus gates */ + &bus_otg_clk.common, + &bus_usb_clk.common, + &bus_gmac_clk.common, + &bus_msgbox_clk.common, + &bus_spinlock_clk.common, + &bus_hstimer_clk.common, + &bus_dma_clk.common, + + /* AHB2 bus gates */ + &bus_lcd0_clk.common, + &bus_lcd1_clk.common, + &bus_edp_clk.common, + &bus_csi_clk.common, + &bus_hdmi_clk.common, + &bus_de_clk.common, + &bus_mp_clk.common, + &bus_mipi_dsi_clk.common, + + /* APB0 bus gates */ + &bus_spdif_clk.common, + &bus_pio_clk.common, + &bus_ac97_clk.common, + &bus_i2s0_clk.common, + &bus_i2s1_clk.common, + &bus_lradc_clk.common, + &bus_gpadc_clk.common, + &bus_twd_clk.common, + &bus_cir_tx_clk.common, + + /* APB1 bus gates */ + &bus_i2c0_clk.common, + &bus_i2c1_clk.common, + &bus_i2c2_clk.common, + &bus_i2c3_clk.common, + &bus_i2c4_clk.common, + &bus_uart0_clk.common, + &bus_uart1_clk.common, + &bus_uart2_clk.common, + &bus_uart3_clk.common, + &bus_uart4_clk.common, + &bus_uart5_clk.common, +}; + +static struct clk_hw_onecell_data sun9i_a80_hw_clks = { + .hws = { + [CLK_PLL_C0CPUX] = &pll_c0cpux_clk.common.hw, + [CLK_PLL_C1CPUX] = &pll_c1cpux_clk.common.hw, + [CLK_PLL_AUDIO] = &pll_audio_clk.common.hw, + [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, + [CLK_PLL_VE] = &pll_ve_clk.common.hw, + [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, + [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, + [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, + [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, + [CLK_PLL_DE] = &pll_de_clk.common.hw, + [CLK_PLL_ISP] = &pll_isp_clk.common.hw, + [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, + [CLK_C0CPUX] = &c0cpux_clk.common.hw, + [CLK_C1CPUX] = &c1cpux_clk.common.hw, + [CLK_ATB0] = &atb0_clk.common.hw, + [CLK_AXI0] = &axi0_clk.common.hw, + [CLK_ATB1] = &atb1_clk.common.hw, + [CLK_AXI1] = &axi1_clk.common.hw, + [CLK_GTBUS] = >bus_clk.common.hw, + [CLK_AHB0] = &ahb0_clk.common.hw, + [CLK_AHB1] = &ahb1_clk.common.hw, + [CLK_AHB2] = &ahb2_clk.common.hw, + [CLK_APB0] = &apb0_clk.common.hw, + [CLK_APB1] = &apb1_clk.common.hw, + [CLK_CCI400] = &cci400_clk.common.hw, + [CLK_ATS] = &ats_clk.common.hw, + [CLK_TRACE] = &trace_clk.common.hw, + + [CLK_OUT_A] = &out_a_clk.common.hw, + [CLK_OUT_B] = &out_b_clk.common.hw, + + [CLK_NAND0_0] = &nand0_0_clk.common.hw, + [CLK_NAND0_1] = &nand0_1_clk.common.hw, + [CLK_NAND1_0] = &nand1_0_clk.common.hw, + [CLK_NAND1_1] = &nand1_1_clk.common.hw, + [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, + [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, + [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, + [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, + [CLK_MMC2] = &mmc2_clk.common.hw, + [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, + [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, + [CLK_MMC3] = &mmc3_clk.common.hw, + [CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw, + [CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw, + [CLK_TS] = &ts_clk.common.hw, + [CLK_SS] = &ss_clk.common.hw, + [CLK_SPI0] = &spi0_clk.common.hw, + [CLK_SPI1] = &spi1_clk.common.hw, + [CLK_SPI2] = &spi2_clk.common.hw, + [CLK_SPI3] = &spi3_clk.common.hw, + [CLK_I2S0] = &i2s0_clk.common.hw, + [CLK_I2S1] = &i2s1_clk.common.hw, + [CLK_SPDIF] = &spdif_clk.common.hw, + [CLK_SDRAM] = &sdram_clk.common.hw, + [CLK_DE] = &de_clk.common.hw, + [CLK_EDP] = &edp_clk.common.hw, + [CLK_MP] = &mp_clk.common.hw, + [CLK_LCD0] = &lcd0_clk.common.hw, + [CLK_LCD1] = &lcd1_clk.common.hw, + [CLK_MIPI_DSI0] = &mipi_dsi0_clk.common.hw, + [CLK_MIPI_DSI1] = &mipi_dsi1_clk.common.hw, + [CLK_HDMI] = &hdmi_clk.common.hw, + [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw, + [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, + [CLK_CSI_ISP] = &csi_isp_clk.common.hw, + [CLK_CSI_MISC] = &csi_misc_clk.common.hw, + [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, + [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, + [CLK_FD] = &fd_clk.common.hw, + [CLK_VE] = &ve_clk.common.hw, + [CLK_AVS] = &avs_clk.common.hw, + [CLK_GPU_CORE] = &gpu_core_clk.common.hw, + [CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw, + [CLK_GPU_AXI] = &gpu_axi_clk.common.hw, + [CLK_SATA] = &sata_clk.common.hw, + [CLK_AC97] = &ac97_clk.common.hw, + [CLK_MIPI_HSI] = &mipi_hsi_clk.common.hw, + [CLK_GPADC] = &gpadc_clk.common.hw, + [CLK_CIR_TX] = &cir_tx_clk.common.hw, + + [CLK_BUS_FD] = &bus_fd_clk.common.hw, + [CLK_BUS_VE] = &bus_ve_clk.common.hw, + [CLK_BUS_GPU_CTRL] = &bus_gpu_ctrl_clk.common.hw, + [CLK_BUS_SS] = &bus_ss_clk.common.hw, + [CLK_BUS_MMC] = &bus_mmc_clk.common.hw, + [CLK_BUS_NAND0] = &bus_nand0_clk.common.hw, + [CLK_BUS_NAND1] = &bus_nand1_clk.common.hw, + [CLK_BUS_SDRAM] = &bus_sdram_clk.common.hw, + [CLK_BUS_MIPI_HSI] = &bus_mipi_hsi_clk.common.hw, + [CLK_BUS_SATA] = &bus_sata_clk.common.hw, + [CLK_BUS_TS] = &bus_ts_clk.common.hw, + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, + [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw, + [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw, + + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, + [CLK_BUS_USB] = &bus_usb_clk.common.hw, + [CLK_BUS_GMAC] = &bus_gmac_clk.common.hw, + [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, + [CLK_BUS_DMA] = &bus_dma_clk.common.hw, + + [CLK_BUS_LCD0] = &bus_lcd0_clk.common.hw, + [CLK_BUS_LCD1] = &bus_lcd1_clk.common.hw, + [CLK_BUS_EDP] = &bus_edp_clk.common.hw, + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, + [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, + [CLK_BUS_DE] = &bus_de_clk.common.hw, + [CLK_BUS_MP] = &bus_mp_clk.common.hw, + [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, + + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, + [CLK_BUS_PIO] = &bus_pio_clk.common.hw, + [CLK_BUS_AC97] = &bus_ac97_clk.common.hw, + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, + [CLK_BUS_LRADC] = &bus_lradc_clk.common.hw, + [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw, + [CLK_BUS_TWD] = &bus_twd_clk.common.hw, + [CLK_BUS_CIR_TX] = &bus_cir_tx_clk.common.hw, + + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, + [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw, + [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw, + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, + [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, + [CLK_BUS_UART5] = &bus_uart5_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map sun9i_a80_ccu_resets[] = { + /* AHB0 reset controls */ + [RST_BUS_FD] = { 0x5a0, BIT(0) }, + [RST_BUS_VE] = { 0x5a0, BIT(1) }, + [RST_BUS_GPU_CTRL] = { 0x5a0, BIT(3) }, + [RST_BUS_SS] = { 0x5a0, BIT(5) }, + [RST_BUS_MMC] = { 0x5a0, BIT(8) }, + [RST_BUS_NAND0] = { 0x5a0, BIT(12) }, + [RST_BUS_NAND1] = { 0x5a0, BIT(13) }, + [RST_BUS_SDRAM] = { 0x5a0, BIT(14) }, + [RST_BUS_SATA] = { 0x5a0, BIT(16) }, + [RST_BUS_TS] = { 0x5a0, BIT(18) }, + [RST_BUS_SPI0] = { 0x5a0, BIT(20) }, + [RST_BUS_SPI1] = { 0x5a0, BIT(21) }, + [RST_BUS_SPI2] = { 0x5a0, BIT(22) }, + [RST_BUS_SPI3] = { 0x5a0, BIT(23) }, + + /* AHB1 reset controls */ + [RST_BUS_OTG] = { 0x5a4, BIT(0) }, + [RST_BUS_OTG_PHY] = { 0x5a4, BIT(1) }, + [RST_BUS_MIPI_HSI] = { 0x5a4, BIT(9) }, + [RST_BUS_GMAC] = { 0x5a4, BIT(17) }, + [RST_BUS_MSGBOX] = { 0x5a4, BIT(21) }, + [RST_BUS_SPINLOCK] = { 0x5a4, BIT(22) }, + [RST_BUS_HSTIMER] = { 0x5a4, BIT(23) }, + [RST_BUS_DMA] = { 0x5a4, BIT(24) }, + + /* AHB2 reset controls */ + [RST_BUS_LCD0] = { 0x5a8, BIT(0) }, + [RST_BUS_LCD1] = { 0x5a8, BIT(1) }, + [RST_BUS_EDP] = { 0x5a8, BIT(2) }, + [RST_BUS_LVDS] = { 0x5a8, BIT(3) }, + [RST_BUS_CSI] = { 0x5a8, BIT(4) }, + [RST_BUS_HDMI0] = { 0x5a8, BIT(5) }, + [RST_BUS_HDMI1] = { 0x5a8, BIT(6) }, + [RST_BUS_DE] = { 0x5a8, BIT(7) }, + [RST_BUS_MP] = { 0x5a8, BIT(8) }, + [RST_BUS_GPU] = { 0x5a8, BIT(9) }, + [RST_BUS_MIPI_DSI] = { 0x5a8, BIT(11) }, + + /* APB0 reset controls */ + [RST_BUS_SPDIF] = { 0x5b0, BIT(1) }, + [RST_BUS_AC97] = { 0x5b0, BIT(11) }, + [RST_BUS_I2S0] = { 0x5b0, BIT(12) }, + [RST_BUS_I2S1] = { 0x5b0, BIT(13) }, + [RST_BUS_LRADC] = { 0x5b0, BIT(15) }, + [RST_BUS_GPADC] = { 0x5b0, BIT(17) }, + [RST_BUS_CIR_TX] = { 0x5b0, BIT(19) }, + + /* APB1 reset controls */ + [RST_BUS_I2C0] = { 0x5b4, BIT(0) }, + [RST_BUS_I2C1] = { 0x5b4, BIT(1) }, + [RST_BUS_I2C2] = { 0x5b4, BIT(2) }, + [RST_BUS_I2C3] = { 0x5b4, BIT(3) }, + [RST_BUS_I2C4] = { 0x5b4, BIT(4) }, + [RST_BUS_UART0] = { 0x5b4, BIT(16) }, + [RST_BUS_UART1] = { 0x5b4, BIT(17) }, + [RST_BUS_UART2] = { 0x5b4, BIT(18) }, + [RST_BUS_UART3] = { 0x5b4, BIT(19) }, + [RST_BUS_UART4] = { 0x5b4, BIT(20) }, + [RST_BUS_UART5] = { 0x5b4, BIT(21) }, +}; + +static const struct sunxi_ccu_desc sun9i_a80_ccu_desc = { + .ccu_clks = sun9i_a80_ccu_clks, + .num_ccu_clks = ARRAY_SIZE(sun9i_a80_ccu_clks), + + .hw_clks = &sun9i_a80_hw_clks, + + .resets = sun9i_a80_ccu_resets, + .num_resets = ARRAY_SIZE(sun9i_a80_ccu_resets), +}; + +static int sun9i_a80_ccu_probe(struct platform_device *pdev) +{ + struct resource *res; + void __iomem *reg; + u32 val; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + reg = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + /* Enforce d1 = 0, d2 = 0 for Audio PLL */ + val = readl(reg + SUN9I_A80_PLL_AUDIO_REG); + val &= (BIT(16) & BIT(18)); + writel(val, reg + SUN9I_A80_PLL_AUDIO_REG); + + return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun9i_a80_ccu_desc); +} + +static const struct of_device_id sun9i_a80_ccu_ids[] = { + { .compatible = "allwinner,sun9i-a80-ccu" }, + { } +}; + +static struct platform_driver sun9i_a80_ccu_driver = { + .probe = sun9i_a80_ccu_probe, + .driver = { + .name = "sun9i-a80-ccu", + .of_match_table = sun9i_a80_ccu_ids, + }, +}; +builtin_platform_driver(sun9i_a80_ccu_driver); diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.h b/drivers/clk/sunxi-ng/ccu-sun9i-a80.h new file mode 100644 index 000000000000..315662341c70 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.h @@ -0,0 +1,57 @@ +/* + * Copyright 2016 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CCU_SUN9I_A80_H_ +#define _CCU_SUN9I_A80_H_ + +#include <dt-bindings/clock/sun9i-a80-ccu.h> +#include <dt-bindings/reset/sun9i-a80-ccu.h> + +#define CLK_PLL_C0CPUX 0 +#define CLK_PLL_C1CPUX 1 + +/* pll-audio and pll-periph0 are exported to the PRCM block */ + +#define CLK_PLL_VE 4 +#define CLK_PLL_DDR 5 +#define CLK_PLL_VIDEO0 6 +#define CLK_PLL_VIDEO1 7 +#define CLK_PLL_GPU 8 +#define CLK_PLL_DE 9 +#define CLK_PLL_ISP 10 +#define CLK_PLL_PERIPH1 11 + +/* The CPUX clocks are exported */ + +#define CLK_ATB0 14 +#define CLK_AXI0 15 +#define CLK_ATB1 16 +#define CLK_AXI1 17 +#define CLK_GTBUS 18 +#define CLK_AHB0 19 +#define CLK_AHB1 20 +#define CLK_AHB2 21 +#define CLK_APB0 22 +#define CLK_APB1 23 +#define CLK_CCI400 24 +#define CLK_ATS 25 +#define CLK_TRACE 26 + +/* module clocks and bus gates exported */ + +#define CLK_NUMBER (CLK_BUS_UART5 + 1) + +#endif /* _CCU_SUN9I_A80_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-ccu.h b/include/dt-bindings/clock/sun9i-a80-ccu.h new file mode 100644 index 000000000000..6ea1492a73a6 --- /dev/null +++ b/include/dt-bindings/clock/sun9i-a80-ccu.h @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ +#define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ + +#define CLK_PLL_AUDIO 2 +#define CLK_PLL_PERIPH0 3 + +#define CLK_C0CPUX 12 +#define CLK_C1CPUX 13 + +#define CLK_OUT_A 27 +#define CLK_OUT_B 28 + +#define CLK_NAND0_0 29 +#define CLK_NAND0_1 30 +#define CLK_NAND1_0 31 +#define CLK_NAND1_1 32 +#define CLK_MMC0 33 +#define CLK_MMC0_SAMPLE 34 +#define CLK_MMC0_OUTPUT 35 +#define CLK_MMC1 36 +#define CLK_MMC1_SAMPLE 37 +#define CLK_MMC1_OUTPUT 38 +#define CLK_MMC2 39 +#define CLK_MMC2_SAMPLE 40 +#define CLK_MMC2_OUTPUT 41 +#define CLK_MMC3 42 +#define CLK_MMC3_SAMPLE 43 +#define CLK_MMC3_OUTPUT 44 +#define CLK_TS 45 +#define CLK_SS 46 +#define CLK_SPI0 47 +#define CLK_SPI1 48 +#define CLK_SPI2 49 +#define CLK_SPI3 50 +#define CLK_I2S0 51 +#define CLK_I2S1 52 +#define CLK_SPDIF 53 +#define CLK_SDRAM 54 +#define CLK_DE 55 +#define CLK_EDP 56 +#define CLK_MP 57 +#define CLK_LCD0 58 +#define CLK_LCD1 59 +#define CLK_MIPI_DSI0 60 +#define CLK_MIPI_DSI1 61 +#define CLK_HDMI 62 +#define CLK_HDMI_SLOW 63 +#define CLK_MIPI_CSI 64 +#define CLK_CSI_ISP 65 +#define CLK_CSI_MISC 66 +#define CLK_CSI0_MCLK 67 +#define CLK_CSI1_MCLK 68 +#define CLK_FD 69 +#define CLK_VE 70 +#define CLK_AVS 71 +#define CLK_GPU_CORE 72 +#define CLK_GPU_MEMORY 73 +#define CLK_GPU_AXI 74 +#define CLK_SATA 75 +#define CLK_AC97 76 +#define CLK_MIPI_HSI 77 +#define CLK_GPADC 78 +#define CLK_CIR_TX 79 + +#define CLK_BUS_FD 80 +#define CLK_BUS_VE 81 +#define CLK_BUS_GPU_CTRL 82 +#define CLK_BUS_SS 83 +#define CLK_BUS_MMC 84 +#define CLK_BUS_NAND0 85 +#define CLK_BUS_NAND1 86 +#define CLK_BUS_SDRAM 87 +#define CLK_BUS_MIPI_HSI 88 +#define CLK_BUS_SATA 89 +#define CLK_BUS_TS 90 +#define CLK_BUS_SPI0 91 +#define CLK_BUS_SPI1 92 +#define CLK_BUS_SPI2 93 +#define CLK_BUS_SPI3 94 + +#define CLK_BUS_OTG 95 +#define CLK_BUS_USB 96 +#define CLK_BUS_GMAC 97 +#define CLK_BUS_MSGBOX 98 +#define CLK_BUS_SPINLOCK 99 +#define CLK_BUS_HSTIMER 100 +#define CLK_BUS_DMA 101 + +#define CLK_BUS_LCD0 102 +#define CLK_BUS_LCD1 103 +#define CLK_BUS_EDP 104 +#define CLK_BUS_CSI 105 +#define CLK_BUS_HDMI 106 +#define CLK_BUS_DE 107 +#define CLK_BUS_MP 108 +#define CLK_BUS_MIPI_DSI 109 + +#define CLK_BUS_SPDIF 110 +#define CLK_BUS_PIO 111 +#define CLK_BUS_AC97 112 +#define CLK_BUS_I2S0 113 +#define CLK_BUS_I2S1 114 +#define CLK_BUS_LRADC 115 +#define CLK_BUS_GPADC 116 +#define CLK_BUS_TWD 117 +#define CLK_BUS_CIR_TX 118 + +#define CLK_BUS_I2C0 119 +#define CLK_BUS_I2C1 120 +#define CLK_BUS_I2C2 121 +#define CLK_BUS_I2C3 122 +#define CLK_BUS_I2C4 123 +#define CLK_BUS_UART0 124 +#define CLK_BUS_UART1 125 +#define CLK_BUS_UART2 126 +#define CLK_BUS_UART3 127 +#define CLK_BUS_UART4 128 +#define CLK_BUS_UART5 129 + +#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun9i-a80-ccu.h b/include/dt-bindings/reset/sun9i-a80-ccu.h new file mode 100644 index 000000000000..4b8df4b36788 --- /dev/null +++ b/include/dt-bindings/reset/sun9i-a80-ccu.h @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ +#define _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ + +#define RST_BUS_FD 0 +#define RST_BUS_VE 1 +#define RST_BUS_GPU_CTRL 2 +#define RST_BUS_SS 3 +#define RST_BUS_MMC 4 +#define RST_BUS_NAND0 5 +#define RST_BUS_NAND1 6 +#define RST_BUS_SDRAM 7 +#define RST_BUS_SATA 8 +#define RST_BUS_TS 9 +#define RST_BUS_SPI0 10 +#define RST_BUS_SPI1 11 +#define RST_BUS_SPI2 12 +#define RST_BUS_SPI3 13 + +#define RST_BUS_OTG 14 +#define RST_BUS_OTG_PHY 15 +#define RST_BUS_MIPI_HSI 16 +#define RST_BUS_GMAC 17 +#define RST_BUS_MSGBOX 18 +#define RST_BUS_SPINLOCK 19 +#define RST_BUS_HSTIMER 20 +#define RST_BUS_DMA 21 + +#define RST_BUS_LCD0 22 +#define RST_BUS_LCD1 23 +#define RST_BUS_EDP 24 +#define RST_BUS_LVDS 25 +#define RST_BUS_CSI 26 +#define RST_BUS_HDMI0 27 +#define RST_BUS_HDMI1 28 +#define RST_BUS_DE 29 +#define RST_BUS_MP 30 +#define RST_BUS_GPU 31 +#define RST_BUS_MIPI_DSI 32 + +#define RST_BUS_SPDIF 33 +#define RST_BUS_AC97 34 +#define RST_BUS_I2S0 35 +#define RST_BUS_I2S1 36 +#define RST_BUS_LRADC 37 +#define RST_BUS_GPADC 38 +#define RST_BUS_CIR_TX 39 + +#define RST_BUS_I2C0 40 +#define RST_BUS_I2C1 41 +#define RST_BUS_I2C2 42 +#define RST_BUS_I2C3 43 +#define RST_BUS_I2C4 44 +#define RST_BUS_UART0 45 +#define RST_BUS_UART1 46 +#define RST_BUS_UART2 47 +#define RST_BUS_UART3 48 +#define RST_BUS_UART4 49 +#define RST_BUS_UART5 50 + +#endif /* _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ */ -- 2.11.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH 05/11] clk: sunxi-ng: Add A80 CCU 2017-01-24 2:32 ` [PATCH 05/11] clk: sunxi-ng: Add A80 CCU Chen-Yu Tsai @ 2017-01-27 21:13 ` Rob Herring 0 siblings, 0 replies; 33+ messages in thread From: Rob Herring @ 2017-01-27 21:13 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Maxime Ripard, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi On Tue, Jan 24, 2017 at 10:32:24AM +0800, Chen-Yu Tsai wrote: > Add support for the main clock unit found in the A80. > > Note that on the A80, some subsystems have separate clock controllers > downstream of the main clock unit. These include the MMC, USB, and > display engine subsystems. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + Acked-by: Rob Herring <robh@kernel.org> > drivers/clk/sunxi-ng/Kconfig | 10 + > drivers/clk/sunxi-ng/Makefile | 1 + > drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 1223 ++++++++++++++++++++ > drivers/clk/sunxi-ng/ccu-sun9i-a80.h | 57 + > include/dt-bindings/clock/sun9i-a80-ccu.h | 162 +++ > include/dt-bindings/reset/sun9i-a80-ccu.h | 102 ++ > 7 files changed, 1556 insertions(+) > create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80.c > create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80.h > create mode 100644 include/dt-bindings/clock/sun9i-a80-ccu.h > create mode 100644 include/dt-bindings/reset/sun9i-a80-ccu.h ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 06/11] clk: sunxi-ng: Add A80 USB CCU 2017-01-24 2:32 [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai ` (4 preceding siblings ...) 2017-01-24 2:32 ` [PATCH 05/11] clk: sunxi-ng: Add A80 CCU Chen-Yu Tsai @ 2017-01-24 2:32 ` Chen-Yu Tsai 2017-01-26 10:14 ` Maxime Ripard 2017-01-27 21:15 ` Rob Herring 2017-01-24 2:32 ` [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU Chen-Yu Tsai ` (5 subsequent siblings) 11 siblings, 2 replies; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-24 2:32 UTC (permalink / raw) To: Maxime Ripard, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd Cc: Chen-Yu Tsai, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi Add support for the USB clock controls found on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- .../devicetree/bindings/clock/sun9i-usb.txt | 24 ++++ drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c | 144 +++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h | 25 ++++ include/dt-bindings/clock/sun9i-a80-usb.h | 59 +++++++++ include/dt-bindings/reset/sun9i-a80-usb.h | 56 ++++++++ 6 files changed, 309 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sun9i-usb.txt create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h create mode 100644 include/dt-bindings/clock/sun9i-a80-usb.h create mode 100644 include/dt-bindings/reset/sun9i-a80-usb.h diff --git a/Documentation/devicetree/bindings/clock/sun9i-usb.txt b/Documentation/devicetree/bindings/clock/sun9i-usb.txt new file mode 100644 index 000000000000..c2d38626eaaa --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sun9i-usb.txt @@ -0,0 +1,24 @@ +Allwinner A80 USB Clock Control Binding +------------------------------------ + +Required properties : +- compatible: must contain one of the following compatibles: + - "allwinner,sun9i-a80-usb-clocks" + +- reg: Must contain the registers base address and length +- clocks: phandle to the clocks feeding the USB subsystem. Two are needed: + - "bus": the bus clock for the whole USB subsystem + - "hosc": the high frequency oscillator (usually at 24MHz) +- clock-names: Must contain the clock names described just above +- #clock-cells : must contain 1 +- #reset-cells : must contain 1 + +Example: +usb_clocks: clock@00a08000 { + compatible = "allwinner,sun9i-a80-usb-clks"; + reg = <0x00a08000 0x8>; + clocks = <&ccu CLK_BUS_USB>, <&osc24M>; + clock-names = "bus", "hosc"; + #clock-cells = <1>; + #reset-cells = <1>; +}; diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 126bb7c1c3f7..8f37ef7fb67d 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -26,3 +26,4 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c new file mode 100644 index 000000000000..1d76f24f7df3 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> + +#include "ccu_common.h" +#include "ccu_gate.h" +#include "ccu_reset.h" + +#include "ccu-sun9i-a80-usb.h" + +static SUNXI_CCU_GATE(bus_hci0_clk, "bus-hci0", "bus-usb", 0x0, BIT(1), 0); +static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 0x0, BIT(2), 0); +static SUNXI_CCU_GATE(bus_hci1_clk, "bus-hci1", "bus-usb", 0x0, BIT(3), 0); +static SUNXI_CCU_GATE(bus_hci2_clk, "bus-hci2", "bus-usb", 0x0, BIT(5), 0); +static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M", 0x0, BIT(6), 0); + +static SUNXI_CCU_GATE(usb0_phy_clk, "usb0-phy", "osc24M", 0x4, BIT(1), 0); +static SUNXI_CCU_GATE(usb1_hsic_clk, "usb1-hsic", "osc24M", 0x4, BIT(2), 0); +static SUNXI_CCU_GATE(usb1_phy_clk, "usb1-phy", "osc24M", 0x4, BIT(3), 0); +static SUNXI_CCU_GATE(usb2_hsic_clk, "usb2-hsic", "osc24M", 0x4, BIT(4), 0); +static SUNXI_CCU_GATE(usb2_phy_clk, "usb2-phy", "osc24M", 0x4, BIT(5), 0); +static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "osc24M", 0x4, BIT(10), 0); + +static struct ccu_common *sun9i_a80_usb_clks[] = { + &bus_hci0_clk.common, + &usb_ohci0_clk.common, + &bus_hci1_clk.common, + &bus_hci2_clk.common, + &usb_ohci2_clk.common, + + &usb0_phy_clk.common, + &usb1_hsic_clk.common, + &usb1_phy_clk.common, + &usb2_hsic_clk.common, + &usb2_phy_clk.common, + &usb_hsic_clk.common, +}; + +static struct clk_hw_onecell_data sun9i_a80_usb_hw_clks = { + .hws = { + [CLK_BUS_HCI0] = &bus_hci0_clk.common.hw, + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, + [CLK_BUS_HCI1] = &bus_hci1_clk.common.hw, + [CLK_BUS_HCI2] = &bus_hci2_clk.common.hw, + [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw, + + [CLK_USB0_PHY] = &usb0_phy_clk.common.hw, + [CLK_USB1_HSIC] = &usb1_hsic_clk.common.hw, + [CLK_USB1_PHY] = &usb1_phy_clk.common.hw, + [CLK_USB2_HSIC] = &usb2_hsic_clk.common.hw, + [CLK_USB2_PHY] = &usb2_phy_clk.common.hw, + [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map sun9i_a80_usb_resets[] = { + [RST_USB0_HCI] = { 0x0, BIT(17) }, + [RST_USB1_HCI] = { 0x0, BIT(18) }, + [RST_USB2_HCI] = { 0x0, BIT(19) }, + + [RST_USB0_PHY] = { 0x4, BIT(17) }, + [RST_USB1_HSIC] = { 0x4, BIT(18) }, + [RST_USB1_PHY] = { 0x4, BIT(19) }, + [RST_USB2_HSIC] = { 0x4, BIT(20) }, + [RST_USB2_PHY] = { 0x4, BIT(21) }, +}; + +static const struct sunxi_ccu_desc sun9i_a80_usb_clk_desc = { + .ccu_clks = sun9i_a80_usb_clks, + .num_ccu_clks = ARRAY_SIZE(sun9i_a80_usb_clks), + + .hw_clks = &sun9i_a80_usb_hw_clks, + + .resets = sun9i_a80_usb_resets, + .num_resets = ARRAY_SIZE(sun9i_a80_usb_resets), +}; + +static int sun9i_a80_usb_clk_probe(struct platform_device *pdev) +{ + struct resource *res; + struct clk *bus_clk; + void __iomem *reg; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + reg = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + bus_clk = devm_clk_get(&pdev->dev, "bus"); + if (IS_ERR(bus_clk)) { + ret = PTR_ERR(bus_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret); + return ret; + } + + /* The bus clock needs to be enabled for us to access the registers */ + ret = clk_prepare_enable(bus_clk); + if (ret) { + dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret); + return ret; + } + + ret = sunxi_ccu_probe(pdev->dev.of_node, reg, + &sun9i_a80_usb_clk_desc); + if (ret) + goto err_disable_clk; + + return 0; + +err_disable_clk: + clk_disable_unprepare(bus_clk); + return ret; +} + +static const struct of_device_id sun9i_a80_usb_clk_ids[] = { + { .compatible = "allwinner,sun9i-a80-usb-clks" }, + { } +}; + +static struct platform_driver sun9i_a80_usb_clk_driver = { + .probe = sun9i_a80_usb_clk_probe, + .driver = { + .name = "sun9i-a80-usb-clks", + .of_match_table = sun9i_a80_usb_clk_ids, + }, +}; +builtin_platform_driver(sun9i_a80_usb_clk_driver); diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h b/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h new file mode 100644 index 000000000000..a184280ba854 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h @@ -0,0 +1,25 @@ +/* + * Copyright 2016 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CCU_SUN9I_A80_USB_H_ +#define _CCU_SUN9I_A80_USB_H_ + +#include <dt-bindings/clock/sun9i-a80-usb.h> +#include <dt-bindings/reset/sun9i-a80-usb.h> + +#define CLK_NUMBER (CLK_USB_HSIC + 1) + +#endif /* _CCU_SUN9I_A80_USB_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-usb.h b/include/dt-bindings/clock/sun9i-a80-usb.h new file mode 100644 index 000000000000..783a60d2ccea --- /dev/null +++ b/include/dt-bindings/clock/sun9i-a80-usb.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ +#define _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ + +#define CLK_BUS_HCI0 0 +#define CLK_USB_OHCI0 1 +#define CLK_BUS_HCI1 2 +#define CLK_BUS_HCI2 3 +#define CLK_USB_OHCI2 4 + +#define CLK_USB0_PHY 5 +#define CLK_USB1_HSIC 6 +#define CLK_USB1_PHY 7 +#define CLK_USB2_HSIC 8 +#define CLK_USB2_PHY 9 +#define CLK_USB_HSIC 10 + +#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ */ diff --git a/include/dt-bindings/reset/sun9i-a80-usb.h b/include/dt-bindings/reset/sun9i-a80-usb.h new file mode 100644 index 000000000000..ee492864c2aa --- /dev/null +++ b/include/dt-bindings/reset/sun9i-a80-usb.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ +#define _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ + +#define RST_USB0_HCI 0 +#define RST_USB1_HCI 1 +#define RST_USB2_HCI 2 + +#define RST_USB0_PHY 3 +#define RST_USB1_HSIC 4 +#define RST_USB1_PHY 5 +#define RST_USB2_HSIC 6 +#define RST_USB2_PHY 7 + +#endif /* _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ */ -- 2.11.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH 06/11] clk: sunxi-ng: Add A80 USB CCU 2017-01-24 2:32 ` [PATCH 06/11] clk: sunxi-ng: Add A80 USB CCU Chen-Yu Tsai @ 2017-01-26 10:14 ` Maxime Ripard 2017-01-26 11:12 ` [linux-sunxi] " Chen-Yu Tsai 2017-01-27 21:15 ` Rob Herring 1 sibling, 1 reply; 33+ messages in thread From: Maxime Ripard @ 2017-01-26 10:14 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 4341 bytes --] Hi, On Tue, Jan 24, 2017 at 10:32:25AM +0800, Chen-Yu Tsai wrote: > Add support for the USB clock controls found on the A80. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > .../devicetree/bindings/clock/sun9i-usb.txt | 24 ++++ > drivers/clk/sunxi-ng/Makefile | 1 + > drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c | 144 +++++++++++++++++++++ > drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h | 25 ++++ > include/dt-bindings/clock/sun9i-a80-usb.h | 59 +++++++++ > include/dt-bindings/reset/sun9i-a80-usb.h | 56 ++++++++ > 6 files changed, 309 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/sun9i-usb.txt > create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c > create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h > create mode 100644 include/dt-bindings/clock/sun9i-a80-usb.h > create mode 100644 include/dt-bindings/reset/sun9i-a80-usb.h > > diff --git a/Documentation/devicetree/bindings/clock/sun9i-usb.txt b/Documentation/devicetree/bindings/clock/sun9i-usb.txt > new file mode 100644 > index 000000000000..c2d38626eaaa > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/sun9i-usb.txt > @@ -0,0 +1,24 @@ > +Allwinner A80 USB Clock Control Binding > +------------------------------------ > + > +Required properties : > +- compatible: must contain one of the following compatibles: > + - "allwinner,sun9i-a80-usb-clocks" > + > +- reg: Must contain the registers base address and length > +- clocks: phandle to the clocks feeding the USB subsystem. Two are needed: > + - "bus": the bus clock for the whole USB subsystem > + - "hosc": the high frequency oscillator (usually at 24MHz) > +- clock-names: Must contain the clock names described just above > +- #clock-cells : must contain 1 > +- #reset-cells : must contain 1 > + > +Example: > +usb_clocks: clock@00a08000 { > + compatible = "allwinner,sun9i-a80-usb-clks"; > + reg = <0x00a08000 0x8>; > + clocks = <&ccu CLK_BUS_USB>, <&osc24M>; > + clock-names = "bus", "hosc"; > + #clock-cells = <1>; > + #reset-cells = <1>; > +}; > diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile > index 126bb7c1c3f7..8f37ef7fb67d 100644 > --- a/drivers/clk/sunxi-ng/Makefile > +++ b/drivers/clk/sunxi-ng/Makefile > @@ -26,3 +26,4 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o > obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o > obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o > obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o > +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o > diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c > new file mode 100644 > index 000000000000..1d76f24f7df3 > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c > @@ -0,0 +1,144 @@ > +/* > + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/clk-provider.h> > +#include <linux/of_address.h> > +#include <linux/platform_device.h> > + > +#include "ccu_common.h" > +#include "ccu_gate.h" > +#include "ccu_reset.h" > + > +#include "ccu-sun9i-a80-usb.h" > + > +static SUNXI_CCU_GATE(bus_hci0_clk, "bus-hci0", "bus-usb", 0x0, BIT(1), 0); > +static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 0x0, BIT(2), 0); > +static SUNXI_CCU_GATE(bus_hci1_clk, "bus-hci1", "bus-usb", 0x0, BIT(3), 0); > +static SUNXI_CCU_GATE(bus_hci2_clk, "bus-hci2", "bus-usb", 0x0, BIT(5), 0); > +static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M", 0x0, BIT(6), 0); In the current !sunxi-ng driver, there's a clock at offset 4, did you forget it? Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 801 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [linux-sunxi] Re: [PATCH 06/11] clk: sunxi-ng: Add A80 USB CCU 2017-01-26 10:14 ` Maxime Ripard @ 2017-01-26 11:12 ` Chen-Yu Tsai 2017-01-27 8:45 ` Maxime Ripard 0 siblings, 1 reply; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-26 11:12 UTC (permalink / raw) To: Maxime Ripard Cc: Chen-Yu Tsai, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi On Thu, Jan 26, 2017 at 6:14 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Hi, > > On Tue, Jan 24, 2017 at 10:32:25AM +0800, Chen-Yu Tsai wrote: >> Add support for the USB clock controls found on the A80. >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> >> --- >> .../devicetree/bindings/clock/sun9i-usb.txt | 24 ++++ >> drivers/clk/sunxi-ng/Makefile | 1 + >> drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c | 144 +++++++++++++++++++++ >> drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h | 25 ++++ >> include/dt-bindings/clock/sun9i-a80-usb.h | 59 +++++++++ >> include/dt-bindings/reset/sun9i-a80-usb.h | 56 ++++++++ >> 6 files changed, 309 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/sun9i-usb.txt >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h >> create mode 100644 include/dt-bindings/clock/sun9i-a80-usb.h >> create mode 100644 include/dt-bindings/reset/sun9i-a80-usb.h >> >> diff --git a/Documentation/devicetree/bindings/clock/sun9i-usb.txt b/Documentation/devicetree/bindings/clock/sun9i-usb.txt >> new file mode 100644 >> index 000000000000..c2d38626eaaa >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/sun9i-usb.txt >> @@ -0,0 +1,24 @@ >> +Allwinner A80 USB Clock Control Binding >> +------------------------------------ >> + >> +Required properties : >> +- compatible: must contain one of the following compatibles: >> + - "allwinner,sun9i-a80-usb-clocks" >> + >> +- reg: Must contain the registers base address and length >> +- clocks: phandle to the clocks feeding the USB subsystem. Two are needed: >> + - "bus": the bus clock for the whole USB subsystem >> + - "hosc": the high frequency oscillator (usually at 24MHz) >> +- clock-names: Must contain the clock names described just above >> +- #clock-cells : must contain 1 >> +- #reset-cells : must contain 1 >> + >> +Example: >> +usb_clocks: clock@00a08000 { >> + compatible = "allwinner,sun9i-a80-usb-clks"; >> + reg = <0x00a08000 0x8>; >> + clocks = <&ccu CLK_BUS_USB>, <&osc24M>; >> + clock-names = "bus", "hosc"; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> +}; >> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile >> index 126bb7c1c3f7..8f37ef7fb67d 100644 >> --- a/drivers/clk/sunxi-ng/Makefile >> +++ b/drivers/clk/sunxi-ng/Makefile >> @@ -26,3 +26,4 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o >> obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o >> obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o >> +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o >> diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c >> new file mode 100644 >> index 000000000000..1d76f24f7df3 >> --- /dev/null >> +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c >> @@ -0,0 +1,144 @@ >> +/* >> + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. >> + * >> + * This software is licensed under the terms of the GNU General Public >> + * License version 2, as published by the Free Software Foundation, and >> + * may be copied, distributed, and modified under those terms. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + */ >> + >> +#include <linux/clk.h> >> +#include <linux/clk-provider.h> >> +#include <linux/of_address.h> >> +#include <linux/platform_device.h> >> + >> +#include "ccu_common.h" >> +#include "ccu_gate.h" >> +#include "ccu_reset.h" >> + >> +#include "ccu-sun9i-a80-usb.h" >> + >> +static SUNXI_CCU_GATE(bus_hci0_clk, "bus-hci0", "bus-usb", 0x0, BIT(1), 0); >> +static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 0x0, BIT(2), 0); >> +static SUNXI_CCU_GATE(bus_hci1_clk, "bus-hci1", "bus-usb", 0x0, BIT(3), 0); >> +static SUNXI_CCU_GATE(bus_hci2_clk, "bus-hci2", "bus-usb", 0x0, BIT(5), 0); >> +static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M", 0x0, BIT(6), 0); > > In the current !sunxi-ng driver, there's a clock at offset 4, did you > forget it? It supposedly is for ohci1, but since the second USB host is HSIC only, and Allwinner does not even list ohci1 in its documents, it probably isn't there. IIRC the gate itself can be toggled. But there probably isn't anything connected. The old driver having a gate for it would be my mistake. ChenYu ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [linux-sunxi] Re: [PATCH 06/11] clk: sunxi-ng: Add A80 USB CCU 2017-01-26 11:12 ` [linux-sunxi] " Chen-Yu Tsai @ 2017-01-27 8:45 ` Maxime Ripard 0 siblings, 0 replies; 33+ messages in thread From: Maxime Ripard @ 2017-01-27 8:45 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 5144 bytes --] On Thu, Jan 26, 2017 at 07:12:44PM +0800, Chen-Yu Tsai wrote: > On Thu, Jan 26, 2017 at 6:14 PM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: > > Hi, > > > > On Tue, Jan 24, 2017 at 10:32:25AM +0800, Chen-Yu Tsai wrote: > >> Add support for the USB clock controls found on the A80. > >> > >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> > >> --- > >> .../devicetree/bindings/clock/sun9i-usb.txt | 24 ++++ > >> drivers/clk/sunxi-ng/Makefile | 1 + > >> drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c | 144 +++++++++++++++++++++ > >> drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h | 25 ++++ > >> include/dt-bindings/clock/sun9i-a80-usb.h | 59 +++++++++ > >> include/dt-bindings/reset/sun9i-a80-usb.h | 56 ++++++++ > >> 6 files changed, 309 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/clock/sun9i-usb.txt > >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c > >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h > >> create mode 100644 include/dt-bindings/clock/sun9i-a80-usb.h > >> create mode 100644 include/dt-bindings/reset/sun9i-a80-usb.h > >> > >> diff --git a/Documentation/devicetree/bindings/clock/sun9i-usb.txt b/Documentation/devicetree/bindings/clock/sun9i-usb.txt > >> new file mode 100644 > >> index 000000000000..c2d38626eaaa > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/clock/sun9i-usb.txt > >> @@ -0,0 +1,24 @@ > >> +Allwinner A80 USB Clock Control Binding > >> +------------------------------------ > >> + > >> +Required properties : > >> +- compatible: must contain one of the following compatibles: > >> + - "allwinner,sun9i-a80-usb-clocks" > >> + > >> +- reg: Must contain the registers base address and length > >> +- clocks: phandle to the clocks feeding the USB subsystem. Two are needed: > >> + - "bus": the bus clock for the whole USB subsystem > >> + - "hosc": the high frequency oscillator (usually at 24MHz) > >> +- clock-names: Must contain the clock names described just above > >> +- #clock-cells : must contain 1 > >> +- #reset-cells : must contain 1 > >> + > >> +Example: > >> +usb_clocks: clock@00a08000 { > >> + compatible = "allwinner,sun9i-a80-usb-clks"; > >> + reg = <0x00a08000 0x8>; > >> + clocks = <&ccu CLK_BUS_USB>, <&osc24M>; > >> + clock-names = "bus", "hosc"; > >> + #clock-cells = <1>; > >> + #reset-cells = <1>; > >> +}; > >> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile > >> index 126bb7c1c3f7..8f37ef7fb67d 100644 > >> --- a/drivers/clk/sunxi-ng/Makefile > >> +++ b/drivers/clk/sunxi-ng/Makefile > >> @@ -26,3 +26,4 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o > >> obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o > >> obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o > >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o > >> +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o > >> diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c > >> new file mode 100644 > >> index 000000000000..1d76f24f7df3 > >> --- /dev/null > >> +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c > >> @@ -0,0 +1,144 @@ > >> +/* > >> + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. > >> + * > >> + * This software is licensed under the terms of the GNU General Public > >> + * License version 2, as published by the Free Software Foundation, and > >> + * may be copied, distributed, and modified under those terms. > >> + * > >> + * This program is distributed in the hope that it will be useful, > >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of > >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > >> + * GNU General Public License for more details. > >> + */ > >> + > >> +#include <linux/clk.h> > >> +#include <linux/clk-provider.h> > >> +#include <linux/of_address.h> > >> +#include <linux/platform_device.h> > >> + > >> +#include "ccu_common.h" > >> +#include "ccu_gate.h" > >> +#include "ccu_reset.h" > >> + > >> +#include "ccu-sun9i-a80-usb.h" > >> + > >> +static SUNXI_CCU_GATE(bus_hci0_clk, "bus-hci0", "bus-usb", 0x0, BIT(1), 0); > >> +static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 0x0, BIT(2), 0); > >> +static SUNXI_CCU_GATE(bus_hci1_clk, "bus-hci1", "bus-usb", 0x0, BIT(3), 0); > >> +static SUNXI_CCU_GATE(bus_hci2_clk, "bus-hci2", "bus-usb", 0x0, BIT(5), 0); > >> +static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M", 0x0, BIT(6), 0); > > > > In the current !sunxi-ng driver, there's a clock at offset 4, did you > > forget it? > > It supposedly is for ohci1, but since the second USB host is HSIC > only, and Allwinner does not even list ohci1 in its documents, it > probably isn't there. IIRC the gate itself can be toggled. But > there probably isn't anything connected. The old driver having > a gate for it would be my mistake. Ok :) Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 801 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 06/11] clk: sunxi-ng: Add A80 USB CCU 2017-01-24 2:32 ` [PATCH 06/11] clk: sunxi-ng: Add A80 USB CCU Chen-Yu Tsai 2017-01-26 10:14 ` Maxime Ripard @ 2017-01-27 21:15 ` Rob Herring 1 sibling, 0 replies; 33+ messages in thread From: Rob Herring @ 2017-01-27 21:15 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Maxime Ripard, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi On Tue, Jan 24, 2017 at 10:32:25AM +0800, Chen-Yu Tsai wrote: > Add support for the USB clock controls found on the A80. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > .../devicetree/bindings/clock/sun9i-usb.txt | 24 ++++ > drivers/clk/sunxi-ng/Makefile | 1 + > drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c | 144 +++++++++++++++++++++ > drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h | 25 ++++ > include/dt-bindings/clock/sun9i-a80-usb.h | 59 +++++++++ > include/dt-bindings/reset/sun9i-a80-usb.h | 56 ++++++++ > 6 files changed, 309 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/sun9i-usb.txt > create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c > create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.h > create mode 100644 include/dt-bindings/clock/sun9i-a80-usb.h > create mode 100644 include/dt-bindings/reset/sun9i-a80-usb.h > > diff --git a/Documentation/devicetree/bindings/clock/sun9i-usb.txt b/Documentation/devicetree/bindings/clock/sun9i-usb.txt > new file mode 100644 > index 000000000000..c2d38626eaaa > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/sun9i-usb.txt > @@ -0,0 +1,24 @@ > +Allwinner A80 USB Clock Control Binding > +------------------------------------ > + > +Required properties : > +- compatible: must contain one of the following compatibles: > + - "allwinner,sun9i-a80-usb-clocks" > + > +- reg: Must contain the registers base address and length > +- clocks: phandle to the clocks feeding the USB subsystem. Two are needed: > + - "bus": the bus clock for the whole USB subsystem > + - "hosc": the high frequency oscillator (usually at 24MHz) > +- clock-names: Must contain the clock names described just above > +- #clock-cells : must contain 1 > +- #reset-cells : must contain 1 > + > +Example: > +usb_clocks: clock@00a08000 { Drop leading 0s. With that, for the binding: Acked-by: Rob Herring <robh@kernel.org> > + compatible = "allwinner,sun9i-a80-usb-clks"; > + reg = <0x00a08000 0x8>; > + clocks = <&ccu CLK_BUS_USB>, <&osc24M>; > + clock-names = "bus", "hosc"; > + #clock-cells = <1>; > + #reset-cells = <1>; > +}; ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU 2017-01-24 2:32 [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai ` (5 preceding siblings ...) 2017-01-24 2:32 ` [PATCH 06/11] clk: sunxi-ng: Add A80 USB CCU Chen-Yu Tsai @ 2017-01-24 2:32 ` Chen-Yu Tsai 2017-01-26 10:39 ` Maxime Ripard 2017-01-24 2:32 ` [PATCH 08/11] ARM: dts: sun8i-a23-q8-tablet: Drop pinmux setting for codec PA gpio Chen-Yu Tsai ` (4 subsequent siblings) 11 siblings, 1 reply; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-24 2:32 UTC (permalink / raw) To: Maxime Ripard, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd Cc: Chen-Yu Tsai, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi Add support for the display engine clock controls found on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- .../devicetree/bindings/clock/sun9i-de.txt | 28 ++ drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 283 +++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h | 33 +++ include/dt-bindings/clock/sun9i-a80-de.h | 80 ++++++ include/dt-bindings/reset/sun9i-a80-de.h | 58 +++++ 6 files changed, 483 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h create mode 100644 include/dt-bindings/clock/sun9i-a80-de.h create mode 100644 include/dt-bindings/reset/sun9i-a80-de.h diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt new file mode 100644 index 000000000000..3a5e6df70677 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sun9i-de.txt @@ -0,0 +1,28 @@ +Allwinner A80 Display Engine Clock Control Binding +------------------------------------ + +Required properties : +- compatible: must contain one of the following compatibles: + - "allwinner,sun9i-a80-de-clocks" + +- reg: Must contain the registers base address and length +- clocks: phandle to the clocks feeding the display engine subsystem. + Three are needed: + - "mod": the display engine module clock + - "dram": the DRAM bus clock for the system + - "bus": the bus clock for the whole display engine subsystem +- clock-names: Must contain the clock names described just above +- resets: phandle to the reset control for the display engine subsystem. +- #clock-cells : must contain 1 +- #reset-cells : must contain 1 + +Example: +de_clocks: clock@03000000 { + compatible = "allwinner,sun9i-a80-de-clks"; + reg = <0x03000000 0x30>; + clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; + clock-names = "mod", "dram", "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; +}; diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 8f37ef7fb67d..6feaac0c5600 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -26,4 +26,5 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c new file mode 100644 index 000000000000..3fc27db0a49a --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/reset.h> + +#include "ccu_common.h" +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_reset.h" + +#include "ccu-sun9i-a80-de.h" + +static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div", + 0x00, BIT(0), 0); +static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div", + 0x00, BIT(1), 0); +static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div", + 0x00, BIT(2), 0); +static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de", + 0x00, BIT(4), 0); +static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de", + 0x00, BIT(5), 0); +static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div", + 0x00, BIT(8), 0); +static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div", + 0x00, BIT(9), 0); +static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div", + 0x00, BIT(10), 0); +static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de", + 0x00, BIT(12), 0); +static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de", + 0x00, BIT(13), 0); +static SUNXI_CCU_GATE(merge_clk, "merge", "de", + 0x00, BIT(20), 0); + +static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram", + 0x04, BIT(0), 0); +static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram", + 0x04, BIT(1), 0); +static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram", + 0x04, BIT(2), 0); +static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram", + 0x04, BIT(4), 0); +static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram", + 0x04, BIT(5), 0); +static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram", + 0x04, BIT(8), 0); +static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram", + 0x04, BIT(9), 0); +static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram", + 0x04, BIT(10), 0); +static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram", + 0x04, BIT(12), 0); +static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram", + 0x04, BIT(13), 0); + +static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de", + 0x08, BIT(0), 0); +static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de", + 0x08, BIT(1), 0); +static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de", + 0x08, BIT(2), 0); +static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de", + 0x08, BIT(4), 0); +static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de", + 0x08, BIT(5), 0); +static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de", + 0x08, BIT(8), 0); +static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de", + 0x08, BIT(9), 0); +static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de", + 0x08, BIT(10), 0); +static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de", + 0x08, BIT(12), 0); +static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de", + 0x08, BIT(13), 0); + +static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0); +static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0); +static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0); +static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0); +static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0); +static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0); + +static struct ccu_common *sun9i_a80_de_clks[] = { + &fe0_clk.common, + &fe1_clk.common, + &fe2_clk.common, + &iep_deu0_clk.common, + &iep_deu1_clk.common, + &be0_clk.common, + &be1_clk.common, + &be2_clk.common, + &iep_drc0_clk.common, + &iep_drc1_clk.common, + &merge_clk.common, + + &dram_fe0_clk.common, + &dram_fe1_clk.common, + &dram_fe2_clk.common, + &dram_deu0_clk.common, + &dram_deu1_clk.common, + &dram_be0_clk.common, + &dram_be1_clk.common, + &dram_be2_clk.common, + &dram_drc0_clk.common, + &dram_drc1_clk.common, + + &bus_fe0_clk.common, + &bus_fe1_clk.common, + &bus_fe2_clk.common, + &bus_deu0_clk.common, + &bus_deu1_clk.common, + &bus_be0_clk.common, + &bus_be1_clk.common, + &bus_be2_clk.common, + &bus_drc0_clk.common, + &bus_drc1_clk.common, + + &fe0_div_clk.common, + &fe1_div_clk.common, + &fe2_div_clk.common, + &be0_div_clk.common, + &be1_div_clk.common, + &be2_div_clk.common, +}; + +static struct clk_hw_onecell_data sun9i_a80_de_hw_clks = { + .hws = { + [CLK_FE0] = &fe0_clk.common.hw, + [CLK_FE1] = &fe1_clk.common.hw, + [CLK_FE2] = &fe2_clk.common.hw, + [CLK_IEP_DEU0] = &iep_deu0_clk.common.hw, + [CLK_IEP_DEU1] = &iep_deu1_clk.common.hw, + [CLK_BE0] = &be0_clk.common.hw, + [CLK_BE1] = &be1_clk.common.hw, + [CLK_BE2] = &be2_clk.common.hw, + [CLK_IEP_DRC0] = &iep_drc0_clk.common.hw, + [CLK_IEP_DRC1] = &iep_drc1_clk.common.hw, + [CLK_MERGE] = &merge_clk.common.hw, + + [CLK_DRAM_FE0] = &dram_fe0_clk.common.hw, + [CLK_DRAM_FE1] = &dram_fe1_clk.common.hw, + [CLK_DRAM_FE2] = &dram_fe2_clk.common.hw, + [CLK_DRAM_DEU0] = &dram_deu0_clk.common.hw, + [CLK_DRAM_DEU1] = &dram_deu1_clk.common.hw, + [CLK_DRAM_BE0] = &dram_be0_clk.common.hw, + [CLK_DRAM_BE1] = &dram_be1_clk.common.hw, + [CLK_DRAM_BE2] = &dram_be2_clk.common.hw, + [CLK_DRAM_DRC0] = &dram_drc0_clk.common.hw, + [CLK_DRAM_DRC1] = &dram_drc1_clk.common.hw, + + [CLK_BUS_FE0] = &bus_fe0_clk.common.hw, + [CLK_BUS_FE1] = &bus_fe1_clk.common.hw, + [CLK_BUS_FE2] = &bus_fe2_clk.common.hw, + [CLK_BUS_DEU0] = &bus_deu0_clk.common.hw, + [CLK_BUS_DEU1] = &bus_deu1_clk.common.hw, + [CLK_BUS_BE0] = &bus_be0_clk.common.hw, + [CLK_BUS_BE1] = &bus_be1_clk.common.hw, + [CLK_BUS_BE2] = &bus_be2_clk.common.hw, + [CLK_BUS_DRC0] = &bus_drc0_clk.common.hw, + [CLK_BUS_DRC1] = &bus_drc1_clk.common.hw, + + [CLK_FE0_DIV] = &fe0_div_clk.common.hw, + [CLK_FE1_DIV] = &fe1_div_clk.common.hw, + [CLK_FE2_DIV] = &fe2_div_clk.common.hw, + [CLK_BE0_DIV] = &be0_div_clk.common.hw, + [CLK_BE1_DIV] = &be1_div_clk.common.hw, + [CLK_BE2_DIV] = &be2_div_clk.common.hw, + }, + .num = CLK_NUMBER, +}; + +static struct ccu_reset_map sun9i_a80_de_resets[] = { + [RST_FE0] = { 0x0c, BIT(0) }, + [RST_FE1] = { 0x0c, BIT(1) }, + [RST_FE2] = { 0x0c, BIT(2) }, + [RST_DEU0] = { 0x0c, BIT(4) }, + [RST_DEU1] = { 0x0c, BIT(5) }, + [RST_BE0] = { 0x0c, BIT(8) }, + [RST_BE1] = { 0x0c, BIT(9) }, + [RST_BE2] = { 0x0c, BIT(10) }, + [RST_DRC0] = { 0x0c, BIT(12) }, + [RST_DRC1] = { 0x0c, BIT(13) }, + [RST_MERGE] = { 0x0c, BIT(20) }, +}; + +static const struct sunxi_ccu_desc sun9i_a80_de_clk_desc = { + .ccu_clks = sun9i_a80_de_clks, + .num_ccu_clks = ARRAY_SIZE(sun9i_a80_de_clks), + + .hw_clks = &sun9i_a80_de_hw_clks, + + .resets = sun9i_a80_de_resets, + .num_resets = ARRAY_SIZE(sun9i_a80_de_resets), +}; + +static int sun9i_a80_de_clk_probe(struct platform_device *pdev) +{ + struct resource *res; + struct clk *bus_clk; + struct reset_control *rstc; + void __iomem *reg; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + reg = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + bus_clk = devm_clk_get(&pdev->dev, "bus"); + if (IS_ERR(bus_clk)) { + ret = PTR_ERR(bus_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret); + return ret; + } + + rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(rstc)) { + ret = PTR_ERR(bus_clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, + "Couldn't get reset control: %d\n", ret); + return ret; + } + + /* The bus clock needs to be enabled for us to access the registers */ + ret = clk_prepare_enable(bus_clk); + if (ret) { + dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret); + return ret; + } + + /* The reset control needs to be asserted for the controls to work */ + ret = reset_control_deassert(rstc); + if (ret) { + dev_err(&pdev->dev, + "Couldn't deassert reset control: %d\n", ret); + goto err_disable_clk; + } + + ret = sunxi_ccu_probe(pdev->dev.of_node, reg, + &sun9i_a80_de_clk_desc); + if (ret) + goto err_assert_reset; + + return 0; + +err_assert_reset: + reset_control_assert(rstc); +err_disable_clk: + clk_disable_unprepare(bus_clk); + return ret; +} + +static const struct of_device_id sun9i_a80_de_clk_ids[] = { + { .compatible = "allwinner,sun9i-a80-de-clks" }, + { } +}; + +static struct platform_driver sun9i_a80_de_clk_driver = { + .probe = sun9i_a80_de_clk_probe, + .driver = { + .name = "sun9i-a80-de-clks", + .of_match_table = sun9i_a80_de_clk_ids, + }, +}; +builtin_platform_driver(sun9i_a80_de_clk_driver); diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h new file mode 100644 index 000000000000..a4769041e40f --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h @@ -0,0 +1,33 @@ +/* + * Copyright 2016 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CCU_SUN9I_A80_DE_H_ +#define _CCU_SUN9I_A80_DE_H_ + +#include <dt-bindings/clock/sun9i-a80-de.h> +#include <dt-bindings/reset/sun9i-a80-de.h> + +/* Intermediary clock dividers are not exported */ +#define CLK_FE0_DIV 31 +#define CLK_FE1_DIV 32 +#define CLK_FE2_DIV 33 +#define CLK_BE0_DIV 34 +#define CLK_BE1_DIV 35 +#define CLK_BE2_DIV 36 + +#define CLK_NUMBER (CLK_BE2_DIV + 1) + +#endif /* _CCU_SUN9I_A80_DE_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-de.h b/include/dt-bindings/clock/sun9i-a80-de.h new file mode 100644 index 000000000000..3dad6c3cd131 --- /dev/null +++ b/include/dt-bindings/clock/sun9i-a80-de.h @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ +#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ + +#define CLK_FE0 0 +#define CLK_FE1 1 +#define CLK_FE2 2 +#define CLK_IEP_DEU0 3 +#define CLK_IEP_DEU1 4 +#define CLK_BE0 5 +#define CLK_BE1 6 +#define CLK_BE2 7 +#define CLK_IEP_DRC0 8 +#define CLK_IEP_DRC1 9 +#define CLK_MERGE 10 + +#define CLK_DRAM_FE0 11 +#define CLK_DRAM_FE1 12 +#define CLK_DRAM_FE2 13 +#define CLK_DRAM_DEU0 14 +#define CLK_DRAM_DEU1 15 +#define CLK_DRAM_BE0 16 +#define CLK_DRAM_BE1 17 +#define CLK_DRAM_BE2 18 +#define CLK_DRAM_DRC0 19 +#define CLK_DRAM_DRC1 20 + +#define CLK_BUS_FE0 21 +#define CLK_BUS_FE1 22 +#define CLK_BUS_FE2 23 +#define CLK_BUS_DEU0 24 +#define CLK_BUS_DEU1 25 +#define CLK_BUS_BE0 26 +#define CLK_BUS_BE1 27 +#define CLK_BUS_BE2 28 +#define CLK_BUS_DRC0 29 +#define CLK_BUS_DRC1 30 + +#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */ diff --git a/include/dt-bindings/reset/sun9i-a80-de.h b/include/dt-bindings/reset/sun9i-a80-de.h new file mode 100644 index 000000000000..205072770171 --- /dev/null +++ b/include/dt-bindings/reset/sun9i-a80-de.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ +#define _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ + +#define RST_FE0 0 +#define RST_FE1 1 +#define RST_FE2 2 +#define RST_DEU0 3 +#define RST_DEU1 4 +#define RST_BE0 5 +#define RST_BE1 6 +#define RST_BE2 7 +#define RST_DRC0 8 +#define RST_DRC1 9 +#define RST_MERGE 10 + +#endif /* _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ */ -- 2.11.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU 2017-01-24 2:32 ` [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU Chen-Yu Tsai @ 2017-01-26 10:39 ` Maxime Ripard 2017-01-26 11:20 ` Chen-Yu Tsai 0 siblings, 1 reply; 33+ messages in thread From: Maxime Ripard @ 2017-01-26 10:39 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 7556 bytes --] Hi, On Tue, Jan 24, 2017 at 10:32:26AM +0800, Chen-Yu Tsai wrote: > Add support for the display engine clock controls found on the A80. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > .../devicetree/bindings/clock/sun9i-de.txt | 28 ++ > drivers/clk/sunxi-ng/Makefile | 1 + > drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 283 +++++++++++++++++++++ > drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h | 33 +++ > include/dt-bindings/clock/sun9i-a80-de.h | 80 ++++++ > include/dt-bindings/reset/sun9i-a80-de.h | 58 +++++ > 6 files changed, 483 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt > create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c > create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h > create mode 100644 include/dt-bindings/clock/sun9i-a80-de.h > create mode 100644 include/dt-bindings/reset/sun9i-a80-de.h > > diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt > new file mode 100644 > index 000000000000..3a5e6df70677 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/sun9i-de.txt > @@ -0,0 +1,28 @@ > +Allwinner A80 Display Engine Clock Control Binding > +------------------------------------ > + > +Required properties : > +- compatible: must contain one of the following compatibles: > + - "allwinner,sun9i-a80-de-clocks" > + > +- reg: Must contain the registers base address and length > +- clocks: phandle to the clocks feeding the display engine subsystem. > + Three are needed: > + - "mod": the display engine module clock > + - "dram": the DRAM bus clock for the system > + - "bus": the bus clock for the whole display engine subsystem > +- clock-names: Must contain the clock names described just above > +- resets: phandle to the reset control for the display engine subsystem. > +- #clock-cells : must contain 1 > +- #reset-cells : must contain 1 > + > +Example: > +de_clocks: clock@03000000 { > + compatible = "allwinner,sun9i-a80-de-clks"; > + reg = <0x03000000 0x30>; > + clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; > + clock-names = "mod", "dram", "bus"; > + resets = <&ccu RST_BUS_DE>; > + #clock-cells = <1>; > + #reset-cells = <1>; > +}; > diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile > index 8f37ef7fb67d..6feaac0c5600 100644 > --- a/drivers/clk/sunxi-ng/Makefile > +++ b/drivers/clk/sunxi-ng/Makefile > @@ -26,4 +26,5 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o > obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o > obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o > obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o > +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o > obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o > diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c > new file mode 100644 > index 000000000000..3fc27db0a49a > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c > @@ -0,0 +1,283 @@ > +/* > + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/clk-provider.h> > +#include <linux/of_address.h> > +#include <linux/platform_device.h> > +#include <linux/reset.h> > + > +#include "ccu_common.h" > +#include "ccu_div.h" > +#include "ccu_gate.h" > +#include "ccu_reset.h" > + > +#include "ccu-sun9i-a80-de.h" > + > +static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div", > + 0x00, BIT(0), 0); > +static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div", > + 0x00, BIT(1), 0); > +static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div", > + 0x00, BIT(2), 0); > +static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de", > + 0x00, BIT(4), 0); > +static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de", > + 0x00, BIT(5), 0); > +static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div", > + 0x00, BIT(8), 0); > +static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div", > + 0x00, BIT(9), 0); > +static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div", > + 0x00, BIT(10), 0); > +static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de", > + 0x00, BIT(12), 0); > +static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de", > + 0x00, BIT(13), 0); > +static SUNXI_CCU_GATE(merge_clk, "merge", "de", > + 0x00, BIT(20), 0); > + > +static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram", > + 0x04, BIT(0), 0); > +static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram", > + 0x04, BIT(1), 0); > +static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram", > + 0x04, BIT(2), 0); > +static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram", > + 0x04, BIT(4), 0); > +static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram", > + 0x04, BIT(5), 0); > +static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram", > + 0x04, BIT(8), 0); > +static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram", > + 0x04, BIT(9), 0); > +static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram", > + 0x04, BIT(10), 0); > +static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram", > + 0x04, BIT(12), 0); > +static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram", > + 0x04, BIT(13), 0); > + > +static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de", > + 0x08, BIT(0), 0); > +static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de", > + 0x08, BIT(1), 0); > +static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de", > + 0x08, BIT(2), 0); > +static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de", > + 0x08, BIT(4), 0); > +static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de", > + 0x08, BIT(5), 0); > +static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de", > + 0x08, BIT(8), 0); > +static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de", > + 0x08, BIT(9), 0); > +static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de", > + 0x08, BIT(10), 0); > +static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de", > + 0x08, BIT(12), 0); > +static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de", > + 0x08, BIT(13), 0); > + > +static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0); > +static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0); > +static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0); > +static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0); > +static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0); > +static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0); I couldn't find any documentation for this CCU. What are those clocks for, and how the display engine should be using (ie, which one is it expecting to drive / ungate / etc.) Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 801 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU 2017-01-26 10:39 ` Maxime Ripard @ 2017-01-26 11:20 ` Chen-Yu Tsai 2017-01-27 8:58 ` Maxime Ripard 0 siblings, 1 reply; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-26 11:20 UTC (permalink / raw) To: Maxime Ripard Cc: Chen-Yu Tsai, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi On Thu, Jan 26, 2017 at 6:39 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Hi, > > On Tue, Jan 24, 2017 at 10:32:26AM +0800, Chen-Yu Tsai wrote: >> Add support for the display engine clock controls found on the A80. >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> >> --- >> .../devicetree/bindings/clock/sun9i-de.txt | 28 ++ >> drivers/clk/sunxi-ng/Makefile | 1 + >> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 283 +++++++++++++++++++++ >> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h | 33 +++ >> include/dt-bindings/clock/sun9i-a80-de.h | 80 ++++++ >> include/dt-bindings/reset/sun9i-a80-de.h | 58 +++++ >> 6 files changed, 483 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h >> create mode 100644 include/dt-bindings/clock/sun9i-a80-de.h >> create mode 100644 include/dt-bindings/reset/sun9i-a80-de.h >> >> diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt >> new file mode 100644 >> index 000000000000..3a5e6df70677 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/sun9i-de.txt >> @@ -0,0 +1,28 @@ >> +Allwinner A80 Display Engine Clock Control Binding >> +------------------------------------ >> + >> +Required properties : >> +- compatible: must contain one of the following compatibles: >> + - "allwinner,sun9i-a80-de-clocks" >> + >> +- reg: Must contain the registers base address and length >> +- clocks: phandle to the clocks feeding the display engine subsystem. >> + Three are needed: >> + - "mod": the display engine module clock >> + - "dram": the DRAM bus clock for the system >> + - "bus": the bus clock for the whole display engine subsystem >> +- clock-names: Must contain the clock names described just above >> +- resets: phandle to the reset control for the display engine subsystem. >> +- #clock-cells : must contain 1 >> +- #reset-cells : must contain 1 >> + >> +Example: >> +de_clocks: clock@03000000 { >> + compatible = "allwinner,sun9i-a80-de-clks"; >> + reg = <0x03000000 0x30>; >> + clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; >> + clock-names = "mod", "dram", "bus"; >> + resets = <&ccu RST_BUS_DE>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> +}; >> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile >> index 8f37ef7fb67d..6feaac0c5600 100644 >> --- a/drivers/clk/sunxi-ng/Makefile >> +++ b/drivers/clk/sunxi-ng/Makefile >> @@ -26,4 +26,5 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o >> obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o >> obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o >> +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o >> diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c >> new file mode 100644 >> index 000000000000..3fc27db0a49a >> --- /dev/null >> +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c >> @@ -0,0 +1,283 @@ >> +/* >> + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. >> + * >> + * This software is licensed under the terms of the GNU General Public >> + * License version 2, as published by the Free Software Foundation, and >> + * may be copied, distributed, and modified under those terms. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + */ >> + >> +#include <linux/clk.h> >> +#include <linux/clk-provider.h> >> +#include <linux/of_address.h> >> +#include <linux/platform_device.h> >> +#include <linux/reset.h> >> + >> +#include "ccu_common.h" >> +#include "ccu_div.h" >> +#include "ccu_gate.h" >> +#include "ccu_reset.h" >> + >> +#include "ccu-sun9i-a80-de.h" >> + >> +static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div", >> + 0x00, BIT(0), 0); >> +static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div", >> + 0x00, BIT(1), 0); >> +static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div", >> + 0x00, BIT(2), 0); >> +static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de", >> + 0x00, BIT(4), 0); >> +static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de", >> + 0x00, BIT(5), 0); >> +static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div", >> + 0x00, BIT(8), 0); >> +static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div", >> + 0x00, BIT(9), 0); >> +static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div", >> + 0x00, BIT(10), 0); >> +static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de", >> + 0x00, BIT(12), 0); >> +static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de", >> + 0x00, BIT(13), 0); >> +static SUNXI_CCU_GATE(merge_clk, "merge", "de", >> + 0x00, BIT(20), 0); >> + >> +static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram", >> + 0x04, BIT(0), 0); >> +static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram", >> + 0x04, BIT(1), 0); >> +static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram", >> + 0x04, BIT(2), 0); >> +static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram", >> + 0x04, BIT(4), 0); >> +static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram", >> + 0x04, BIT(5), 0); >> +static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram", >> + 0x04, BIT(8), 0); >> +static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram", >> + 0x04, BIT(9), 0); >> +static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram", >> + 0x04, BIT(10), 0); >> +static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram", >> + 0x04, BIT(12), 0); >> +static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram", >> + 0x04, BIT(13), 0); >> + >> +static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de", >> + 0x08, BIT(0), 0); >> +static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de", >> + 0x08, BIT(1), 0); >> +static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de", >> + 0x08, BIT(2), 0); >> +static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de", >> + 0x08, BIT(4), 0); >> +static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de", >> + 0x08, BIT(5), 0); >> +static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de", >> + 0x08, BIT(8), 0); >> +static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de", >> + 0x08, BIT(9), 0); >> +static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de", >> + 0x08, BIT(10), 0); >> +static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de", >> + 0x08, BIT(12), 0); >> +static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de", >> + 0x08, BIT(13), 0); >> + >> +static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0); >> +static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0); >> +static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0); >> +static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0); >> +static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0); >> +static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0); > > I couldn't find any documentation for this CCU. I dug this up in the released Allwinner kernel. > What are those clocks for, and how the display engine should be using > (ie, which one is it expecting to drive / ungate / etc.) Allwinner basically put all DE-related clock controls into a separate module. In here, as the names above suggest, we have bus gates, dram gates, and module clocks for each part of the display pipeline. As with older SoCs that have DE 1.0, each module should ungate and use the clocks related to them. I'll put something like the above in the commit message. ChenYu > Thanks! > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU 2017-01-26 11:20 ` Chen-Yu Tsai @ 2017-01-27 8:58 ` Maxime Ripard 2017-01-27 9:26 ` Chen-Yu Tsai 0 siblings, 1 reply; 33+ messages in thread From: Maxime Ripard @ 2017-01-27 8:58 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 9481 bytes --] On Thu, Jan 26, 2017 at 07:20:22PM +0800, Chen-Yu Tsai wrote: > On Thu, Jan 26, 2017 at 6:39 PM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: > > Hi, > > > > On Tue, Jan 24, 2017 at 10:32:26AM +0800, Chen-Yu Tsai wrote: > >> Add support for the display engine clock controls found on the A80. > >> > >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> > >> --- > >> .../devicetree/bindings/clock/sun9i-de.txt | 28 ++ > >> drivers/clk/sunxi-ng/Makefile | 1 + > >> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 283 +++++++++++++++++++++ > >> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h | 33 +++ > >> include/dt-bindings/clock/sun9i-a80-de.h | 80 ++++++ > >> include/dt-bindings/reset/sun9i-a80-de.h | 58 +++++ > >> 6 files changed, 483 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt > >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c > >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h > >> create mode 100644 include/dt-bindings/clock/sun9i-a80-de.h > >> create mode 100644 include/dt-bindings/reset/sun9i-a80-de.h > >> > >> diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt > >> new file mode 100644 > >> index 000000000000..3a5e6df70677 > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/clock/sun9i-de.txt > >> @@ -0,0 +1,28 @@ > >> +Allwinner A80 Display Engine Clock Control Binding > >> +------------------------------------ > >> + > >> +Required properties : > >> +- compatible: must contain one of the following compatibles: > >> + - "allwinner,sun9i-a80-de-clocks" > >> + > >> +- reg: Must contain the registers base address and length > >> +- clocks: phandle to the clocks feeding the display engine subsystem. > >> + Three are needed: > >> + - "mod": the display engine module clock > >> + - "dram": the DRAM bus clock for the system > >> + - "bus": the bus clock for the whole display engine subsystem > >> +- clock-names: Must contain the clock names described just above > >> +- resets: phandle to the reset control for the display engine subsystem. > >> +- #clock-cells : must contain 1 > >> +- #reset-cells : must contain 1 > >> + > >> +Example: > >> +de_clocks: clock@03000000 { > >> + compatible = "allwinner,sun9i-a80-de-clks"; > >> + reg = <0x03000000 0x30>; > >> + clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; > >> + clock-names = "mod", "dram", "bus"; > >> + resets = <&ccu RST_BUS_DE>; > >> + #clock-cells = <1>; > >> + #reset-cells = <1>; > >> +}; > >> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile > >> index 8f37ef7fb67d..6feaac0c5600 100644 > >> --- a/drivers/clk/sunxi-ng/Makefile > >> +++ b/drivers/clk/sunxi-ng/Makefile > >> @@ -26,4 +26,5 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o > >> obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o > >> obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o > >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o > >> +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o > >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o > >> diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c > >> new file mode 100644 > >> index 000000000000..3fc27db0a49a > >> --- /dev/null > >> +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c > >> @@ -0,0 +1,283 @@ > >> +/* > >> + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. > >> + * > >> + * This software is licensed under the terms of the GNU General Public > >> + * License version 2, as published by the Free Software Foundation, and > >> + * may be copied, distributed, and modified under those terms. > >> + * > >> + * This program is distributed in the hope that it will be useful, > >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of > >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > >> + * GNU General Public License for more details. > >> + */ > >> + > >> +#include <linux/clk.h> > >> +#include <linux/clk-provider.h> > >> +#include <linux/of_address.h> > >> +#include <linux/platform_device.h> > >> +#include <linux/reset.h> > >> + > >> +#include "ccu_common.h" > >> +#include "ccu_div.h" > >> +#include "ccu_gate.h" > >> +#include "ccu_reset.h" > >> + > >> +#include "ccu-sun9i-a80-de.h" > >> + > >> +static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div", > >> + 0x00, BIT(0), 0); > >> +static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div", > >> + 0x00, BIT(1), 0); > >> +static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div", > >> + 0x00, BIT(2), 0); > >> +static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de", > >> + 0x00, BIT(4), 0); > >> +static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de", > >> + 0x00, BIT(5), 0); > >> +static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div", > >> + 0x00, BIT(8), 0); > >> +static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div", > >> + 0x00, BIT(9), 0); > >> +static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div", > >> + 0x00, BIT(10), 0); > >> +static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de", > >> + 0x00, BIT(12), 0); > >> +static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de", > >> + 0x00, BIT(13), 0); > >> +static SUNXI_CCU_GATE(merge_clk, "merge", "de", > >> + 0x00, BIT(20), 0); > >> + > >> +static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram", > >> + 0x04, BIT(0), 0); > >> +static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram", > >> + 0x04, BIT(1), 0); > >> +static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram", > >> + 0x04, BIT(2), 0); > >> +static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram", > >> + 0x04, BIT(4), 0); > >> +static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram", > >> + 0x04, BIT(5), 0); > >> +static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram", > >> + 0x04, BIT(8), 0); > >> +static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram", > >> + 0x04, BIT(9), 0); > >> +static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram", > >> + 0x04, BIT(10), 0); > >> +static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram", > >> + 0x04, BIT(12), 0); > >> +static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram", > >> + 0x04, BIT(13), 0); > >> + > >> +static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de", > >> + 0x08, BIT(0), 0); > >> +static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de", > >> + 0x08, BIT(1), 0); > >> +static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de", > >> + 0x08, BIT(2), 0); > >> +static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de", > >> + 0x08, BIT(4), 0); > >> +static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de", > >> + 0x08, BIT(5), 0); > >> +static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de", > >> + 0x08, BIT(8), 0); > >> +static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de", > >> + 0x08, BIT(9), 0); > >> +static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de", > >> + 0x08, BIT(10), 0); > >> +static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de", > >> + 0x08, BIT(12), 0); > >> +static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de", > >> + 0x08, BIT(13), 0); > >> + > >> +static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0); > >> +static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0); > >> +static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0); > >> +static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0); > >> +static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0); > >> +static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0); > > > > I couldn't find any documentation for this CCU. > > I dug this up in the released Allwinner kernel. > > > What are those clocks for, and how the display engine should be using > > (ie, which one is it expecting to drive / ungate / etc.) > > Allwinner basically put all DE-related clock controls into a > separate module. In here, as the names above suggest, we have > bus gates, dram gates, and module clocks for each part of the > display pipeline. As with older SoCs that have DE 1.0, each > module should ungate and use the clocks related to them. > > I'll put something like the above in the commit message. So the module clocks are a combination of a divider and a clock? And I'm guessing the reason you separated them is because they belong in a different register. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 801 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU 2017-01-27 8:58 ` Maxime Ripard @ 2017-01-27 9:26 ` Chen-Yu Tsai 2017-01-27 9:42 ` Maxime Ripard 0 siblings, 1 reply; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-27 9:26 UTC (permalink / raw) To: Maxime Ripard Cc: Chen-Yu Tsai, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi On Fri, Jan 27, 2017 at 4:58 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > On Thu, Jan 26, 2017 at 07:20:22PM +0800, Chen-Yu Tsai wrote: >> On Thu, Jan 26, 2017 at 6:39 PM, Maxime Ripard >> <maxime.ripard@free-electrons.com> wrote: >> > Hi, >> > >> > On Tue, Jan 24, 2017 at 10:32:26AM +0800, Chen-Yu Tsai wrote: >> >> Add support for the display engine clock controls found on the A80. >> >> >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> >> >> --- >> >> .../devicetree/bindings/clock/sun9i-de.txt | 28 ++ >> >> drivers/clk/sunxi-ng/Makefile | 1 + >> >> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 283 +++++++++++++++++++++ >> >> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h | 33 +++ >> >> include/dt-bindings/clock/sun9i-a80-de.h | 80 ++++++ >> >> include/dt-bindings/reset/sun9i-a80-de.h | 58 +++++ >> >> 6 files changed, 483 insertions(+) >> >> create mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt >> >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c >> >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h >> >> create mode 100644 include/dt-bindings/clock/sun9i-a80-de.h >> >> create mode 100644 include/dt-bindings/reset/sun9i-a80-de.h >> >> >> >> diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt >> >> new file mode 100644 >> >> index 000000000000..3a5e6df70677 >> >> --- /dev/null >> >> +++ b/Documentation/devicetree/bindings/clock/sun9i-de.txt >> >> @@ -0,0 +1,28 @@ >> >> +Allwinner A80 Display Engine Clock Control Binding >> >> +------------------------------------ >> >> + >> >> +Required properties : >> >> +- compatible: must contain one of the following compatibles: >> >> + - "allwinner,sun9i-a80-de-clocks" >> >> + >> >> +- reg: Must contain the registers base address and length >> >> +- clocks: phandle to the clocks feeding the display engine subsystem. >> >> + Three are needed: >> >> + - "mod": the display engine module clock >> >> + - "dram": the DRAM bus clock for the system >> >> + - "bus": the bus clock for the whole display engine subsystem >> >> +- clock-names: Must contain the clock names described just above >> >> +- resets: phandle to the reset control for the display engine subsystem. >> >> +- #clock-cells : must contain 1 >> >> +- #reset-cells : must contain 1 >> >> + >> >> +Example: >> >> +de_clocks: clock@03000000 { >> >> + compatible = "allwinner,sun9i-a80-de-clks"; >> >> + reg = <0x03000000 0x30>; >> >> + clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; >> >> + clock-names = "mod", "dram", "bus"; >> >> + resets = <&ccu RST_BUS_DE>; >> >> + #clock-cells = <1>; >> >> + #reset-cells = <1>; >> >> +}; >> >> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile >> >> index 8f37ef7fb67d..6feaac0c5600 100644 >> >> --- a/drivers/clk/sunxi-ng/Makefile >> >> +++ b/drivers/clk/sunxi-ng/Makefile >> >> @@ -26,4 +26,5 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o >> >> obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o >> >> obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o >> >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o >> >> +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o >> >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o >> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c >> >> new file mode 100644 >> >> index 000000000000..3fc27db0a49a >> >> --- /dev/null >> >> +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c >> >> @@ -0,0 +1,283 @@ >> >> +/* >> >> + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. >> >> + * >> >> + * This software is licensed under the terms of the GNU General Public >> >> + * License version 2, as published by the Free Software Foundation, and >> >> + * may be copied, distributed, and modified under those terms. >> >> + * >> >> + * This program is distributed in the hope that it will be useful, >> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> >> + * GNU General Public License for more details. >> >> + */ >> >> + >> >> +#include <linux/clk.h> >> >> +#include <linux/clk-provider.h> >> >> +#include <linux/of_address.h> >> >> +#include <linux/platform_device.h> >> >> +#include <linux/reset.h> >> >> + >> >> +#include "ccu_common.h" >> >> +#include "ccu_div.h" >> >> +#include "ccu_gate.h" >> >> +#include "ccu_reset.h" >> >> + >> >> +#include "ccu-sun9i-a80-de.h" >> >> + >> >> +static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div", >> >> + 0x00, BIT(0), 0); >> >> +static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div", >> >> + 0x00, BIT(1), 0); >> >> +static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div", >> >> + 0x00, BIT(2), 0); >> >> +static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de", >> >> + 0x00, BIT(4), 0); >> >> +static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de", >> >> + 0x00, BIT(5), 0); >> >> +static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div", >> >> + 0x00, BIT(8), 0); >> >> +static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div", >> >> + 0x00, BIT(9), 0); >> >> +static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div", >> >> + 0x00, BIT(10), 0); >> >> +static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de", >> >> + 0x00, BIT(12), 0); >> >> +static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de", >> >> + 0x00, BIT(13), 0); >> >> +static SUNXI_CCU_GATE(merge_clk, "merge", "de", >> >> + 0x00, BIT(20), 0); >> >> + >> >> +static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram", >> >> + 0x04, BIT(0), 0); >> >> +static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram", >> >> + 0x04, BIT(1), 0); >> >> +static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram", >> >> + 0x04, BIT(2), 0); >> >> +static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram", >> >> + 0x04, BIT(4), 0); >> >> +static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram", >> >> + 0x04, BIT(5), 0); >> >> +static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram", >> >> + 0x04, BIT(8), 0); >> >> +static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram", >> >> + 0x04, BIT(9), 0); >> >> +static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram", >> >> + 0x04, BIT(10), 0); >> >> +static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram", >> >> + 0x04, BIT(12), 0); >> >> +static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram", >> >> + 0x04, BIT(13), 0); >> >> + >> >> +static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de", >> >> + 0x08, BIT(0), 0); >> >> +static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de", >> >> + 0x08, BIT(1), 0); >> >> +static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de", >> >> + 0x08, BIT(2), 0); >> >> +static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de", >> >> + 0x08, BIT(4), 0); >> >> +static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de", >> >> + 0x08, BIT(5), 0); >> >> +static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de", >> >> + 0x08, BIT(8), 0); >> >> +static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de", >> >> + 0x08, BIT(9), 0); >> >> +static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de", >> >> + 0x08, BIT(10), 0); >> >> +static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de", >> >> + 0x08, BIT(12), 0); >> >> +static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de", >> >> + 0x08, BIT(13), 0); >> >> + >> >> +static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0); >> >> +static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0); >> >> +static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0); >> >> +static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0); >> >> +static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0); >> >> +static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0); >> > >> > I couldn't find any documentation for this CCU. >> >> I dug this up in the released Allwinner kernel. >> >> > What are those clocks for, and how the display engine should be using >> > (ie, which one is it expecting to drive / ungate / etc.) >> >> Allwinner basically put all DE-related clock controls into a >> separate module. In here, as the names above suggest, we have >> bus gates, dram gates, and module clocks for each part of the >> display pipeline. As with older SoCs that have DE 1.0, each >> module should ungate and use the clocks related to them. >> >> I'll put something like the above in the commit message. > > So the module clocks are a combination of a divider and a clock? Correct. Some have dividers, some don't. > And I'm guessing the reason you separated them is because they belong > in a different register. Correct. Trying to support them within one clock would be a big deviation from what sunxi-ng currently supports. I left the divider clocks at the end of the list, and aren't exported to dt either. So if we really want to get rid of those intermediate divider clocks, we can do so later without affecting the exposed interface. Regards ChenYu > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU 2017-01-27 9:26 ` Chen-Yu Tsai @ 2017-01-27 9:42 ` Maxime Ripard 0 siblings, 0 replies; 33+ messages in thread From: Maxime Ripard @ 2017-01-27 9:42 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 10633 bytes --] On Fri, Jan 27, 2017 at 05:26:53PM +0800, Chen-Yu Tsai wrote: > On Fri, Jan 27, 2017 at 4:58 PM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: > > On Thu, Jan 26, 2017 at 07:20:22PM +0800, Chen-Yu Tsai wrote: > >> On Thu, Jan 26, 2017 at 6:39 PM, Maxime Ripard > >> <maxime.ripard@free-electrons.com> wrote: > >> > Hi, > >> > > >> > On Tue, Jan 24, 2017 at 10:32:26AM +0800, Chen-Yu Tsai wrote: > >> >> Add support for the display engine clock controls found on the A80. > >> >> > >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> > >> >> --- > >> >> .../devicetree/bindings/clock/sun9i-de.txt | 28 ++ > >> >> drivers/clk/sunxi-ng/Makefile | 1 + > >> >> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c | 283 +++++++++++++++++++++ > >> >> drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h | 33 +++ > >> >> include/dt-bindings/clock/sun9i-a80-de.h | 80 ++++++ > >> >> include/dt-bindings/reset/sun9i-a80-de.h | 58 +++++ > >> >> 6 files changed, 483 insertions(+) > >> >> create mode 100644 Documentation/devicetree/bindings/clock/sun9i-de.txt > >> >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c > >> >> create mode 100644 drivers/clk/sunxi-ng/ccu-sun9i-a80-de.h > >> >> create mode 100644 include/dt-bindings/clock/sun9i-a80-de.h > >> >> create mode 100644 include/dt-bindings/reset/sun9i-a80-de.h > >> >> > >> >> diff --git a/Documentation/devicetree/bindings/clock/sun9i-de.txt b/Documentation/devicetree/bindings/clock/sun9i-de.txt > >> >> new file mode 100644 > >> >> index 000000000000..3a5e6df70677 > >> >> --- /dev/null > >> >> +++ b/Documentation/devicetree/bindings/clock/sun9i-de.txt > >> >> @@ -0,0 +1,28 @@ > >> >> +Allwinner A80 Display Engine Clock Control Binding > >> >> +------------------------------------ > >> >> + > >> >> +Required properties : > >> >> +- compatible: must contain one of the following compatibles: > >> >> + - "allwinner,sun9i-a80-de-clocks" > >> >> + > >> >> +- reg: Must contain the registers base address and length > >> >> +- clocks: phandle to the clocks feeding the display engine subsystem. > >> >> + Three are needed: > >> >> + - "mod": the display engine module clock > >> >> + - "dram": the DRAM bus clock for the system > >> >> + - "bus": the bus clock for the whole display engine subsystem > >> >> +- clock-names: Must contain the clock names described just above > >> >> +- resets: phandle to the reset control for the display engine subsystem. > >> >> +- #clock-cells : must contain 1 > >> >> +- #reset-cells : must contain 1 > >> >> + > >> >> +Example: > >> >> +de_clocks: clock@03000000 { > >> >> + compatible = "allwinner,sun9i-a80-de-clks"; > >> >> + reg = <0x03000000 0x30>; > >> >> + clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>; > >> >> + clock-names = "mod", "dram", "bus"; > >> >> + resets = <&ccu RST_BUS_DE>; > >> >> + #clock-cells = <1>; > >> >> + #reset-cells = <1>; > >> >> +}; > >> >> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile > >> >> index 8f37ef7fb67d..6feaac0c5600 100644 > >> >> --- a/drivers/clk/sunxi-ng/Makefile > >> >> +++ b/drivers/clk/sunxi-ng/Makefile > >> >> @@ -26,4 +26,5 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o > >> >> obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o > >> >> obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o > >> >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o > >> >> +obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o > >> >> obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o > >> >> diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c > >> >> new file mode 100644 > >> >> index 000000000000..3fc27db0a49a > >> >> --- /dev/null > >> >> +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c > >> >> @@ -0,0 +1,283 @@ > >> >> +/* > >> >> + * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved. > >> >> + * > >> >> + * This software is licensed under the terms of the GNU General Public > >> >> + * License version 2, as published by the Free Software Foundation, and > >> >> + * may be copied, distributed, and modified under those terms. > >> >> + * > >> >> + * This program is distributed in the hope that it will be useful, > >> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of > >> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > >> >> + * GNU General Public License for more details. > >> >> + */ > >> >> + > >> >> +#include <linux/clk.h> > >> >> +#include <linux/clk-provider.h> > >> >> +#include <linux/of_address.h> > >> >> +#include <linux/platform_device.h> > >> >> +#include <linux/reset.h> > >> >> + > >> >> +#include "ccu_common.h" > >> >> +#include "ccu_div.h" > >> >> +#include "ccu_gate.h" > >> >> +#include "ccu_reset.h" > >> >> + > >> >> +#include "ccu-sun9i-a80-de.h" > >> >> + > >> >> +static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div", > >> >> + 0x00, BIT(0), 0); > >> >> +static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div", > >> >> + 0x00, BIT(1), 0); > >> >> +static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div", > >> >> + 0x00, BIT(2), 0); > >> >> +static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de", > >> >> + 0x00, BIT(4), 0); > >> >> +static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de", > >> >> + 0x00, BIT(5), 0); > >> >> +static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div", > >> >> + 0x00, BIT(8), 0); > >> >> +static SUNXI_CCU_GATE(be1_clk, "be1", "be1-div", > >> >> + 0x00, BIT(9), 0); > >> >> +static SUNXI_CCU_GATE(be2_clk, "be2", "be2-div", > >> >> + 0x00, BIT(10), 0); > >> >> +static SUNXI_CCU_GATE(iep_drc0_clk, "iep-drc0", "de", > >> >> + 0x00, BIT(12), 0); > >> >> +static SUNXI_CCU_GATE(iep_drc1_clk, "iep-drc1", "de", > >> >> + 0x00, BIT(13), 0); > >> >> +static SUNXI_CCU_GATE(merge_clk, "merge", "de", > >> >> + 0x00, BIT(20), 0); > >> >> + > >> >> +static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram", > >> >> + 0x04, BIT(0), 0); > >> >> +static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram", > >> >> + 0x04, BIT(1), 0); > >> >> +static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram", > >> >> + 0x04, BIT(2), 0); > >> >> +static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram", > >> >> + 0x04, BIT(4), 0); > >> >> +static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram", > >> >> + 0x04, BIT(5), 0); > >> >> +static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram", > >> >> + 0x04, BIT(8), 0); > >> >> +static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram", > >> >> + 0x04, BIT(9), 0); > >> >> +static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram", > >> >> + 0x04, BIT(10), 0); > >> >> +static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram", > >> >> + 0x04, BIT(12), 0); > >> >> +static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram", > >> >> + 0x04, BIT(13), 0); > >> >> + > >> >> +static SUNXI_CCU_GATE(bus_fe0_clk, "bus-fe0", "bus-de", > >> >> + 0x08, BIT(0), 0); > >> >> +static SUNXI_CCU_GATE(bus_fe1_clk, "bus-fe1", "bus-de", > >> >> + 0x08, BIT(1), 0); > >> >> +static SUNXI_CCU_GATE(bus_fe2_clk, "bus-fe2", "bus-de", > >> >> + 0x08, BIT(2), 0); > >> >> +static SUNXI_CCU_GATE(bus_deu0_clk, "bus-deu0", "bus-de", > >> >> + 0x08, BIT(4), 0); > >> >> +static SUNXI_CCU_GATE(bus_deu1_clk, "bus-deu1", "bus-de", > >> >> + 0x08, BIT(5), 0); > >> >> +static SUNXI_CCU_GATE(bus_be0_clk, "bus-be0", "bus-de", > >> >> + 0x08, BIT(8), 0); > >> >> +static SUNXI_CCU_GATE(bus_be1_clk, "bus-be1", "bus-de", > >> >> + 0x08, BIT(9), 0); > >> >> +static SUNXI_CCU_GATE(bus_be2_clk, "bus-be2", "bus-de", > >> >> + 0x08, BIT(10), 0); > >> >> +static SUNXI_CCU_GATE(bus_drc0_clk, "bus-drc0", "bus-de", > >> >> + 0x08, BIT(12), 0); > >> >> +static SUNXI_CCU_GATE(bus_drc1_clk, "bus-drc1", "bus-de", > >> >> + 0x08, BIT(13), 0); > >> >> + > >> >> +static SUNXI_CCU_M(fe0_div_clk, "fe0-div", "de", 0x20, 0, 4, 0); > >> >> +static SUNXI_CCU_M(fe1_div_clk, "fe1-div", "de", 0x20, 4, 4, 0); > >> >> +static SUNXI_CCU_M(fe2_div_clk, "fe2-div", "de", 0x20, 8, 4, 0); > >> >> +static SUNXI_CCU_M(be0_div_clk, "be0-div", "de", 0x20, 16, 4, 0); > >> >> +static SUNXI_CCU_M(be1_div_clk, "be1-div", "de", 0x20, 20, 4, 0); > >> >> +static SUNXI_CCU_M(be2_div_clk, "be2-div", "de", 0x20, 24, 4, 0); > >> > > >> > I couldn't find any documentation for this CCU. > >> > >> I dug this up in the released Allwinner kernel. > >> > >> > What are those clocks for, and how the display engine should be using > >> > (ie, which one is it expecting to drive / ungate / etc.) > >> > >> Allwinner basically put all DE-related clock controls into a > >> separate module. In here, as the names above suggest, we have > >> bus gates, dram gates, and module clocks for each part of the > >> display pipeline. As with older SoCs that have DE 1.0, each > >> module should ungate and use the clocks related to them. > >> > >> I'll put something like the above in the commit message. > > > > So the module clocks are a combination of a divider and a clock? > > Correct. Some have dividers, some don't. > > > And I'm guessing the reason you separated them is because they belong > > in a different register. > > Correct. Trying to support them within one clock would be a big > deviation from what sunxi-ng currently supports. I left the > divider clocks at the end of the list, and aren't exported to > dt either. So if we really want to get rid of those intermediate > divider clocks, we can do so later without affecting the exposed > interface. That works for me, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 801 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 08/11] ARM: dts: sun8i-a23-q8-tablet: Drop pinmux setting for codec PA gpio 2017-01-24 2:32 [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai ` (6 preceding siblings ...) 2017-01-24 2:32 ` [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU Chen-Yu Tsai @ 2017-01-24 2:32 ` Chen-Yu Tsai 2017-01-26 10:38 ` Maxime Ripard 2017-01-24 2:32 ` [PATCH 09/11] ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h header Chen-Yu Tsai ` (3 subsequent siblings) 11 siblings, 1 reply; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-24 2:32 UTC (permalink / raw) To: Maxime Ripard, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd Cc: Chen-Yu Tsai, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi We are moving towards handling GPIO pinmux settings that don't require extra bias or drive strength settings to use the GPIO bindings only. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- arch/arm/boot/dts/sun8i-a23-q8-tablet.dts | 10 ---------- drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 24 ++++++++++++------------ 2 files changed, 12 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts index 3ab5c0c09d93..b6958e8f2f01 100644 --- a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts +++ b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts @@ -50,7 +50,6 @@ }; &codec { - pinctrl-0 = <&codec_pa_pin>; allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ allwinner,audio-routing = "Headphone", "HP", @@ -62,12 +61,3 @@ "Headset Mic", "HBIAS"; status = "okay"; }; - -&pio { - codec_pa_pin: codec_pa_pin@0 { - allwinner,pins = "PH9"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; -}; diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c index 5626e4674f48..e13e313ce4f5 100644 --- a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c @@ -42,7 +42,7 @@ static struct clk_div_table pll_cpux_p_div_table[] = { static struct ccu_nm pll_c0cpux_clk = { .enable = BIT(31), .lock = BIT(0), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV_TABLE(16, 1, pll_cpux_p_div_table), .common = { .reg = 0x000, @@ -56,7 +56,7 @@ static struct ccu_nm pll_c0cpux_clk = { static struct ccu_nm pll_c1cpux_clk = { .enable = BIT(31), .lock = BIT(1), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV_TABLE(16, 1, pll_cpux_p_div_table), .common = { .reg = 0x004, @@ -78,7 +78,7 @@ static struct ccu_nm pll_c1cpux_clk = { static struct ccu_nm pll_audio_clk = { .enable = BIT(31), .lock = BIT(2), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV_OFFSET(0, 6, 0), .common = { .reg = 0x008, @@ -93,7 +93,7 @@ static struct ccu_nm pll_audio_clk = { static struct ccu_nkmp pll_periph0_clk = { .enable = BIT(31), .lock = BIT(3), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ .common = { @@ -109,7 +109,7 @@ static struct ccu_nkmp pll_periph0_clk = { static struct ccu_nkmp pll_ve_clk = { .enable = BIT(31), .lock = BIT(4), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ .common = { @@ -125,7 +125,7 @@ static struct ccu_nkmp pll_ve_clk = { static struct ccu_nkmp pll_ddr_clk = { .enable = BIT(31), .lock = BIT(5), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ .common = { @@ -141,7 +141,7 @@ static struct ccu_nkmp pll_ddr_clk = { static struct ccu_nm pll_video0_clk = { .enable = BIT(31), .lock = BIT(6), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .common = { .reg = 0x018, @@ -156,7 +156,7 @@ static struct ccu_nm pll_video0_clk = { static struct ccu_nkmp pll_video1_clk = { .enable = BIT(31), .lock = BIT(7), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(0, 2), /* external divider p */ .common = { @@ -172,7 +172,7 @@ static struct ccu_nkmp pll_video1_clk = { static struct ccu_nkmp pll_gpu_clk = { .enable = BIT(31), .lock = BIT(8), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ .common = { @@ -188,7 +188,7 @@ static struct ccu_nkmp pll_gpu_clk = { static struct ccu_nkmp pll_de_clk = { .enable = BIT(31), .lock = BIT(9), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ .common = { @@ -204,7 +204,7 @@ static struct ccu_nkmp pll_de_clk = { static struct ccu_nkmp pll_isp_clk = { .enable = BIT(31), .lock = BIT(10), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ .common = { @@ -220,7 +220,7 @@ static struct ccu_nkmp pll_isp_clk = { static struct ccu_nkmp pll_periph1_clk = { .enable = BIT(31), .lock = BIT(11), - .n = _SUNXI_CCU_MULT_OFFSET_MIN(8, 8, 0, 12), + .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ .common = { -- 2.11.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH 08/11] ARM: dts: sun8i-a23-q8-tablet: Drop pinmux setting for codec PA gpio 2017-01-24 2:32 ` [PATCH 08/11] ARM: dts: sun8i-a23-q8-tablet: Drop pinmux setting for codec PA gpio Chen-Yu Tsai @ 2017-01-26 10:38 ` Maxime Ripard 2017-01-26 11:15 ` Chen-Yu Tsai 0 siblings, 1 reply; 33+ messages in thread From: Maxime Ripard @ 2017-01-26 10:38 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 651 bytes --] On Tue, Jan 24, 2017 at 10:32:27AM +0800, Chen-Yu Tsai wrote: > We are moving towards handling GPIO pinmux settings that don't require > extra bias or drive strength settings to use the GPIO bindings only. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > arch/arm/boot/dts/sun8i-a23-q8-tablet.dts | 10 ---------- > drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 24 ++++++++++++------------ That diff looks suspicious :) (and the patch for which you wrote a commit log for doesn't have anything to do in this serie) Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 801 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 08/11] ARM: dts: sun8i-a23-q8-tablet: Drop pinmux setting for codec PA gpio 2017-01-26 10:38 ` Maxime Ripard @ 2017-01-26 11:15 ` Chen-Yu Tsai 0 siblings, 0 replies; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-26 11:15 UTC (permalink / raw) To: Maxime Ripard Cc: Chen-Yu Tsai, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi On Thu, Jan 26, 2017 at 6:38 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > On Tue, Jan 24, 2017 at 10:32:27AM +0800, Chen-Yu Tsai wrote: >> We are moving towards handling GPIO pinmux settings that don't require >> extra bias or drive strength settings to use the GPIO bindings only. >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> >> --- >> arch/arm/boot/dts/sun8i-a23-q8-tablet.dts | 10 ---------- >> drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 24 ++++++++++++------------ > > That diff looks suspicious :) Squashed in a fix against your updated sun5i CCU patches into the wrong one. :/ > (and the patch for which you wrote a commit log for > doesn't have anything to do in this serie) Correct. This is a prerequisite to the pinctrl header removal patch you just merged. This patch removes the last in-tree usage of macros from said header file. ChenYu > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 09/11] ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h header 2017-01-24 2:32 [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai ` (7 preceding siblings ...) 2017-01-24 2:32 ` [PATCH 08/11] ARM: dts: sun8i-a23-q8-tablet: Drop pinmux setting for codec PA gpio Chen-Yu Tsai @ 2017-01-24 2:32 ` Chen-Yu Tsai 2017-01-26 10:21 ` Maxime Ripard 2017-01-24 2:32 ` [PATCH 10/11] arm64: dts: allwinner: " Chen-Yu Tsai ` (2 subsequent siblings) 11 siblings, 1 reply; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-24 2:32 UTC (permalink / raw) To: Maxime Ripard, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd Cc: Chen-Yu Tsai, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi All dts files for the sunxi platform have been switched to the generic pinconf bindings. As a result, the sunxi specific pinctrl macros are no longer used. Remove the #include entry with the following command: sed -i -e '/pinctrl\/sun4i-a10.h/D' arch/arm/boot/dts/sun?i*.* Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- arch/arm/boot/dts/sun4i-a10-a1000.dts | 1 - arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 1 - arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 1 - arch/arm/boot/dts/sun4i-a10-hackberry.dts | 1 - arch/arm/boot/dts/sun4i-a10-inet1.dts | 1 - arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 1 - arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts | 1 - arch/arm/boot/dts/sun4i-a10-marsboard.dts | 1 - arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 1 - arch/arm/boot/dts/sun4i-a10-mk802.dts | 1 - arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 1 - arch/arm/boot/dts/sun4i-a10-pcduino.dts | 1 - arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 1 - arch/arm/boot/dts/sun4i-a10.dtsi | 1 - arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts | 1 - arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts | 1 - arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 1 - arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts | 1 - arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts | 1 - arch/arm/boot/dts/sun5i-a10s.dtsi | 1 - arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts | 1 - arch/arm/boot/dts/sun5i-a13-hsg-h702.dts | 1 - arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 1 - arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 1 - arch/arm/boot/dts/sun5i-a13.dtsi | 1 - arch/arm/boot/dts/sun5i-gr8.dtsi | 1 - arch/arm/boot/dts/sun5i.dtsi | 1 - arch/arm/boot/dts/sun6i-a31-app4-evb1.dts | 1 - arch/arm/boot/dts/sun6i-a31-colombus.dts | 1 - arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 1 - arch/arm/boot/dts/sun6i-a31-i7.dts | 1 - arch/arm/boot/dts/sun6i-a31-m9.dts | 1 - arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 1 - arch/arm/boot/dts/sun6i-a31.dtsi | 1 - arch/arm/boot/dts/sun6i-a31s-cs908.dts | 2 -- arch/arm/boot/dts/sun6i-a31s-primo81.dts | 1 - arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 1 - arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts | 1 - arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi | 1 - arch/arm/boot/dts/sun7i-a20-bananapi.dts | 1 - arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 1 - arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 1 - arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 1 - arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 1 - arch/arm/boot/dts/sun7i-a20-icnova-swac.dts | 1 - arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 1 - arch/arm/boot/dts/sun7i-a20-m3.dts | 1 - arch/arm/boot/dts/sun7i-a20-mk808c.dts | 1 - arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 1 - arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 1 - arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 1 - arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 1 - arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts | 1 - arch/arm/boot/dts/sun7i-a20-orangepi.dts | 1 - arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 1 - arch/arm/boot/dts/sun7i-a20.dtsi | 1 - arch/arm/boot/dts/sun8i-a23-a33.dtsi | 1 - arch/arm/boot/dts/sun8i-a23-evb.dts | 1 - arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 1 - arch/arm/boot/dts/sun8i-a83t.dtsi | 2 -- arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 1 - arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 1 - arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 1 - arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 1 - arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 1 - arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 1 - arch/arm/boot/dts/sun8i-h3.dtsi | 1 - arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 1 - arch/arm/boot/dts/sun9i-a80-optimus.dts | 1 - arch/arm/boot/dts/sun9i-a80.dtsi | 2 -- arch/arm/boot/dts/sunxi-common-regulators.dtsi | 1 - arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi | 1 - 72 files changed, 75 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index f3fc27412a67..f2a01fe2bebc 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -47,7 +47,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Mele A1000"; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 04e040e6233d..d844938e2aa7 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -46,7 +46,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Cubietech Cubieboard"; diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts index 8317fbfeec4a..aad3bec1cb39 100644 --- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts +++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/pwm/pwm.h> / { diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index a48b46474417..a1a7282199d5 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -47,7 +47,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Miniand Hackberry"; diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts index f3092703a1a6..b8923b92cb36 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet1.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/pwm/pwm.h> / { diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts index 4ef2a60a8cd4..4a27eb9102cd 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "iNet-9F Rev 03"; diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts index fc4d4d49e2e2..308dc1513041 100644 --- a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts +++ b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts @@ -47,7 +47,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Jesurun Q5"; diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts index a2885039d5f1..98a5f7258dca 100644 --- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts @@ -46,7 +46,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "HAOYU Electronics Marsboard A10"; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index af42ebb3a97b..484c57493bd2 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -47,7 +47,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "PineRiver Mini X-Plus"; diff --git a/arch/arm/boot/dts/sun4i-a10-mk802.dts b/arch/arm/boot/dts/sun4i-a10-mk802.dts index 9c1afd4277d7..2b75745cd246 100644 --- a/arch/arm/boot/dts/sun4i-a10-mk802.dts +++ b/arch/arm/boot/dts/sun4i-a10-mk802.dts @@ -44,7 +44,6 @@ #include "sun4i-a10.dtsi" #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "MK802"; diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index 214a5accfe93..3a2522a9419d 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A10-OLinuXino-LIME"; diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index b0365d63ba70..83596fd2ccfc 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -47,7 +47,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "LinkSprite pcDuino"; diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts index bfa6bbdaab27..a68c7cc53b94 100644 --- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/pwm/pwm.h> / { diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index ba20b48c0702..7dc4230da0c0 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -47,7 +47,6 @@ #include <dt-bindings/clock/sun4i-a10-pll2.h> #include <dt-bindings/dma/sun4i-a10.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts index a539b72ce093..c6f742a7e69f 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts @@ -44,7 +44,6 @@ #include "sun5i-a10s.dtsi" #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Auxtek t003 A10s hdmi tv-stick"; diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts index e1b5e8a446fe..a27c3fa58736 100644 --- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts +++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts @@ -44,7 +44,6 @@ #include "sun5i-a10s.dtsi" #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Auxtek t004 A10s hdmi tv-stick"; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index d8245c6314a7..9f19423ad135 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A10s-Olinuxino Micro"; diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts index 51371f9b1cf0..262b3669f04d 100644 --- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts +++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "R7 A10s hdmi tv-stick"; diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts index 2b8adda0deda..10b4e6122c9d 100644 --- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts +++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "A10s-Wobo i5"; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 24b0f5f556f8..74671f7e9c9b 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -47,7 +47,6 @@ #include "sun5i.dtsi" #include <dt-bindings/dma/sun4i-a10.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { interrupt-parent = <&intc>; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts index 42435454acef..34411d27aadf 100644 --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/pwm/pwm.h> / { diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts index 5879a75cf97a..2489c16f7efa 100644 --- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts +++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "HSG H702"; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index 60e393e28783..3a831eaf1dfc 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -46,7 +46,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A13-Olinuxino Micro"; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 940d47e88056..95f591bb8ced 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A13-Olinuxino"; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index fb2ddb9a04c9..d723e9e9e776 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -46,7 +46,6 @@ #include "sun5i.dtsi" -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/thermal/thermal.h> / { diff --git a/arch/arm/boot/dts/sun5i-gr8.dtsi b/arch/arm/boot/dts/sun5i-gr8.dtsi index cb9b2aaf7297..29e3c924c3a5 100644 --- a/arch/arm/boot/dts/sun5i-gr8.dtsi +++ b/arch/arm/boot/dts/sun5i-gr8.dtsi @@ -44,7 +44,6 @@ #include <dt-bindings/clock/sun5i-ccu.h> #include <dt-bindings/dma/sun4i-a10.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/reset/sun5i-ccu.h> / { diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index a9574a6cd95c..f7927d972405 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -46,7 +46,6 @@ #include <dt-bindings/clock/sun5i-ccu.h> #include <dt-bindings/dma/sun4i-a10.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/reset/sun5i-ccu.h> / { diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts index effbdc766938..7f34323a668c 100644 --- a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts +++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts @@ -47,7 +47,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Allwinner A31 APP4 EVB1 Evaluation Board"; diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index f5ececd45bc0..85eff0307ca4 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts @@ -47,7 +47,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "WITS A31 Colombus Evaluation Board"; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index f094eeb6c499..d4f74f476f25 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -47,7 +47,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Merrii A31 Hummingbird"; diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts b/arch/arm/boot/dts/sun6i-a31-i7.dts index 3354e4df06e9..d9a03004c40f 100644 --- a/arch/arm/boot/dts/sun6i-a31-i7.dts +++ b/arch/arm/boot/dts/sun6i-a31-i7.dts @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Mele I7 Quad top set box"; diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts index 8af5b667a46d..50605fd4449e 100644 --- a/arch/arm/boot/dts/sun6i-a31-m9.dts +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Mele M9 top set box"; diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts index bf0f5831126f..5219556e9f73 100644 --- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts +++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Mele A1000G Quad top set box"; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index ee1eb6de355f..9618b6ae1905 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -48,7 +48,6 @@ #include <dt-bindings/thermal/thermal.h> #include <dt-bindings/clock/sun6i-a31-ccu.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/reset/sun6i-a31-ccu.h> / { diff --git a/arch/arm/boot/dts/sun6i-a31s-cs908.dts b/arch/arm/boot/dts/sun6i-a31s-cs908.dts index 5e8f8c4f2b30..75e578159c3a 100644 --- a/arch/arm/boot/dts/sun6i-a31s-cs908.dts +++ b/arch/arm/boot/dts/sun6i-a31s-cs908.dts @@ -43,8 +43,6 @@ /dts-v1/; #include "sun6i-a31s.dtsi" -#include <dt-bindings/pinctrl/sun4i-a10.h> - / { model = "CSQ CS908 top set box"; compatible = "csq,cs908", "allwinner,sun6i-a31s"; diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts index 2238eda318f6..f3712753fa42 100644 --- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "MSI Primo81 tablet"; diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi index 4ec0c8679b2e..d7325bc4eeb4 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Sinlinx SinA31s Core Board"; diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts index 154ebf5082ed..f3edf9ca435c 100644 --- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts +++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Yones TopTech BS1078 v2 Tablet"; diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi index edaba5f904fd..3cc4046b904a 100644 --- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi @@ -44,7 +44,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { aliases { diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts index 91f2e5f9efcb..ed2f35adf542 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "LeMaker Banana Pi"; diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 4dc1e10f88c4..a2eab7aa80e0 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Cubietech Cubieboard2"; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index f019aa3fe96d..feb995d29799 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Cubietech Cubietruck"; diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts index e921ba42f170..99c00b9a1546 100644 --- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts +++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Merrii A20 Hummingbird"; diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index 385fd8232ae0..4da49717da21 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "I12 / Q5 / QT840A A20 tvbox"; diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts index f5b5325a70e2..28d3abbdc2d4 100644 --- a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts +++ b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "ICnova-A20 SWAC"; diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts index 72ec0d5ae052..072c4e8610ec 100644 --- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts +++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Lamobo R1"; diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts index 0e074bd0e8c9..86f69813683e 100644 --- a/arch/arm/boot/dts/sun7i-a20-m3.dts +++ b/arch/arm/boot/dts/sun7i-a20-m3.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Mele M3"; diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/sun7i-a20-mk808c.dts index 97d7a8b65a03..c4ee30709f3a 100644 --- a/arch/arm/boot/dts/sun7i-a20-mk808c.dts +++ b/arch/arm/boot/dts/sun7i-a20-mk808c.dts @@ -53,7 +53,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "mk808c"; diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts index a1450c10b08e..1af5b46862cb 100644 --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A20-Olimex-SOM-EVB"; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts index 1297432c2802..dcd0f7a0dffa 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -49,7 +49,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A20-OLinuXino-LIME"; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts index 71cca5360728..e7d45425758c 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A20-OLinuXino-LIME2"; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index 223fbd9f7c62..499f8328050c 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -49,7 +49,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Olimex A20-Olinuxino Micro"; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts index a74265749227..7af4c8fc1865 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Orange Pi Mini"; diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts index 3de980c8f8ff..0a8d4a05e8a0 100644 --- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts +++ b/arch/arm/boot/dts/sun7i-a20-orangepi.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Orange Pi"; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index 4599f98a3aee..7c96b53b76bf 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "LinkSprite pcDuino3"; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 04c997735c32..827e71392ece 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -49,7 +49,6 @@ #include <dt-bindings/clock/sun4i-a10-pll2.h> #include <dt-bindings/dma/sun4i-a10.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 597f2fce6c31..6d47a5fe018d 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -47,7 +47,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> / { diff --git a/arch/arm/boot/dts/sun8i-a23-evb.dts b/arch/arm/boot/dts/sun8i-a23-evb.dts index c21f5b1b255e..87289a60c520 100644 --- a/arch/arm/boot/dts/sun8i-a23-evb.dts +++ b/arch/arm/boot/dts/sun8i-a23-evb.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Allwinner A23 Evaluation Board"; diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index b75162075ca1..4858df5ee00d 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -48,7 +48,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Sinlinx SinA33"; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 79eaa7139f43..c3c556eaaf26 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -47,8 +47,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> - / { interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts index c0c49dd4d3b2..52acbe111cad 100644 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Banana Pi BPI-M2-Plus"; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi index 2216e68d1838..c6decee41a27 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi +++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi @@ -47,7 +47,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { aliases { diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index 047e9e1c6093..5b6d14555b7c 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Xunlong Orange Pi 2"; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts index 22b99b407019..9b47a0def740 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Xunlong Orange Pi Lite"; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index 34da853ee037..ea8fd1325356 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Xunlong Orange Pi One"; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index d43978d3294e..f148111c326d 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -46,7 +46,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Xunlong Orange Pi PC"; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 08fd0860bb6b..11e046c1e4b3 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -44,7 +44,6 @@ #include <dt-bindings/clock/sun8i-h3-ccu.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/reset/sun8i-h3-ccu.h> / { diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 9112a200fd5e..3741ac71c3d6 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -47,7 +47,6 @@ #include "sun9i-a80.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Cubietech Cubieboard4"; diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 0fc3a87f5576..85f1ad670310 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -46,7 +46,6 @@ #include "sun9i-a80.dtsi" #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> / { model = "Merrii A80 Optimus Board"; diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 7231d2c90dde..18b35fc23f46 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -46,8 +46,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> - / { interrupt-parent = <&gic>; diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi index 17c09fed9e84..ce5c53e4452f 100644 --- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi +++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi @@ -43,7 +43,6 @@ */ #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> &pio { ahci_pwr_pin_a: ahci_pwr_pin@0 { diff --git a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi index b8241462fcea..245d0bcde441 100644 --- a/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi @@ -42,7 +42,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include "sunxi-common-regulators.dtsi" &i2c0 { -- 2.11.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH 09/11] ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h header 2017-01-24 2:32 ` [PATCH 09/11] ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h header Chen-Yu Tsai @ 2017-01-26 10:21 ` Maxime Ripard 0 siblings, 0 replies; 33+ messages in thread From: Maxime Ripard @ 2017-01-26 10:21 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 547 bytes --] On Tue, Jan 24, 2017 at 10:32:28AM +0800, Chen-Yu Tsai wrote: > All dts files for the sunxi platform have been switched to the generic > pinconf bindings. As a result, the sunxi specific pinctrl macros are > no longer used. > > Remove the #include entry with the following command: > > sed -i -e '/pinctrl\/sun4i-a10.h/D' arch/arm/boot/dts/sun?i*.* > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Applied, thanks Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 801 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 10/11] arm64: dts: allwinner: Remove no longer used pinctrl/sun4i-a10.h header 2017-01-24 2:32 [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai ` (8 preceding siblings ...) 2017-01-24 2:32 ` [PATCH 09/11] ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h header Chen-Yu Tsai @ 2017-01-24 2:32 ` Chen-Yu Tsai 2017-01-26 10:15 ` Maxime Ripard 2017-01-24 2:32 ` [PATCH 11/11] ARM: dts: sun9i: Switch to new clock bindings Chen-Yu Tsai 2017-01-24 6:03 ` [linux-sunxi] [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Priit Laes 11 siblings, 1 reply; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-24 2:32 UTC (permalink / raw) To: Maxime Ripard, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd Cc: Chen-Yu Tsai, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi All dts files for the sunxi platform have been switched to the generic pinconf bindings. As a result, the sunxi specific pinctrl macros are no longer used. Remove the #include entry with the following command: sed -i -e '/pinctrl\/sun4i-a10.h/D' \ arch/arm64/boot/dts/allwinner/*.dts? Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 99b6bb1e141c..6ec831177b22 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -44,7 +44,6 @@ #include <dt-bindings/clock/sun50i-a64-ccu.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/reset/sun50i-a64-ccu.h> / { -- 2.11.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH 10/11] arm64: dts: allwinner: Remove no longer used pinctrl/sun4i-a10.h header 2017-01-24 2:32 ` [PATCH 10/11] arm64: dts: allwinner: " Chen-Yu Tsai @ 2017-01-26 10:15 ` Maxime Ripard 2017-01-26 11:23 ` Chen-Yu Tsai 0 siblings, 1 reply; 33+ messages in thread From: Maxime Ripard @ 2017-01-26 10:15 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 616 bytes --] On Tue, Jan 24, 2017 at 10:32:29AM +0800, Chen-Yu Tsai wrote: > All dts files for the sunxi platform have been switched to the generic > pinconf bindings. As a result, the sunxi specific pinctrl macros are > no longer used. > > Remove the #include entry with the following command: > > sed -i -e '/pinctrl\/sun4i-a10.h/D' \ > arch/arm64/boot/dts/allwinner/*.dts? > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Applied, thanks! Maybe we should also remove the header entirely? Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 801 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 10/11] arm64: dts: allwinner: Remove no longer used pinctrl/sun4i-a10.h header 2017-01-26 10:15 ` Maxime Ripard @ 2017-01-26 11:23 ` Chen-Yu Tsai 2017-01-27 8:46 ` Maxime Ripard 0 siblings, 1 reply; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-26 11:23 UTC (permalink / raw) To: Maxime Ripard Cc: Chen-Yu Tsai, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi On Thu, Jan 26, 2017 at 6:15 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > On Tue, Jan 24, 2017 at 10:32:29AM +0800, Chen-Yu Tsai wrote: >> All dts files for the sunxi platform have been switched to the generic >> pinconf bindings. As a result, the sunxi specific pinctrl macros are >> no longer used. >> >> Remove the #include entry with the following command: >> >> sed -i -e '/pinctrl\/sun4i-a10.h/D' \ >> arch/arm64/boot/dts/allwinner/*.dts? >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> > > Applied, thanks! > > Maybe we should also remove the header entirely? I don't know. What do we do about deprecated bindings? ChenYu ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 10/11] arm64: dts: allwinner: Remove no longer used pinctrl/sun4i-a10.h header 2017-01-26 11:23 ` Chen-Yu Tsai @ 2017-01-27 8:46 ` Maxime Ripard 0 siblings, 0 replies; 33+ messages in thread From: Maxime Ripard @ 2017-01-27 8:46 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi [-- Attachment #1: Type: text/plain, Size: 1008 bytes --] On Thu, Jan 26, 2017 at 07:23:25PM +0800, Chen-Yu Tsai wrote: > On Thu, Jan 26, 2017 at 6:15 PM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: > > On Tue, Jan 24, 2017 at 10:32:29AM +0800, Chen-Yu Tsai wrote: > >> All dts files for the sunxi platform have been switched to the generic > >> pinconf bindings. As a result, the sunxi specific pinctrl macros are > >> no longer used. > >> > >> Remove the #include entry with the following command: > >> > >> sed -i -e '/pinctrl\/sun4i-a10.h/D' \ > >> arch/arm64/boot/dts/allwinner/*.dts? > >> > >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> > > > > Applied, thanks! > > > > Maybe we should also remove the header entirely? > > I don't know. What do we do about deprecated bindings? Well, we have to support the old device trees, but I don't think to be expected to still compile them from the source Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 801 bytes --] ^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 11/11] ARM: dts: sun9i: Switch to new clock bindings 2017-01-24 2:32 [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai ` (9 preceding siblings ...) 2017-01-24 2:32 ` [PATCH 10/11] arm64: dts: allwinner: " Chen-Yu Tsai @ 2017-01-24 2:32 ` Chen-Yu Tsai 2017-01-24 6:03 ` [linux-sunxi] [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Priit Laes 11 siblings, 0 replies; 33+ messages in thread From: Chen-Yu Tsai @ 2017-01-24 2:32 UTC (permalink / raw) To: Maxime Ripard, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd Cc: Chen-Yu Tsai, linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi Now that we have a full clock driver for sun9i, switch to it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- arch/arm/boot/dts/sun9i-a80.dtsi | 404 +++++++++++---------------------------- 1 file changed, 107 insertions(+), 297 deletions(-) diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 18b35fc23f46..b763c61cacba 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -46,6 +46,13 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun9i-a80-ccu.h> +#include <dt-bindings/clock/sun9i-a80-de.h> +#include <dt-bindings/clock/sun9i-a80-usb.h> +#include <dt-bindings/reset/sun9i-a80-ccu.h> +#include <dt-bindings/reset/sun9i-a80-de.h> +#include <dt-bindings/reset/sun9i-a80-usb.h> + / { interrupt-parent = <&gic>; @@ -157,228 +164,13 @@ clock-output-names = "osc32k"; }; - usb_mod_clk: clk@00a08000 { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun9i-a80-usb-mod-clk"; - reg = <0x00a08000 0x4>; - clocks = <&ahb1_gates 1>; - clock-output-names = "usb0_ahb", "usb_ohci0", - "usb1_ahb", "usb_ohci1", - "usb2_ahb", "usb_ohci2"; - }; - - usb_phy_clk: clk@00a08004 { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun9i-a80-usb-phy-clk"; - reg = <0x00a08004 0x4>; - clocks = <&ahb1_gates 1>; - clock-output-names = "usb_phy0", "usb_hsic1_480M", - "usb_phy1", "usb_hsic2_480M", - "usb_phy2", "usb_hsic_12M"; - }; - - pll3: clk@06000008 { - /* placeholder until implemented */ - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-rate = <0>; - clock-output-names = "pll3"; - }; - - pll4: clk@0600000c { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-pll4-clk"; - reg = <0x0600000c 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll4"; - }; - - pll12: clk@0600002c { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-pll4-clk"; - reg = <0x0600002c 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll12"; - }; - - gt_clk: clk@0600005c { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-gt-clk"; - reg = <0x0600005c 0x4>; - clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>; - clock-output-names = "gt"; - }; - - ahb0: clk@06000060 { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-ahb-clk"; - reg = <0x06000060 0x4>; - clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; - clock-output-names = "ahb0"; - }; - - ahb1: clk@06000064 { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-ahb-clk"; - reg = <0x06000064 0x4>; - clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; - clock-output-names = "ahb1"; - }; - - ahb2: clk@06000068 { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-ahb-clk"; - reg = <0x06000068 0x4>; - clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; - clock-output-names = "ahb2"; - }; - - apb0: clk@06000070 { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-apb0-clk"; - reg = <0x06000070 0x4>; - clocks = <&osc24M>, <&pll4>; - clock-output-names = "apb0"; - }; - - apb1: clk@06000074 { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-apb1-clk"; - reg = <0x06000074 0x4>; - clocks = <&osc24M>, <&pll4>; - clock-output-names = "apb1"; - }; - - cci400_clk: clk@06000078 { - #clock-cells = <0>; - compatible = "allwinner,sun9i-a80-gt-clk"; - reg = <0x06000078 0x4>; - clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>; - clock-output-names = "cci400"; - }; - - mmc0_clk: clk@06000410 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-mmc-clk"; - reg = <0x06000410 0x4>; - clocks = <&osc24M>, <&pll4>; - clock-output-names = "mmc0", "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@06000414 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-mmc-clk"; - reg = <0x06000414 0x4>; - clocks = <&osc24M>, <&pll4>; - clock-output-names = "mmc1", "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@06000418 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-mmc-clk"; - reg = <0x06000418 0x4>; - clocks = <&osc24M>, <&pll4>; - clock-output-names = "mmc2", "mmc2_output", - "mmc2_sample"; - }; - - mmc3_clk: clk@0600041c { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-mmc-clk"; - reg = <0x0600041c 0x4>; - clocks = <&osc24M>, <&pll4>; - clock-output-names = "mmc3", "mmc3_output", - "mmc3_sample"; - }; - - ahb0_gates: clk@06000580 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-ahb0-gates-clk"; - reg = <0x06000580 0x4>; - clocks = <&ahb0>; - clock-indices = <0>, <1>, <3>, - <5>, <8>, <12>, - <13>, <14>, - <15>, <16>, <18>, - <20>, <21>, <22>, - <23>; - clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu", - "ahb0_ss", "ahb0_sd", "ahb0_nand1", - "ahb0_nand0", "ahb0_sdram", - "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts", - "ahb0_spi0", "ahb0_spi1", "ahb0_spi2", - "ahb0_spi3"; - }; - - ahb1_gates: clk@06000584 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-ahb1-gates-clk"; - reg = <0x06000584 0x4>; - clocks = <&ahb1>; - clock-indices = <0>, <1>, - <17>, <21>, - <22>, <23>, - <24>; - clock-output-names = "ahb1_usbotg", "ahb1_usbhci", - "ahb1_gmac", "ahb1_msgbox", - "ahb1_spinlock", "ahb1_hstimer", - "ahb1_dma"; - }; - - ahb2_gates: clk@06000588 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-ahb2-gates-clk"; - reg = <0x06000588 0x4>; - clocks = <&ahb2>; - clock-indices = <0>, <1>, - <2>, <4>, <5>, - <7>, <8>, <11>; - clock-output-names = "ahb2_lcd0", "ahb2_lcd1", - "ahb2_edp", "ahb2_csi", "ahb2_hdmi", - "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi"; - }; - - apb0_gates: clk@06000590 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-apb0-gates-clk"; - reg = <0x06000590 0x4>; - clocks = <&apb0>; - clock-indices = <1>, <5>, - <11>, <12>, <13>, - <15>, <17>, <18>, - <19>; - clock-output-names = "apb0_spdif", "apb0_pio", - "apb0_ac97", "apb0_i2s0", "apb0_i2s1", - "apb0_lradc", "apb0_gpadc", "apb0_twd", - "apb0_cirtx"; - }; - - apb1_gates: clk@06000594 { - #clock-cells = <1>; - compatible = "allwinner,sun9i-a80-apb1-gates-clk"; - reg = <0x06000594 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <1>, - <2>, <3>, <4>, - <16>, <17>, - <18>, <19>, - <20>, <21>; - clock-output-names = "apb1_i2c0", "apb1_i2c1", - "apb1_i2c2", "apb1_i2c3", "apb1_i2c4", - "apb1_uart0", "apb1_uart1", - "apb1_uart2", "apb1_uart3", - "apb1_uart4", "apb1_uart5"; - }; - cpus_clk: clk@08001410 { compatible = "allwinner,sun9i-a80-cpus-clk"; reg = <0x08001410 0x4>; #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>; + clocks = <&osc32k>, <&osc24M>, + <&ccu CLK_PLL_PERIPH0>, + <&ccu CLK_PLL_AUDIO>; clock-output-names = "cpus"; }; @@ -451,8 +243,8 @@ compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; reg = <0x00a00000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_mod_clk 1>; - resets = <&usb_mod_clk 17>; + clocks = <&usb_clocks CLK_BUS_HCI0>; + resets = <&usb_clocks RST_USB0_HCI>; phys = <&usbphy1>; phy-names = "usb"; status = "disabled"; @@ -462,8 +254,9 @@ compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; reg = <0x00a00400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>; - resets = <&usb_mod_clk 17>; + clocks = <&usb_clocks CLK_BUS_HCI0>, + <&usb_clocks CLK_USB_OHCI0>; + resets = <&usb_clocks RST_USB0_HCI>; phys = <&usbphy1>; phy-names = "usb"; status = "disabled"; @@ -472,9 +265,9 @@ usbphy1: phy@00a00800 { compatible = "allwinner,sun9i-a80-usb-phy"; reg = <0x00a00800 0x4>; - clocks = <&usb_phy_clk 1>; + clocks = <&usb_clocks CLK_USB0_PHY>; clock-names = "phy"; - resets = <&usb_phy_clk 17>; + resets = <&usb_clocks RST_USB0_PHY>; reset-names = "phy"; status = "disabled"; #phy-cells = <0>; @@ -484,8 +277,8 @@ compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; reg = <0x00a01000 0x100>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_mod_clk 3>; - resets = <&usb_mod_clk 18>; + clocks = <&usb_clocks CLK_BUS_HCI1>; + resets = <&usb_clocks RST_USB1_HCI>; phys = <&usbphy2>; phy-names = "usb"; status = "disabled"; @@ -494,11 +287,16 @@ usbphy2: phy@00a01800 { compatible = "allwinner,sun9i-a80-usb-phy"; reg = <0x00a01800 0x4>; - clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>, - <&usb_phy_clk 3>; - clock-names = "hsic_480M", "hsic_12M", "phy"; - resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>; - reset-names = "hsic", "phy"; + clocks = <&usb_clocks CLK_USB1_HSIC>, + <&usb_clocks CLK_USB_HSIC>, + <&usb_clocks CLK_USB1_PHY>; + clock-names = "hsic_480M", + "hsic_12M", + "phy"; + resets = <&usb_clocks RST_USB1_HSIC>, + <&usb_clocks RST_USB1_PHY>; + reset-names = "hsic", + "phy"; status = "disabled"; #phy-cells = <0>; /* usb1 is always used with HSIC */ @@ -509,8 +307,8 @@ compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; reg = <0x00a02000 0x100>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_mod_clk 5>; - resets = <&usb_mod_clk 19>; + clocks = <&usb_clocks CLK_BUS_HCI2>; + resets = <&usb_clocks RST_USB2_HCI>; phys = <&usbphy3>; phy-names = "usb"; status = "disabled"; @@ -520,8 +318,9 @@ compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; reg = <0x00a02400 0x100>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>; - resets = <&usb_mod_clk 19>; + clocks = <&usb_clocks CLK_BUS_HCI2>, + <&usb_clocks CLK_USB_OHCI2>; + resets = <&usb_clocks RST_USB2_HCI>; phys = <&usbphy3>; phy-names = "usb"; status = "disabled"; @@ -530,20 +329,35 @@ usbphy3: phy@00a02800 { compatible = "allwinner,sun9i-a80-usb-phy"; reg = <0x00a02800 0x4>; - clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>, - <&usb_phy_clk 5>; - clock-names = "hsic_480M", "hsic_12M", "phy"; - resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>; - reset-names = "hsic", "phy"; + clocks = <&usb_clocks CLK_USB2_HSIC>, + <&usb_clocks CLK_USB_HSIC>, + <&usb_clocks CLK_USB2_PHY>; + clock-names = "hsic_480M", + "hsic_12M", + "phy"; + resets = <&usb_clocks RST_USB2_HSIC>, + <&usb_clocks RST_USB2_PHY>; + reset-names = "hsic", + "phy"; status = "disabled"; #phy-cells = <0>; }; + usb_clocks: clock@00a08000 { + compatible = "allwinner,sun9i-a80-usb-clks"; + reg = <0x00a08000 0x8>; + clocks = <&ccu CLK_BUS_USB>, <&osc24M>; + clock-names = "bus", "hosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + mmc0: mmc@01c0f000 { compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>, - <&mmc0_clk 1>, <&mmc0_clk 2>; + clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; resets = <&mmc_config_clk 0>; reset-names = "ahb"; @@ -556,8 +370,9 @@ mmc1: mmc@01c10000 { compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>, - <&mmc1_clk 1>, <&mmc1_clk 2>; + clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; resets = <&mmc_config_clk 1>; reset-names = "ahb"; @@ -570,8 +385,9 @@ mmc2: mmc@01c11000 { compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>, - <&mmc2_clk 1>, <&mmc2_clk 2>; + clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; resets = <&mmc_config_clk 2>; reset-names = "ahb"; @@ -584,8 +400,9 @@ mmc3: mmc@01c12000 { compatible = "allwinner,sun9i-a80-mmc"; reg = <0x01c12000 0x1000>; - clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>, - <&mmc3_clk 1>, <&mmc3_clk 2>; + clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>, + <&ccu CLK_MMC3_OUTPUT>, + <&ccu CLK_MMC3_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; resets = <&mmc_config_clk 3>; reset-names = "ahb"; @@ -598,9 +415,9 @@ mmc_config_clk: clk@01c13000 { compatible = "allwinner,sun9i-a80-mmc-config-clk"; reg = <0x01c13000 0x10>; - clocks = <&ahb0_gates 8>; + clocks = <&ccu CLK_BUS_MMC>; clock-names = "ahb"; - resets = <&ahb0_resets 8>; + resets = <&ccu RST_BUS_MMC>; reset-names = "ahb"; #clock-cells = <1>; #reset-cells = <1>; @@ -619,34 +436,27 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; - ahb0_resets: reset@060005a0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x060005a0 0x4>; - }; - - ahb1_resets: reset@060005a4 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x060005a4 0x4>; - }; - - ahb2_resets: reset@060005a8 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x060005a8 0x4>; - }; - - apb0_resets: reset@060005b0 { + de_clocks: clock@03000000 { + compatible = "allwinner,sun9i-a80-de-clks"; + reg = <0x03000000 0x30>; + clocks = <&ccu CLK_DE>, + <&ccu CLK_SDRAM>, + <&ccu CLK_BUS_DE>; + clock-names = "mod", + "dram", + "bus"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x060005b0 0x4>; }; - apb1_resets: reset@060005b4 { + ccu: clock@06000000 { + compatible = "allwinner,sun9i-a80-ccu"; + reg = <0x06000000 0x800>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x060005b4 0x4>; }; timer@06000c00 { @@ -676,7 +486,7 @@ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -732,8 +542,8 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 16>; - resets = <&apb1_resets 16>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -743,8 +553,8 @@ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 17>; - resets = <&apb1_resets 17>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -754,8 +564,8 @@ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 18>; - resets = <&apb1_resets 18>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; status = "disabled"; }; @@ -765,8 +575,8 @@ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 19>; - resets = <&apb1_resets 19>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; status = "disabled"; }; @@ -776,8 +586,8 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 20>; - resets = <&apb1_resets 20>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; status = "disabled"; }; @@ -787,8 +597,8 @@ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb1_gates 21>; - resets = <&apb1_resets 21>; + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; status = "disabled"; }; @@ -796,8 +606,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07002800 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 0>; - resets = <&apb1_resets 0>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -807,8 +617,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07002c00 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 1>; - resets = <&apb1_resets 1>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -818,8 +628,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07003000 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 2>; - resets = <&apb1_resets 2>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -829,8 +639,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07003400 0x400>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 3>; - resets = <&apb1_resets 3>; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -840,8 +650,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x07003800 0x400>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb1_gates 4>; - resets = <&apb1_resets 4>; + clocks = <&ccu CLK_BUS_I2C4>; + resets = <&ccu RST_BUS_I2C4>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; -- 2.11.0 ^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [linux-sunxi] [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs 2017-01-24 2:32 [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai ` (10 preceding siblings ...) 2017-01-24 2:32 ` [PATCH 11/11] ARM: dts: sun9i: Switch to new clock bindings Chen-Yu Tsai @ 2017-01-24 6:03 ` Priit Laes 11 siblings, 0 replies; 33+ messages in thread From: Priit Laes @ 2017-01-24 6:03 UTC (permalink / raw) To: wens, Maxime Ripard, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd Cc: linux-clk, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi On Tue, 2017-01-24 at 10:32 +0800, Chen-Yu Tsai wrote: > Hi everyone, Hi! Thanks for working on that! You might want to bump the copyright year starting from patch 5.=20 [...] P=C3=A4ikest, Priit Laes ^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU @ 2017-01-24 6:50 Icenowy Zheng 0 siblings, 0 replies; 33+ messages in thread From: Icenowy Zheng @ 2017-01-24 6:50 UTC (permalink / raw) To: Chen-Yu Tsai Cc: Michael Turquette, Mark Rutland, Rob Herring, linux-clk, linux-kernel, devicetree, Stephen Boyd, Maxime Ripard, linux-arm-kernel, linux-sunxi CjIwMTflubQx5pyIMjTml6UgMTA6MzLkuo4gQ2hlbi1ZdSBUc2FpIDx3ZW5zQGNzaWUub3JnPuWG memBk++8mgo+Cj4gQWRkIHN1cHBvcnQgZm9yIHRoZSBkaXNwbGF5IGVuZ2luZSBjbG9jayBjb250 cm9scyBmb3VuZCBvbiB0aGUgQTgwLiAKPgo+IFNpZ25lZC1vZmYtYnk6IENoZW4tWXUgVHNhaSA8 d2Vuc0Bjc2llLm9yZz4gCj4gLS0tIAo+IC4uLi9kZXZpY2V0cmVlL2JpbmRpbmdzL2Nsb2NrL3N1 bjlpLWRlLnR4dMKgwqDCoMKgwqDCoMKgwqAgfMKgIDI4ICsrIAo+IGRyaXZlcnMvY2xrL3N1bnhp LW5nL01ha2VmaWxlwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgIHzC oMKgIDEgKyAKPiBkcml2ZXJzL2Nsay9zdW54aS1uZy9jY3Utc3VuOWktYTgwLWRlLmPCoMKgwqDC oMKgwqDCoMKgwqDCoMKgIHwgMjgzICsrKysrKysrKysrKysrKysrKysrKyAKPiBkcml2ZXJzL2Ns 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end of thread, other threads:[~2017-01-27 21:15 UTC | newest] Thread overview: 33+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-01-24 2:32 [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai 2017-01-24 2:32 ` [PATCH 01/11] clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers Chen-Yu Tsai 2017-01-26 9:55 ` Maxime Ripard 2017-01-26 11:22 ` Chen-Yu Tsai 2017-01-24 2:32 ` [PATCH 02/11] clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag Chen-Yu Tsai 2017-01-24 2:32 ` [PATCH 03/11] clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT Chen-Yu Tsai 2017-01-24 2:32 ` [PATCH 04/11] clk: sunxi-ng: Support separately grouped PLL lock status register Chen-Yu Tsai 2017-01-26 9:57 ` Maxime Ripard 2017-01-24 2:32 ` [PATCH 05/11] clk: sunxi-ng: Add A80 CCU Chen-Yu Tsai 2017-01-27 21:13 ` Rob Herring 2017-01-24 2:32 ` [PATCH 06/11] clk: sunxi-ng: Add A80 USB CCU Chen-Yu Tsai 2017-01-26 10:14 ` Maxime Ripard 2017-01-26 11:12 ` [linux-sunxi] " Chen-Yu Tsai 2017-01-27 8:45 ` Maxime Ripard 2017-01-27 21:15 ` Rob Herring 2017-01-24 2:32 ` [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU Chen-Yu Tsai 2017-01-26 10:39 ` Maxime Ripard 2017-01-26 11:20 ` Chen-Yu Tsai 2017-01-27 8:58 ` Maxime Ripard 2017-01-27 9:26 ` Chen-Yu Tsai 2017-01-27 9:42 ` Maxime Ripard 2017-01-24 2:32 ` [PATCH 08/11] ARM: dts: sun8i-a23-q8-tablet: Drop pinmux setting for codec PA gpio Chen-Yu Tsai 2017-01-26 10:38 ` Maxime Ripard 2017-01-26 11:15 ` Chen-Yu Tsai 2017-01-24 2:32 ` [PATCH 09/11] ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h header Chen-Yu Tsai 2017-01-26 10:21 ` Maxime Ripard 2017-01-24 2:32 ` [PATCH 10/11] arm64: dts: allwinner: " Chen-Yu Tsai 2017-01-26 10:15 ` Maxime Ripard 2017-01-26 11:23 ` Chen-Yu Tsai 2017-01-27 8:46 ` Maxime Ripard 2017-01-24 2:32 ` [PATCH 11/11] ARM: dts: sun9i: Switch to new clock bindings Chen-Yu Tsai 2017-01-24 6:03 ` [linux-sunxi] [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Priit Laes -- strict thread matches above, loose matches on Subject: below -- 2017-01-24 6:50 [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU Icenowy Zheng
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