From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Jon Hunter <jonathanh@nvidia.com>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@codeaurora.org>,
Stephen Warren <swarren@wwwdotorg.org>,
"Thierry Reding" <thierry.reding@gmail.com>,
Alexandre Courbot <gnurou@gmail.com>,
linux-clk <linux-clk@vger.kernel.org>,
<linux-tegra@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on
Date: Mon, 13 Mar 2017 16:18:50 +0200 [thread overview]
Message-ID: <20170313141850.GX26640@tbergstrom-lnx.Nvidia.com> (raw)
In-Reply-To: <9e81c653-b6bb-a47c-8891-d7c7d42a7650@nvidia.com>
On Mon, Mar 13, 2017 at 11:03:27AM +0000, Jon Hunter wrote:
>
> On 13/03/17 10:45, Peter De Schrijver wrote:
> > On Wed, Mar 08, 2017 at 11:48:21AM +0000, Jon Hunter wrote:
> >>
> >> On 08/03/17 11:38, Geert Uytterhoeven wrote:
> >>> Hi Jon,
> >>>
> >>> On Wed, Mar 8, 2017 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
> >>>>> I had a similar issue with SH-Mobile AG5, where the power domain containing
> >>>>> the JTAG interface is powered down.
> >>>>
> >>>> This reminds me, does your patch assume that the DFD power domain is
> >>>> enabled? I am guessing that it needs to be for JTAG to work.
> >>>
> >>> Yes. The pm-rmobile driver looks for "arm,coresight-etm3x" devices, and
> >>> marks the corresponding PM Domain as always-on, as long as the
> >>> Coresight code doesn't handle runtime PM.
> >>
> >> Sorry Geert, but I was asking Peter specifically about the power-domain
> >> on Tegra as I have a feeling we may have the same scenario ;-)
> >
> > We don't have a specific power domain for DFD on Tegra210. It's part of the
> > non-powergateable core domain.
>
> Either we are getting our wires crossed or the TRM is wrong :-(
>
> static const char * const tegra210_powergates[] = {
> [TEGRA_POWERGATE_CPU] = "crail",
> [TEGRA_POWERGATE_3D] = "3d",
> [TEGRA_POWERGATE_VENC] = "venc",
> [TEGRA_POWERGATE_PCIE] = "pcie",
> [TEGRA_POWERGATE_MPE] = "mpe",
> [TEGRA_POWERGATE_SATA] = "sata",
> [TEGRA_POWERGATE_CPU1] = "cpu1",
> [TEGRA_POWERGATE_CPU2] = "cpu2",
> [TEGRA_POWERGATE_CPU3] = "cpu3",
> [TEGRA_POWERGATE_CPU0] = "cpu0",
> [TEGRA_POWERGATE_C0NC] = "c0nc",
> [TEGRA_POWERGATE_SOR] = "sor",
> [TEGRA_POWERGATE_DIS] = "dis",
> [TEGRA_POWERGATE_DISB] = "disb",
> [TEGRA_POWERGATE_XUSBA] = "xusba",
> [TEGRA_POWERGATE_XUSBB] = "xusbb",
> [TEGRA_POWERGATE_XUSBC] = "xusbc",
> [TEGRA_POWERGATE_VIC] = "vic",
> [TEGRA_POWERGATE_IRAM] = "iram",
> [TEGRA_POWERGATE_NVDEC] = "nvdec",
> [TEGRA_POWERGATE_NVJPG] = "nvjpg",
> [TEGRA_POWERGATE_AUD] = "aud",
> [TEGRA_POWERGATE_DFD] = "dfd",
> [TEGRA_POWERGATE_VE2] = "ve2",
> };
>
This seems to exist indeed. However downstream has never used it, so I wonder
how well powergating this domain has been tested.
Peter.
next prev parent reply other threads:[~2017-03-13 14:18 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-28 15:19 [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on Peter De Schrijver
2017-03-02 17:56 ` Jon Hunter
2017-03-06 8:38 ` Peter De Schrijver
2017-03-06 9:58 ` Jon Hunter
2017-03-06 14:28 ` Peter De Schrijver
2017-03-06 15:46 ` Jon Hunter
2017-03-06 15:53 ` Geert Uytterhoeven
2017-03-07 20:27 ` Jon Hunter
2017-03-08 8:23 ` Geert Uytterhoeven
2017-03-08 10:13 ` Jon Hunter
2017-03-08 11:38 ` Geert Uytterhoeven
2017-03-08 11:48 ` Jon Hunter
2017-03-13 10:45 ` Peter De Schrijver
2017-03-13 11:03 ` Jon Hunter
2017-03-13 14:18 ` Peter De Schrijver [this message]
2017-03-13 10:47 ` Peter De Schrijver
2017-03-20 14:18 ` Thierry Reding
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