Re: [RFC 14/14] dt-bindings: tegra: Add Tegra210 EMC binding

Re: [RFC 14/14] dt-bindings: tegra: Add Tegra210 EMC binding

[Peter De Schrijver]

On Mon, Sep 24, 2018 at 02:04:24PM -0700, Rob Herring wrote:
> On Fri, Sep 14, 2018 at 11:03:09PM +0300, Peter De Schrijver wrote:
> > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> 
> Needs a commit msg.
> 
> > ---
> >  .../memory-controllers/nvidia,tegra210-emc.txt     | 448 +++++++++++++++++++++
> >  1 file changed, 448 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > new file mode 100644
> > index 0000000..1c52f47
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > @@ -0,0 +1,448 @@
> > +NVIDIA Tegra210 SoC EMC (external memory controller)
> > +====================================================
> > +
> > +Required properties :
> > +- compatible : Should be "nvidia,tegra21-emc", "nvidia,tegra124-emc".
> > +- reg : physical base address and length of the controller's registers.
> > +- nvidia,memory-controller : phandle of the MC driver.
> 
> Huh? What is this block then?
> 
> > +- clocks : phandles of the possible source clocks
> > +- clock-names : names of the possible source clocks
> > +
> > +The node should contain a "emc-table" subnode for each supported RAM type
> > +(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address
> > +being its RAM_CODE.
> 
> Unit address is based on reg property.
> 
> > +
> > +Required properties for "emc-table" nodes :
> > +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
> > +used for.
> > +
> > +Each "emc-table" node should contain a "emc-table" subnode for every supported
> > +EMC clock rate. The "emc-table" subnodes should have the clock rate in kHz as
> > +their unit address.
> > +
> > +Required properties for "emc-table" nodes :
> 
> Which emc-table nodes, the child or grand-child nodes?
> 
> > +- compatible  "nvidia,tegra21-emc-table", "nvidia,tegra210-emc-table"
> 
> > +- nvidia,revision : revision of the parameter set used for this node. All
> > +                    nodes in the same "emc-table" should have the same revision
> > +- clock-frequency : frequency in kHz
> > +- nvidia,emc-min-mv : minimum voltage for this OPP
> > +- nvidia,gk20a-min-mv : minimum GPU voltage for this OPP
> > +- nvidia,source : clock source to be used for this OPP
> 
> Is this memory timings/settings or OPPs? We have a binding for OPPs 
> already.
> 
> > +- nvidia,src-sel-reg : value of EMC CAR register to be used for this OPP
> > +- nvidia,needs-training : 1 if the OPP needs training at boot, 0 otherwise
> > +- nvidia,trained : 1 if initial training has been done by firmware, 0 otherwise
> > +- nvidia,periodic_training : 1 if the OPP needs periodic training, 0 otherwise
> > +- nvidia,trained_dram_clktree_c0d0u0 : training data word
> > +- nvidia,trained_dram_clktree_c0d0u1 : training data word
> 
> [...]
> 
> This is a huge list of properties. For all the things that are memory 
> timings, is there really value to defining a property for each setting? 
> Perhaps you should just define your own format and either make it a 
> separate firmware file or include that file in the dtb.
> 

The problem with moving to a binary blob is that it will break compatibility
with existing devices (eg. Jetson TX1 and shield TV) because their bootloaders
rely on the existing format.

Peter.

Re: [RFC 14/14] dt-bindings: tegra: Add Tegra210 EMC binding

[Rob Herring]

On Tue, Sep 25, 2018 at 8:03 AM Peter De Schrijver
<pdeschrijver@nvidia.com> wrote:
>
> On Mon, Sep 24, 2018 at 02:04:24PM -0700, Rob Herring wrote:
> > On Fri, Sep 14, 2018 at 11:03:09PM +0300, Peter De Schrijver wrote:
> > > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> >
> > Needs a commit msg.
> >
> > > ---
> > >  .../memory-controllers/nvidia,tegra210-emc.txt     | 448 +++++++++++++++++++++
> > >  1 file changed, 448 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > > new file mode 100644
> > > index 0000000..1c52f47
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > > @@ -0,0 +1,448 @@
> > > +NVIDIA Tegra210 SoC EMC (external memory controller)
> > > +====================================================
> > > +
> > > +Required properties :
> > > +- compatible : Should be "nvidia,tegra21-emc", "nvidia,tegra124-emc".
> > > +- reg : physical base address and length of the controller's registers.
> > > +- nvidia,memory-controller : phandle of the MC driver.
> >
> > Huh? What is this block then?
> >
> > > +- clocks : phandles of the possible source clocks
> > > +- clock-names : names of the possible source clocks
> > > +
> > > +The node should contain a "emc-table" subnode for each supported RAM type
> > > +(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address
> > > +being its RAM_CODE.
> >
> > Unit address is based on reg property.
> >
> > > +
> > > +Required properties for "emc-table" nodes :
> > > +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
> > > +used for.
> > > +
> > > +Each "emc-table" node should contain a "emc-table" subnode for every supported
> > > +EMC clock rate. The "emc-table" subnodes should have the clock rate in kHz as
> > > +their unit address.
> > > +
> > > +Required properties for "emc-table" nodes :
> >
> > Which emc-table nodes, the child or grand-child nodes?
> >
> > > +- compatible  "nvidia,tegra21-emc-table", "nvidia,tegra210-emc-table"
> >
> > > +- nvidia,revision : revision of the parameter set used for this node. All
> > > +                    nodes in the same "emc-table" should have the same revision
> > > +- clock-frequency : frequency in kHz
> > > +- nvidia,emc-min-mv : minimum voltage for this OPP
> > > +- nvidia,gk20a-min-mv : minimum GPU voltage for this OPP
> > > +- nvidia,source : clock source to be used for this OPP
> >
> > Is this memory timings/settings or OPPs? We have a binding for OPPs
> > already.
> >
> > > +- nvidia,src-sel-reg : value of EMC CAR register to be used for this OPP
> > > +- nvidia,needs-training : 1 if the OPP needs training at boot, 0 otherwise
> > > +- nvidia,trained : 1 if initial training has been done by firmware, 0 otherwise
> > > +- nvidia,periodic_training : 1 if the OPP needs periodic training, 0 otherwise
> > > +- nvidia,trained_dram_clktree_c0d0u0 : training data word
> > > +- nvidia,trained_dram_clktree_c0d0u1 : training data word
> >
> > [...]
> >
> > This is a huge list of properties. For all the things that are memory
> > timings, is there really value to defining a property for each setting?
> > Perhaps you should just define your own format and either make it a
> > separate firmware file or include that file in the dtb.
> >
>
> The problem with moving to a binary blob is that it will break compatibility
> with existing devices (eg. Jetson TX1 and shield TV) because their bootloaders
> rely on the existing format.

Good to know, but not really my problem that bindings shipped without
review. While this is self-contained and doesn't have any sort of
common binding which could be used instead, can you say that about
*everything* the bootloader depends on.

Rob

Re: [RFC 14/14] dt-bindings: tegra: Add Tegra210 EMC binding

[Peter De Schrijver]

Corrected the address of linux-clk in the CC line.

Peter.

On Tue, Sep 25, 2018 at 03:11:07PM +0300, Peter De Schrijver wrote:
> On Mon, Sep 24, 2018 at 02:04:24PM -0700, Rob Herring wrote:
> > On Fri, Sep 14, 2018 at 11:03:09PM +0300, Peter De Schrijver wrote:
> > > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> > 
> > Needs a commit msg.
> > 
> > > ---
> > >  .../memory-controllers/nvidia,tegra210-emc.txt     | 448 +++++++++++++++++++++
> > >  1 file changed, 448 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > > 
> > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > > new file mode 100644
> > > index 0000000..1c52f47
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > > @@ -0,0 +1,448 @@
> > > +NVIDIA Tegra210 SoC EMC (external memory controller)
> > > +====================================================
> > > +
> > > +Required properties :
> > > +- compatible : Should be "nvidia,tegra21-emc", "nvidia,tegra124-emc".
> > > +- reg : physical base address and length of the controller's registers.
> > > +- nvidia,memory-controller : phandle of the MC driver.
> > 
> > Huh? What is this block then?
> > 
> 
> This is the EMC. The EMC handles the interface with the external DRAM chips.
> The MC aggregates and schedules requests to the EMC. It also handles address
> translation. See figure 33 of the TRM.
> 
> > > +- clocks : phandles of the possible source clocks
> > > +- clock-names : names of the possible source clocks
> > > +
> > > +The node should contain a "emc-table" subnode for each supported RAM type
> > > +(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address
> > > +being its RAM_CODE.
> > 
> > Unit address is based on reg property.
> > 
> > > +
> > > +Required properties for "emc-table" nodes :
> > > +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
> > > +used for.
> > > +
> > > +Each "emc-table" node should contain a "emc-table" subnode for every supported
> > > +EMC clock rate. The "emc-table" subnodes should have the clock rate in kHz as
> > > +their unit address.
> > > +
> > > +Required properties for "emc-table" nodes :
> > 
> > Which emc-table nodes, the child or grand-child nodes?
> > 
> 
> The child "emc-table" node.
> 
> > > +- compatible  "nvidia,tegra21-emc-table", "nvidia,tegra210-emc-table"
> > 
> > > +- nvidia,revision : revision of the parameter set used for this node. All
> > > +                    nodes in the same "emc-table" should have the same revision
> > > +- clock-frequency : frequency in kHz
> > > +- nvidia,emc-min-mv : minimum voltage for this OPP
> > > +- nvidia,gk20a-min-mv : minimum GPU voltage for this OPP
> > > +- nvidia,source : clock source to be used for this OPP
> > 
> > Is this memory timings/settings or OPPs? We have a binding for OPPs 
> > already.
> > 
> 
> This is memory timings.
> 
> > > +- nvidia,src-sel-reg : value of EMC CAR register to be used for this OPP
> > > +- nvidia,needs-training : 1 if the OPP needs training at boot, 0 otherwise
> > > +- nvidia,trained : 1 if initial training has been done by firmware, 0 otherwise
> > > +- nvidia,periodic_training : 1 if the OPP needs periodic training, 0 otherwise
> > > +- nvidia,trained_dram_clktree_c0d0u0 : training data word
> > > +- nvidia,trained_dram_clktree_c0d0u1 : training data word
> > 
> > [...]
> > 
> > This is a huge list of properties. For all the things that are memory 
> > timings, is there really value to defining a property for each setting? 
> > Perhaps you should just define your own format and either make it a 
> > separate firmware file or include that file in the dtb.
> 
> If it's a binary structure, how would this be passed given the bootloader has
> to fill in the training information?
> 
> Peter.

Re: [RFC 14/14] dt-bindings: tegra: Add Tegra210 EMC binding

[Rob Herring]

On Tue, Sep 25, 2018 at 7:11 AM Peter De Schrijver
<pdeschrijver@nvidia.com> wrote:
>
> On Mon, Sep 24, 2018 at 02:04:24PM -0700, Rob Herring wrote:
> > On Fri, Sep 14, 2018 at 11:03:09PM +0300, Peter De Schrijver wrote:
> > > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> >
> > Needs a commit msg.
> >
> > > ---
> > >  .../memory-controllers/nvidia,tegra210-emc.txt     | 448 +++++++++++++++++++++
> > >  1 file changed, 448 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > > new file mode 100644
> > > index 0000000..1c52f47
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > > @@ -0,0 +1,448 @@
> > > +NVIDIA Tegra210 SoC EMC (external memory controller)
> > > +====================================================
> > > +
> > > +Required properties :
> > > +- compatible : Should be "nvidia,tegra21-emc", "nvidia,tegra124-emc".
> > > +- reg : physical base address and length of the controller's registers.
> > > +- nvidia,memory-controller : phandle of the MC driver.
> >
> > Huh? What is this block then?
> >
>
> This is the EMC. The EMC handles the interface with the external DRAM chips.
> The MC aggregates and schedules requests to the EMC. It also handles address
> translation. See figure 33 of the TRM.

Sorry, but I hardly have time to go read TRM's for every binding.

Just explain what the MC is here and remove 'driver'.

> > > +- clocks : phandles of the possible source clocks
> > > +- clock-names : names of the possible source clocks
> > > +
> > > +The node should contain a "emc-table" subnode for each supported RAM type
> > > +(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address
> > > +being its RAM_CODE.
> >
> > Unit address is based on reg property.
> >
> > > +
> > > +Required properties for "emc-table" nodes :
> > > +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
> > > +used for.
> > > +
> > > +Each "emc-table" node should contain a "emc-table" subnode for every supported
> > > +EMC clock rate. The "emc-table" subnodes should have the clock rate in kHz as
> > > +their unit address.
> > > +
> > > +Required properties for "emc-table" nodes :
> >
> > Which emc-table nodes, the child or grand-child nodes?
> >
>
> The child "emc-table" node.
>
> > > +- compatible  "nvidia,tegra21-emc-table", "nvidia,tegra210-emc-table"
> >
> > > +- nvidia,revision : revision of the parameter set used for this node. All
> > > +                    nodes in the same "emc-table" should have the same revision
> > > +- clock-frequency : frequency in kHz
> > > +- nvidia,emc-min-mv : minimum voltage for this OPP
> > > +- nvidia,gk20a-min-mv : minimum GPU voltage for this OPP
> > > +- nvidia,source : clock source to be used for this OPP
> >
> > Is this memory timings/settings or OPPs? We have a binding for OPPs
> > already.
> >
>
> This is memory timings.
>
> > > +- nvidia,src-sel-reg : value of EMC CAR register to be used for this OPP
> > > +- nvidia,needs-training : 1 if the OPP needs training at boot, 0 otherwise
> > > +- nvidia,trained : 1 if initial training has been done by firmware, 0 otherwise
> > > +- nvidia,periodic_training : 1 if the OPP needs periodic training, 0 otherwise
> > > +- nvidia,trained_dram_clktree_c0d0u0 : training data word
> > > +- nvidia,trained_dram_clktree_c0d0u1 : training data word
> >
> > [...]
> >
> > This is a huge list of properties. For all the things that are memory
> > timings, is there really value to defining a property for each setting?
> > Perhaps you should just define your own format and either make it a
> > separate firmware file or include that file in the dtb.
>
> If it's a binary structure, how would this be passed given the bootloader has
> to fill in the training information?

Perhaps training data makes sense to keep as DT properties, but it is
not all training data, right? Things like a list of register
initialization values do not sound like training data.

I assume the the training data is read back from the h/w, can't the
kernel just do that itself? Or the data is lost after init is
complete?

Rob

Re: [RFC 14/14] dt-bindings: tegra: Add Tegra210 EMC binding

[Peter De Schrijver]

On Tue, Sep 25, 2018 at 09:37:59AM -0500, Rob Herring wrote:
> On Tue, Sep 25, 2018 at 7:11 AM Peter De Schrijver
> <pdeschrijver@nvidia.com> wrote:
> >
> > On Mon, Sep 24, 2018 at 02:04:24PM -0700, Rob Herring wrote:
> > > On Fri, Sep 14, 2018 at 11:03:09PM +0300, Peter De Schrijver wrote:
> > > > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> > >
> > > Needs a commit msg.
> > >
> > > > ---
> > > >  .../memory-controllers/nvidia,tegra210-emc.txt     | 448 +++++++++++++++++++++
> > > >  1 file changed, 448 insertions(+)
> > > >  create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > > > new file mode 100644
> > > > index 0000000..1c52f47
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
> > > > @@ -0,0 +1,448 @@
> > > > +NVIDIA Tegra210 SoC EMC (external memory controller)
> > > > +====================================================
> > > > +
> > > > +Required properties :
> > > > +- compatible : Should be "nvidia,tegra21-emc", "nvidia,tegra124-emc".
> > > > +- reg : physical base address and length of the controller's registers.
> > > > +- nvidia,memory-controller : phandle of the MC driver.
> > >
> > > Huh? What is this block then?
> > >
> >
> > This is the EMC. The EMC handles the interface with the external DRAM chips.
> > The MC aggregates and schedules requests to the EMC. It also handles address
> > translation. See figure 33 of the TRM.
> 
> Sorry, but I hardly have time to go read TRM's for every binding.
> 
> Just explain what the MC is here and remove 'driver'.
> 
> > > > +- clocks : phandles of the possible source clocks
> > > > +- clock-names : names of the possible source clocks
> > > > +
> > > > +The node should contain a "emc-table" subnode for each supported RAM type
> > > > +(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address
> > > > +being its RAM_CODE.
> > >
> > > Unit address is based on reg property.
> > >
> > > > +
> > > > +Required properties for "emc-table" nodes :
> > > > +- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
> > > > +used for.
> > > > +
> > > > +Each "emc-table" node should contain a "emc-table" subnode for every supported
> > > > +EMC clock rate. The "emc-table" subnodes should have the clock rate in kHz as
> > > > +their unit address.
> > > > +
> > > > +Required properties for "emc-table" nodes :
> > >
> > > Which emc-table nodes, the child or grand-child nodes?
> > >
> >
> > The child "emc-table" node.
> >
> > > > +- compatible  "nvidia,tegra21-emc-table", "nvidia,tegra210-emc-table"
> > >
> > > > +- nvidia,revision : revision of the parameter set used for this node. All
> > > > +                    nodes in the same "emc-table" should have the same revision
> > > > +- clock-frequency : frequency in kHz
> > > > +- nvidia,emc-min-mv : minimum voltage for this OPP
> > > > +- nvidia,gk20a-min-mv : minimum GPU voltage for this OPP
> > > > +- nvidia,source : clock source to be used for this OPP
> > >
> > > Is this memory timings/settings or OPPs? We have a binding for OPPs
> > > already.
> > >
> >
> > This is memory timings.
> >
> > > > +- nvidia,src-sel-reg : value of EMC CAR register to be used for this OPP
> > > > +- nvidia,needs-training : 1 if the OPP needs training at boot, 0 otherwise
> > > > +- nvidia,trained : 1 if initial training has been done by firmware, 0 otherwise
> > > > +- nvidia,periodic_training : 1 if the OPP needs periodic training, 0 otherwise
> > > > +- nvidia,trained_dram_clktree_c0d0u0 : training data word
> > > > +- nvidia,trained_dram_clktree_c0d0u1 : training data word
> > >
> > > [...]
> > >
> > > This is a huge list of properties. For all the things that are memory
> > > timings, is there really value to defining a property for each setting?
> > > Perhaps you should just define your own format and either make it a
> > > separate firmware file or include that file in the dtb.
> >
> > If it's a binary structure, how would this be passed given the bootloader has
> > to fill in the training information?
> 
> Perhaps training data makes sense to keep as DT properties, but it is
> not all training data, right? Things like a list of register
> initialization values do not sound like training data.
> 

No, those are per frequency timing settings, just like we have them for
Tegra124 and previous chips.

> I assume the the training data is read back from the h/w, can't the
> kernel just do that itself? Or the data is lost after init is
> complete?

The data is mostly lost. The training data also depends on the frequency, so
if it could be read back from the h/w, it would only be the data for the last
frequency which was trained.

Peter.

[RFC 00/14] Tegra210 EMC scaling

[Peter De Schrijver]

This series introduces EMC scaling for Tegra210. It's a preliminary version
which hasn't been extensively tested so it may crash your system. The reason
I'm posting it anyway to start discussing the DT binding document. The
problem here is that this binding is also used by firmware which is already
in the field. The firmware needs the data in the DT to perform the initial
training and it also writes the results of this training in the DT which are
then used by this driver. Without this training higher OPPs cannot be used.

Peter De Schrijver (14):
  memory: tegra: mc: Add Tegra210 MC emem registers
  clk: tegra: rename emc timing functions
  clk: tegra: emc: simplify parent matching
  clk: tegra: emc: prepare for Tegra210 parent table
  memory: tegra: mc: Introduce helpers
  memory: tegra: mc: Add support for scaled LA
  memory: tegra: scaled LA register for Tegra210
  clk: tegra: clock changes for emc scaling
  memory: tegra: Add definitions shared by Tegra210 EMC scaling code
  memory: tegra: Add Tegra210 EMC scaling sequence
  memory: tegra: parse DT and costruct timing tables
  memory: tegra: Tegra210 EMC memory driver
  memory: tegra: enable Tegra210 EMC scaling driver
  dt-bindings: tegra: Add Tegra210 EMC binding

 .../memory-controllers/nvidia,tegra210-emc.txt     |  448 ++++
 drivers/clk/tegra/clk-emc.c                        |   88 +-
 drivers/clk/tegra/clk-tegra210.c                   |   53 +-
 drivers/memory/tegra/Kconfig                       |   10 +
 drivers/memory/tegra/Makefile                      |    1 +
 drivers/memory/tegra/mc.c                          |   84 +-
 drivers/memory/tegra/tegra124-emc.c                |    8 +-
 drivers/memory/tegra/tegra210-dt-parse.c           |  363 ++++
 drivers/memory/tegra/tegra210-emc-cc-r21021.c      | 1864 ++++++++++++++++
 drivers/memory/tegra/tegra210-emc-reg.h            | 1879 ++++++++++++++++
 drivers/memory/tegra/tegra210-emc.c                | 2268 ++++++++++++++++++++
 drivers/memory/tegra/tegra210.c                    |   99 +
 include/dt-bindings/clock/tegra210-car.h           |    2 +
 include/soc/tegra/emc.h                            |    8 +-
 include/soc/tegra/mc.h                             |    6 +
 15 files changed, 7119 insertions(+), 62 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
 create mode 100644 drivers/memory/tegra/tegra210-dt-parse.c
 create mode 100644 drivers/memory/tegra/tegra210-emc-cc-r21021.c
 create mode 100644 drivers/memory/tegra/tegra210-emc-reg.h
 create mode 100644 drivers/memory/tegra/tegra210-emc.c

-- 
1.9.1

[RFC 14/14] dt-bindings: tegra: Add Tegra210 EMC binding

[Peter De Schrijver]

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 .../memory-controllers/nvidia,tegra210-emc.txt     | 448 +++++++++++++++++++++
 1 file changed, 448 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
new file mode 100644
index 0000000..1c52f47
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt
@@ -0,0 +1,448 @@
+NVIDIA Tegra210 SoC EMC (external memory controller)
+====================================================
+
+Required properties :
+- compatible : Should be "nvidia,tegra21-emc", "nvidia,tegra124-emc".
+- reg : physical base address and length of the controller's registers.
+- nvidia,memory-controller : phandle of the MC driver.
+- clocks : phandles of the possible source clocks
+- clock-names : names of the possible source clocks
+
+The node should contain a "emc-table" subnode for each supported RAM type
+(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address
+being its RAM_CODE.
+
+Required properties for "emc-table" nodes :
+- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
+used for.
+
+Each "emc-table" node should contain a "emc-table" subnode for every supported
+EMC clock rate. The "emc-table" subnodes should have the clock rate in kHz as
+their unit address.
+
+Required properties for "emc-table" nodes :
+- compatible  "nvidia,tegra21-emc-table", "nvidia,tegra210-emc-table"
+- nvidia,revision : revision of the parameter set used for this node. All
+                    nodes in the same "emc-table" should have the same revision
+- clock-frequency : frequency in kHz
+- nvidia,emc-min-mv : minimum voltage for this OPP
+- nvidia,gk20a-min-mv : minimum GPU voltage for this OPP
+- nvidia,source : clock source to be used for this OPP
+- nvidia,src-sel-reg : value of EMC CAR register to be used for this OPP
+- nvidia,needs-training : 1 if the OPP needs training at boot, 0 otherwise
+- nvidia,trained : 1 if initial training has been done by firmware, 0 otherwise
+- nvidia,periodic_training : 1 if the OPP needs periodic training, 0 otherwise
+- nvidia,trained_dram_clktree_c0d0u0 : training data word
+- nvidia,trained_dram_clktree_c0d0u1 : training data word
+- nvidia,trained_dram_clktree_c0d1u0 : training data word
+- nvidia,trained_dram_clktree_c0d1u1 : training data word
+- nvidia,trained_dram_clktree_c1d0u0 : training data word
+- nvidia,trained_dram_clktree_c1d0u1 : training data word
+- nvidia,trained_dram_clktree_c1d1u0 : training data word
+- nvidia,trained_dram_clktree_c1d1u1 : training data word
+- nvidia,run_clocks : training data
+- nvidia,tree_margin : training data
+- nvidia,burst-regs-num : number of values in nvidia,emc-registers
+- nvidia,burst-regs-per-ch-num : number of values in nvidia,emc-burst-regs-per-ch
+- nvidia,trim-regs-num : number of values in nvidia,emc-trim-regs
+- nvidia,trim-regs-per-ch-num : number of values in nvidia,emc-trim-regs-per-ch
+- nvidia,burst-mc-regs-num : number of values in nvidia,emc-burst-mc-regs
+- nvidia,la-scale-regs-num : number of values in nvidia,emc-la-scale-regs
+- nvidia,vref-regs-num : number of values in nvidia,emc-vref-regs
+- nvidia,dram-timing-regs: number of values in nvidia,emc-dram-timing-regs
+- nvidia,min-mrs-wait : value of the EMC_MRW register
+- nvidia,emc-mrw : value of the EMC_MRW register
+- nvidia,emc-mrw2 : value of the EMC_MRW2 register
+- nvidia,emc-mrw3 : used to determine the value of EMC_MRW3
+- nvidia,emc-mrw4 : value of EMC_MRW4
+- nvidia,ptfv : control data for periodic training
+- nvidia,emc-registers : values for the following registers (See TRM 18.11.2 for register descriptions)
+	 EMC_RC
+	 EMC_RFC
+	 EMC_RFCPB
+	 EMC_REFCTRL2
+	 EMC_RFC_SLR
+	 EMC_RAS
+	 EMC_RP
+	 EMC_R2W
+	 EMC_W2R
+	 EMC_R2P
+	 EMC_W2P
+	 EMC_R2R
+	 EMC_TPPD
+	 EMC_CCDMW
+	 EMC_RD_RCD
+	 EMC_WR_RCD
+	 EMC_RRD
+	 EMC_REXT
+	 EMC_WEXT
+	 EMC_WDV_CHK
+	 EMC_WDV
+	 EMC_WSV
+	 EMC_WEV
+	 EMC_WDV_MASK
+	 EMC_WS_DURATION
+	 EMC_WE_DURATION
+	 EMC_QUSE
+	 EMC_QUSE_WIDTH
+	 EMC_IBDLY
+	 EMC_OBDLY
+	 EMC_EINPUT
+	 EMC_MRW6
+	 EMC_EINPUT_DURATION
+	 EMC_PUTERM_EXTRA
+	 EMC_PUTERM_WIDTH
+	 EMC_QRST
+	 EMC_QSAFE
+	 EMC_RDV
+	 EMC_RDV_MASK
+	 EMC_RDV_EARLY
+	 EMC_RDV_EARLY_MASK
+	 EMC_REFRESH
+	 EMC_BURST_REFRESH_NUM
+	 EMC_PRE_REFRESH_REQ_CNT
+	 EMC_PDEX2WR
+	 EMC_PDEX2RD
+	 EMC_PCHG2PDEN
+	 EMC_ACT2PDEN
+	 EMC_AR2PDEN
+	 EMC_RW2PDEN
+	 EMC_CKE2PDEN
+	 EMC_PDEX2CKE
+	 EMC_PDEX2MRR
+	 EMC_TXSR
+	 EMC_TXSRDLL
+	 EMC_TCKE
+	 EMC_TCKESR
+	 EMC_TPD
+	 EMC_TFAW
+	 EMC_TRPAB
+	 EMC_TCLKSTABLE
+	 EMC_TCLKSTOP
+	 EMC_MRW7
+	 EMC_TREFBW
+	 EMC_ODT_WRITE
+	 EMC_FBIO_CFG5
+	 EMC_FBIO_CFG7
+	 EMC_CFG_DIG_DLL
+	 EMC_CFG_DIG_DLL_PERIOD
+	 EMC_PMACRO_IB_RXRT
+	 EMC_CFG_PIPE_1
+	 EMC_CFG_PIPE_2
+	 EMC_PMACRO_QUSE_DDLL_RANK0_4
+	 EMC_PMACRO_QUSE_DDLL_RANK0_5
+	 EMC_PMACRO_QUSE_DDLL_RANK1_4
+	 EMC_PMACRO_QUSE_DDLL_RANK1_5
+	 EMC_MRW8
+	 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4
+	 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5
+	 EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0
+	 EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1
+	 EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2
+	 EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3
+	 EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4
+	 EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5
+	 EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0
+	 EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1
+	 EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2
+	 EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3
+	 EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4
+	 EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5
+	 EMC_PMACRO_DDLL_LONG_CMD_0
+	 EMC_PMACRO_DDLL_LONG_CMD_1
+	 EMC_PMACRO_DDLL_LONG_CMD_2
+	 EMC_PMACRO_DDLL_LONG_CMD_3
+	 EMC_PMACRO_DDLL_LONG_CMD_4
+	 EMC_PMACRO_DDLL_SHORT_CMD_0
+	 EMC_PMACRO_DDLL_SHORT_CMD_1
+	 EMC_PMACRO_DDLL_SHORT_CMD_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3
+	 EMC_TXDSRVTTGEN
+	 EMC_FDPD_CTRL_DQ
+	 EMC_FDPD_CTRL_CMD
+	 EMC_FBIO_SPARE
+	 EMC_ZCAL_INTERVAL
+	 EMC_ZCAL_WAIT_CNT
+	 EMC_MRS_WAIT_CNT
+	 EMC_MRS_WAIT_CNT2
+	 EMC_AUTO_CAL_CHANNEL
+	 EMC_DLL_CFG_0
+	 EMC_DLL_CFG_1
+	 EMC_PMACRO_AUTOCAL_CFG_COMMON
+	 EMC_PMACRO_ZCTRL
+	 EMC_CFG
+	 EMC_CFG_PIPE
+	 EMC_DYN_SELF_REF_CONTROL
+	 EMC_QPOP
+	 EMC_DQS_BRLSHFT_0
+	 EMC_DQS_BRLSHFT_1
+	 EMC_CMD_BRLSHFT_2
+	 EMC_CMD_BRLSHFT_3
+	 EMC_PMACRO_PAD_CFG_CTRL
+	 EMC_PMACRO_DATA_PAD_RX_CTRL
+	 EMC_PMACRO_CMD_PAD_RX_CTRL
+	 EMC_PMACRO_DATA_RX_TERM_MODE
+	 EMC_PMACRO_CMD_RX_TERM_MODE
+	 EMC_PMACRO_CMD_PAD_TX_CTRL
+	 EMC_PMACRO_DATA_PAD_TX_CTRL
+	 EMC_PMACRO_COMMON_PAD_TX_CTRL
+	 EMC_PMACRO_VTTGEN_CTRL_0
+	 EMC_PMACRO_VTTGEN_CTRL_1
+	 EMC_PMACRO_VTTGEN_CTRL_2
+	 EMC_PMACRO_BRICK_CTRL_RFU1
+	 EMC_PMACRO_CMD_BRICK_CTRL_FDPD
+	 EMC_PMACRO_BRICK_CTRL_RFU2
+	 EMC_PMACRO_DATA_BRICK_CTRL_FDPD
+	 EMC_PMACRO_BG_BIAS_CTRL_0
+	 EMC_CFG_3
+	 EMC_PMACRO_TX_PWRD_0
+	 EMC_PMACRO_TX_PWRD_1
+	 EMC_PMACRO_TX_PWRD_2
+	 EMC_PMACRO_TX_PWRD_3
+	 EMC_PMACRO_TX_PWRD_4
+	 EMC_PMACRO_TX_PWRD_5
+	 EMC_CONFIG_SAMPLE_DELAY
+	 EMC_PMACRO_TX_SEL_CLK_SRC_0
+	 EMC_PMACRO_TX_SEL_CLK_SRC_1
+	 EMC_PMACRO_TX_SEL_CLK_SRC_2
+	 EMC_PMACRO_TX_SEL_CLK_SRC_3
+	 EMC_PMACRO_TX_SEL_CLK_SRC_4
+	 EMC_PMACRO_TX_SEL_CLK_SRC_5
+	 EMC_PMACRO_DDLL_BYPASS
+	 EMC_PMACRO_DDLL_PWRD_0
+	 EMC_PMACRO_DDLL_PWRD_1
+	 EMC_PMACRO_DDLL_PWRD_2
+	 EMC_PMACRO_CMD_CTRL_0
+	 EMC_PMACRO_CMD_CTRL_1
+	 EMC_PMACRO_CMD_CTRL_2
+	 EMC_TR_TIMING_0
+	 EMC_TR_DVFS
+	 EMC_TR_CTRL_1
+	 EMC_TR_RDV
+	 EMC_TR_QPOP
+	 EMC_TR_RDV_MASK
+	 EMC_MRW14
+	 EMC_TR_QSAFE
+	 EMC_TR_QRST
+	 EMC_TRAINING_CTRL
+	 EMC_TRAINING_SETTLE
+	 EMC_TRAINING_VREF_SETTLE
+	 EMC_TRAINING_CA_FINE_CTRL
+	 EMC_TRAINING_CA_CTRL_MISC
+	 EMC_TRAINING_CA_CTRL_MISC1
+	 EMC_TRAINING_CA_VREF_CTRL
+	 EMC_TRAINING_QUSE_CORS_CTRL
+	 EMC_TRAINING_QUSE_FINE_CTRL
+	 EMC_TRAINING_QUSE_CTRL_MISC
+	 EMC_TRAINING_QUSE_VREF_CTRL
+	 EMC_TRAINING_READ_FINE_CTRL
+	 EMC_TRAINING_READ_CTRL_MISC
+	 EMC_TRAINING_READ_VREF_CTRL
+	 EMC_TRAINING_WRITE_FINE_CTRL
+	 EMC_TRAINING_WRITE_CTRL_MISC
+	 EMC_TRAINING_WRITE_VREF_CTRL
+	 EMC_TRAINING_MPC
+	 EMC_MRW15
+- nvidia,emc-burst-regs-per-ch : values for the following registers (See TRM 18.11.2 for register descriptions)
+	 the array containts 2 values for each register, one per channel.
+	 EMC_MRW10
+	 EMC_MRW11
+	 EMC_MRW12
+	 EMC_MRW13
+- nvidia,emc-trim-regs : values for the following registers (See TRM 18.11.2 for register descriptions)
+	 EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0
+	 EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1
+	 EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2
+	 EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3
+	 EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0
+	 EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1
+	 EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2
+	 EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1
+	 EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2
+	 EMC_PMACRO_IB_VREF_DQS_0
+	 EMC_PMACRO_IB_VREF_DQS_1
+	 EMC_PMACRO_IB_VREF_DQ_0
+	 EMC_PMACRO_IB_VREF_DQ_1
+	 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0
+	 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1
+	 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2
+	 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3
+	 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4
+	 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5
+	 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0
+	 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1
+	 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2
+	 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1
+	 EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2
+	 EMC_PMACRO_QUSE_DDLL_RANK0_0
+	 EMC_PMACRO_QUSE_DDLL_RANK0_1
+	 EMC_PMACRO_QUSE_DDLL_RANK0_2
+	 EMC_PMACRO_QUSE_DDLL_RANK0_3
+	 EMC_PMACRO_QUSE_DDLL_RANK1_0
+	 EMC_PMACRO_QUSE_DDLL_RANK1_1
+	 EMC_PMACRO_QUSE_DDLL_RANK1_2
+	 EMC_PMACRO_QUSE_DDLL_RANK1_3
+- nvidia,emc-trim-regs-per-ch : values for the following registers (See TRM 18.11.2 for register descriptions)
+	 EMC_CMD_BRLSHFT_0
+	 EMC_CMD_BRLSHFT_1
+	 EMC_DATA_BRLSHFT_0 (channel 0)
+	 EMC_DATA_BRLSHFT_0 (channel 1)
+	 EMC_DATA_BRLSHFT_1 (channel 0)
+	 EMC_DATA_BRLSHFT_1 (channel 1)
+	 EMC_QUSE_BRLSHFT_0
+	 EMC_QUSE_BRLSHFT_1
+	 EMC_QUSE_BRLSHFT_2
+	 EMC_QUSE_BRLSHFT_3
+- nvidia,emc-vref-regs : values for the following registers (See TRM 18.11.2 for register descriptions)
+	 the array containts 2 values for each register, one per channel.
+	 EMC_TRAINING_OPT_DQS_IB_VREF_RANK0
+	 EMC_TRAINING_OPT_DQS_IB_VREF_RANK1
+- nvidia,emc-dram-timing-regs : DRAM timing values. These are not written to
+				registers but used during the sequence.
+	 T_RP : row pre-charge delay
+	 T_FC_LPDDR4 : frequency change time
+	 T_RFC : refresh cycle time
+	 T_PDEX : power down exit delay
+	 RL : mode register read latency
+
-- 
1.9.1