[GIT PULL] clk: renesas: Updates for v5.17

[GIT PULL] clk: renesas: Updates for v5.17

[Geert Uytterhoeven]

	Hi Mike, Stephen,

The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf:

  Linux 5.16-rc1 (2021-11-14 13:56:52 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v5.17-tag1

for you to fetch changes up to 33b22d9c3272003a525ba2d6b7b851f3d4f30574:

  clk: renesas: r9a07g044: Add TSU clock and reset entry (2021-11-26 14:06:16 +0100)

----------------------------------------------------------------
clk: renesas: Updates for v5.17

  - Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and
    thermal (TSU) clocks and resets on RZ/G2L,
  - Rework SDHI clock handling in the R-Car Gen3 and RZ/G2 clock
    drivers, and in the Renesas SDHI driver,
  - Make the Cortex-A55 (I) clock on RZ/G2L programmable,
  - Document support for the new R-Car S4-8 (R8A779F0) SoC,
  - Miscellaneous fixes and improvements.

Note that due to dependencies between Renesas Clock and Renesas SDHI
driver changes, I'm handling Renesas SDHI changes for this cycle.
Hence the presence of several Renesas SDHI commits.

Thanks for pulling!
----------------------------------------------------------------
Biju Das (6):
      clk: renesas: r9a07g044: Add WDT clock and reset entries
      clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros
      clk: renesas: r9a07g044: Add OSTM clock and reset entries
      clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
      clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
      clk: renesas: r9a07g044: Add TSU clock and reset entry

Geert Uytterhoeven (2):
      clk: renesas: rzg2l: Add missing kerneldoc for resets
      mmc: renesas_sdhi: Use devm_clk_get_optional() to obtain CD clock

Lad Prabhakar (6):
      clk: renesas: r9a07g044: Add clock and reset entry for SCI1
      clk: renesas: r9a07g044: Add RSPI clock and reset entries
      clk: renesas: rzg2l: Check return value of pm_genpd_init()
      clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()
      clk: renesas: cpg-mssr: Check return value of pm_genpd_init()
      clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()

Wolfram Sang (9):
      clk: renesas: rcar-gen3: Add dummy SDnH clock
      clk: renesas: rcar-gen3: Add SDnH clock
      clk: renesas: r8a779a0: Add SDnH clock to V3U
      mmc: renesas_sdhi: Flag non-standard SDnH handling for V3M
      clk: renesas: rcar-gen3: Switch to new SD clock handling
      clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRST
      mmc: renesas_sdhi: Use dev_err_probe when getting clock fails
      mmc: renesas_sdhi: Parse DT for SDnH
      mmc: renesas_sdhi: Simplify an expression

Yoshihiro Shimoda (1):
      dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0

 .../bindings/clock/renesas,cpg-mssr.yaml           |   1 +
 drivers/clk/renesas/r8a774a1-cpg-mssr.c            |  12 +-
 drivers/clk/renesas/r8a774b1-cpg-mssr.c            |  12 +-
 drivers/clk/renesas/r8a774c0-cpg-mssr.c            |   9 +-
 drivers/clk/renesas/r8a774e1-cpg-mssr.c            |  12 +-
 drivers/clk/renesas/r8a7795-cpg-mssr.c             |  12 +-
 drivers/clk/renesas/r8a7796-cpg-mssr.c             |  12 +-
 drivers/clk/renesas/r8a77965-cpg-mssr.c            |  12 +-
 drivers/clk/renesas/r8a77980-cpg-mssr.c            |   3 +-
 drivers/clk/renesas/r8a77990-cpg-mssr.c            |   9 +-
 drivers/clk/renesas/r8a77995-cpg-mssr.c            |   3 +-
 drivers/clk/renesas/r8a779a0-cpg-mssr.c            |  17 +-
 drivers/clk/renesas/r9a07g044-cpg.c                |  62 +++++-
 drivers/clk/renesas/rcar-cpg-lib.c                 | 211 +++------------------
 drivers/clk/renesas/rcar-cpg-lib.h                 |   7 +-
 drivers/clk/renesas/rcar-gen3-cpg.c                |  24 +--
 drivers/clk/renesas/rcar-gen3-cpg.h                |   4 +
 drivers/clk/renesas/renesas-cpg-mssr.c             |  18 +-
 drivers/clk/renesas/rzg2l-cpg.c                    |  18 +-
 drivers/clk/renesas/rzg2l-cpg.h                    |   5 +
 drivers/mmc/host/renesas_sdhi.h                    |   4 +
 drivers/mmc/host/renesas_sdhi_core.c               |  45 +++--
 drivers/mmc/host/renesas_sdhi_internal_dmac.c      |  21 ++
 23 files changed, 269 insertions(+), 264 deletions(-)

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

Re: [GIT PULL] clk: renesas: Updates for v5.17

[Stephen Boyd]

Quoting Geert Uytterhoeven (2021-12-03 04:30:58)
>         Hi Mike, Stephen,
> 
> The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf:
> 
>   Linux 5.16-rc1 (2021-11-14 13:56:52 -0800)
> 
> are available in the Git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v5.17-tag1
> 
> for you to fetch changes up to 33b22d9c3272003a525ba2d6b7b851f3d4f30574:
> 
>   clk: renesas: r9a07g044: Add TSU clock and reset entry (2021-11-26 14:06:16 +0100)
> 
> ----------------------------------------------------------------

Thanks. Pulled into clk-next