Re: [PATCH 3/8] clk: imx: pll14xx: Use FIELD_GET/FIELD_PREP

[kernel test robot <lkp@intel.com>]

Hi Sascha,

I love your patch! Yet something to improve:

[auto build test ERROR on shawnguo/for-next]
[also build test ERROR on clk/clk-next v5.17-rc5 next-20220222]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Sascha-Hauer/clk-i-MX-PLL14xx-Support-dynamic-rates/20220223-155846
base:   https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
config: hexagon-randconfig-r015-20220221 (https://download.01.org/0day-ci/archive/20220223/202202232030.DHNZfsc4-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project d271fc04d5b97b12e6b797c6067d3c96a8d7470e)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/c12e6c700842e937d181c80ce6ada39017ed6268
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Sascha-Hauer/clk-i-MX-PLL14xx-Support-dynamic-rates/20220223-155846
        git checkout c12e6c700842e937d181c80ce6ada39017ed6268
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=hexagon SHELL=/bin/bash drivers/clk/imx/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> drivers/clk/imx/clk-pll14xx.c:123:9: error: implicit declaration of function 'FIELD_GET' [-Werror,-Wimplicit-function-declaration]
           mdiv = FIELD_GET(MDIV_MASK, pll_div);
                  ^
   drivers/clk/imx/clk-pll14xx.c:143:9: error: implicit declaration of function 'FIELD_GET' [-Werror,-Wimplicit-function-declaration]
           mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0);
                  ^
   drivers/clk/imx/clk-pll14xx.c:162:13: error: implicit declaration of function 'FIELD_GET' [-Werror,-Wimplicit-function-declaration]
           old_mdiv = FIELD_GET(MDIV_MASK, pll_div);
                      ^
>> drivers/clk/imx/clk-pll14xx.c:195:10: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
                   tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv);
                          ^
   drivers/clk/imx/clk-pll14xx.c:214:12: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
           div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) |
                     ^
   drivers/clk/imx/clk-pll14xx.c:261:10: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
                   tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv);
                          ^
   drivers/clk/imx/clk-pll14xx.c:279:12: error: implicit declaration of function 'FIELD_PREP' [-Werror,-Wimplicit-function-declaration]
           div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) |
                     ^
   7 errors generated.


vim +/FIELD_GET +123 drivers/clk/imx/clk-pll14xx.c

   114	
   115	static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw,
   116							  unsigned long parent_rate)
   117	{
   118		struct clk_pll14xx *pll = to_clk_pll14xx(hw);
   119		u32 mdiv, pdiv, sdiv, pll_div;
   120		u64 fvco = parent_rate;
   121	
   122		pll_div = readl_relaxed(pll->base + DIV_CTL0);
 > 123		mdiv = FIELD_GET(MDIV_MASK, pll_div);
   124		pdiv = FIELD_GET(PDIV_MASK, pll_div);
   125		sdiv = FIELD_GET(SDIV_MASK, pll_div);
   126	
   127		fvco *= mdiv;
   128		do_div(fvco, pdiv << sdiv);
   129	
   130		return fvco;
   131	}
   132	
   133	static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw,
   134							  unsigned long parent_rate)
   135	{
   136		struct clk_pll14xx *pll = to_clk_pll14xx(hw);
   137		u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
   138		short int kdiv;
   139		u64 fvco = parent_rate;
   140	
   141		pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0);
   142		pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1);
   143		mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0);
   144		pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0);
   145		sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0);
   146		kdiv = FIELD_GET(KDIV_MASK, pll_div_ctl1);
   147	
   148		/* fvco = (m * 65536 + k) * Fin / (p * 65536) */
   149		fvco *= (mdiv * 65536 + kdiv);
   150		pdiv *= 65536;
   151	
   152		do_div(fvco, pdiv << sdiv);
   153	
   154		return fvco;
   155	}
   156	
   157	static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate,
   158						  u32 pll_div)
   159	{
   160		u32 old_mdiv, old_pdiv;
   161	
   162		old_mdiv = FIELD_GET(MDIV_MASK, pll_div);
   163		old_pdiv = FIELD_GET(PDIV_MASK, pll_div);
   164	
   165		return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
   166	}
   167	
   168	static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
   169	{
   170		u32 val;
   171	
   172		return readl_poll_timeout(pll->base + GNRL_CTL, val, val & LOCK_STATUS, 0,
   173				LOCK_TIMEOUT_US);
   174	}
   175	
   176	static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
   177					 unsigned long prate)
   178	{
   179		struct clk_pll14xx *pll = to_clk_pll14xx(hw);
   180		const struct imx_pll14xx_rate_table *rate;
   181		u32 tmp, div_val;
   182		int ret;
   183	
   184		rate = imx_get_pll_settings(pll, drate);
   185		if (!rate) {
   186			pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
   187			       drate, clk_hw_get_name(hw));
   188			return -EINVAL;
   189		}
   190	
   191		tmp = readl_relaxed(pll->base + DIV_CTL0);
   192	
   193		if (!clk_pll14xx_mp_change(rate, tmp)) {
   194			tmp &= ~SDIV_MASK;
 > 195			tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv);
   196			writel_relaxed(tmp, pll->base + DIV_CTL0);
   197	
   198			return 0;
   199		}
   200	
   201		/* Bypass clock and set lock to pll output lock */
   202		tmp = readl_relaxed(pll->base + GNRL_CTL);
   203		tmp |= LOCK_SEL_MASK;
   204		writel_relaxed(tmp, pll->base + GNRL_CTL);
   205	
   206		/* Enable RST */
   207		tmp &= ~RST_MASK;
   208		writel_relaxed(tmp, pll->base + GNRL_CTL);
   209	
   210		/* Enable BYPASS */
   211		tmp |= BYPASS_MASK;
   212		writel(tmp, pll->base + GNRL_CTL);
   213	
   214		div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) |
   215			FIELD_PREP(SDIV_MASK, rate->sdiv);
   216		writel_relaxed(div_val, pll->base + DIV_CTL0);
   217	
   218		/*
   219		 * According to SPEC, t3 - t2 need to be greater than
   220		 * 1us and 1/FREF, respectively.
   221		 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
   222		 * 3us.
   223		 */
   224		udelay(3);
   225	
   226		/* Disable RST */
   227		tmp |= RST_MASK;
   228		writel_relaxed(tmp, pll->base + GNRL_CTL);
   229	
   230		/* Wait Lock */
   231		ret = clk_pll14xx_wait_lock(pll);
   232		if (ret)
   233			return ret;
   234	
   235		/* Bypass */
   236		tmp &= ~BYPASS_MASK;
   237		writel_relaxed(tmp, pll->base + GNRL_CTL);
   238	
   239		return 0;
   240	}
   241	

---
0-DAY CI Kernel Test Service, Intel Corporation
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