From: Jacky Huang <ychuang3@nuvoton.com>
To: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <ychuang570808@gmail.com>
Cc: <robh+dt@kernel.org>, <sboyd@kernel.org>, <krzk+dt@kernel.org>,
<arnd@arndb.de>, <olof@lixom.net>, <will@kernel.org>,
<soc@kernel.org>, <cfli0@nuvoton.com>,
Jacky Huang <ychuang3@nuvoton.com>
Subject: [PATCH v3 2/5] dt-bindings: clock: Document MA35D1 clock controller bindings
Date: Mon, 18 Apr 2022 16:27:35 +0800 [thread overview]
Message-ID: <20220418082738.11301-3-ychuang3@nuvoton.com> (raw)
In-Reply-To: <20220418082738.11301-1-ychuang3@nuvoton.com>
Add documentation to describe Nuvoton MA35D1 clock driver bindings.
Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
---
.../bindings/clock/nuvoton,ma35d1-clk.yaml | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml
diff --git a/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml
new file mode 100644
index 000000000000..d0d37c5e84af
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 Clock Control Module Binding
+
+maintainers:
+ - Chi-Fang Li <cfli0@nuvoton.com>
+ - Jacky Huang <ychuang3@nuvoton.com>
+
+description: |
+ The MA35D1 clock controller generates clocks for the whole chip,
+ including system clocks and all peripheral clocks.
+
+ See also:
+ include/dt-bindings/clock/ma35d1-clk.h
+
+properties:
+ compatible:
+ const: nuvoton,ma35d1-clk
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ assigned-clocks:
+ minItems: 5
+ maxItems: 5
+
+ assigned-clock-rates:
+ minItems: 5
+ maxItems: 5
+
+ nuvoton,clk-pll-mode:
+ A list of PLL operation mode corresponding to DDRPLL, APLL, EPLL,
+ and VPLL in sequential.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 5
+ maxItems: 5
+ items:
+ enum: [ 0, 1, 2 ]
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+
+ clk: clock-controller@40460200 {
+ compatible = "nuvoton,ma35d1-clk";
+ reg = <0x0 0x40460200 0x0 0x100>;
+ #clock-cells = <1>;
+ };
+...
--
2.17.1
next prev parent reply other threads:[~2022-04-18 8:27 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-18 8:27 [PATCH v3 0/5] Add initial support for MA35D1 SoC Jacky Huang
2022-04-18 8:27 ` [PATCH v3 1/5] dt-bindings: clock: add binding for MA35D1 clock controller Jacky Huang
2022-04-18 12:09 ` Krzysztof Kozlowski
2022-04-18 8:27 ` Jacky Huang [this message]
2022-04-18 12:18 ` [PATCH v3 2/5] dt-bindings: clock: Document MA35D1 clock controller bindings Krzysztof Kozlowski
2022-04-19 10:12 ` Jacky Huang
2022-04-19 10:39 ` Krzysztof Kozlowski
2022-04-19 10:49 ` Jacky Huang
2022-04-18 13:35 ` Rob Herring
2022-04-19 8:49 ` Jacky Huang
2022-04-18 8:27 ` [PATCH v3 3/5] arm64: dts: nuvoton: Add initial support for MA35D1 Jacky Huang
2022-04-18 12:20 ` Krzysztof Kozlowski
2022-04-21 6:41 ` Jacky Huang
2022-04-18 8:27 ` [PATCH v3 4/5] arm64: Kconfig: nuvoton: Introduce CONFIG_ARCH_NUVOTON Jacky Huang
2022-04-18 8:27 ` [PATCH v3 5/5] dt-bindings: arm: Add initial bindings for Nuvoton Platform Jacky Huang
2022-04-18 12:11 ` Krzysztof Kozlowski
2022-04-21 6:39 ` Jacky Huang
2022-04-21 6:56 ` Krzysztof Kozlowski
2022-04-21 8:04 ` Jacky Huang
2022-04-21 8:05 ` Krzysztof Kozlowski
2022-04-21 8:13 ` Jacky Huang
2022-04-21 8:33 ` Krzysztof Kozlowski
2022-04-26 0:19 ` Rob Herring
2022-04-26 0:47 ` Jacky Huang
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