* [PATCH 0/9] Add Renesas RZ/V2M Ethernet support @ 2022-05-04 14:54 Phil Edworthy 2022-05-04 14:54 ` [PATCH 1/9] clk: renesas: r9a09g011: Add eth clock and reset entries Phil Edworthy 2022-05-05 0:57 ` [PATCH 0/9] Add Renesas RZ/V2M Ethernet support Jakub Kicinski 0 siblings, 2 replies; 6+ messages in thread From: Phil Edworthy @ 2022-05-04 14:54 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni, Geert Uytterhoeven Cc: Phil Edworthy, Sergey Shtylyov, Sergei Shtylyov, Biju Das, Lad Prabhakar, Chris Paterson, Magnus Damm, linux-clk, netdev, devicetree, linux-renesas-soc The RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though some small parts are the same as R-Car Gen2. Other differences are: * It has separate data (DI), error (Line 1) and management (Line 2) irqs rather than one irq for all three. * Instead of using the High-speed peripheral bus clock for gPTP, it has a separate gPTP reference clock. The dts patches depend on v4 of the following patch set: "Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support" Phil Edworthy (9): clk: renesas: r9a09g011: Add eth clock and reset entries dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC ravb: Separate use of GIC reg for PTME from multi_irqs ravb: Separate handling of irq enable/disable regs into feature ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs ravb: Use separate clock for gPTP ravb: Add support for RZ/V2M arm64: dts: renesas: r9a09g011: Add ethernet nodes arm64: dts: renesas: rzv2m evk: Enable ethernet .../bindings/net/renesas,etheravb.yaml | 82 ++++++++++++----- .../boot/dts/renesas/r9a09g011-v2mevk2.dts | 14 +++ arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 51 +++++++++++ drivers/clk/renesas/r9a09g011-cpg.c | 14 +-- drivers/net/ethernet/renesas/ravb.h | 7 ++ drivers/net/ethernet/renesas/ravb_main.c | 89 +++++++++++++++++-- drivers/net/ethernet/renesas/ravb_ptp.c | 4 +- 7 files changed, 228 insertions(+), 33 deletions(-) -- 2.32.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/9] clk: renesas: r9a09g011: Add eth clock and reset entries 2022-05-04 14:54 [PATCH 0/9] Add Renesas RZ/V2M Ethernet support Phil Edworthy @ 2022-05-04 14:54 ` Phil Edworthy 2022-05-05 9:19 ` Geert Uytterhoeven 2022-05-05 0:57 ` [PATCH 0/9] Add Renesas RZ/V2M Ethernet support Jakub Kicinski 1 sibling, 1 reply; 6+ messages in thread From: Phil Edworthy @ 2022-05-04 14:54 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Geert Uytterhoeven Cc: Phil Edworthy, linux-renesas-soc, linux-clk, Biju Das Add ethernet clock/reset entries to CPG driver. Note that the AXI and CHI clocks are both enabled and disabled using the same register bit. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/clk/renesas/r9a09g011-cpg.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index 7f16a617dc8c..f0a958497f47 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -126,14 +126,18 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { }; static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { - DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5), - DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12), - DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), - DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), - DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), + DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5), + DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8), + DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), + DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9), + DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12), + DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), + DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), + DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), }; static const struct rzg2l_reset r9a09g011_resets[] = { + DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11), DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13), }; -- 2.32.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/9] clk: renesas: r9a09g011: Add eth clock and reset entries 2022-05-04 14:54 ` [PATCH 1/9] clk: renesas: r9a09g011: Add eth clock and reset entries Phil Edworthy @ 2022-05-05 9:19 ` Geert Uytterhoeven 0 siblings, 0 replies; 6+ messages in thread From: Geert Uytterhoeven @ 2022-05-05 9:19 UTC (permalink / raw) To: Phil Edworthy Cc: Michael Turquette, Stephen Boyd, Geert Uytterhoeven, Linux-Renesas, linux-clk, Biju Das On Wed, May 4, 2022 at 4:55 PM Phil Edworthy <phil.edworthy@renesas.com> wrote: > Add ethernet clock/reset entries to CPG driver. > > Note that the AXI and CHI clocks are both enabled and disabled using > the same register bit. > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.19. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/9] Add Renesas RZ/V2M Ethernet support 2022-05-04 14:54 [PATCH 0/9] Add Renesas RZ/V2M Ethernet support Phil Edworthy 2022-05-04 14:54 ` [PATCH 1/9] clk: renesas: r9a09g011: Add eth clock and reset entries Phil Edworthy @ 2022-05-05 0:57 ` Jakub Kicinski 2022-05-05 6:59 ` Geert Uytterhoeven 1 sibling, 1 reply; 6+ messages in thread From: Jakub Kicinski @ 2022-05-05 0:57 UTC (permalink / raw) To: Phil Edworthy Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, David S. Miller, Eric Dumazet, Paolo Abeni, Geert Uytterhoeven, Sergey Shtylyov, Sergei Shtylyov, Biju Das, Lad Prabhakar, Chris Paterson, Magnus Damm, linux-clk, netdev, devicetree, linux-renesas-soc On Wed, 4 May 2022 15:54:45 +0100 Phil Edworthy wrote: > The RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though > some small parts are the same as R-Car Gen2. > Other differences are: > * It has separate data (DI), error (Line 1) and management (Line 2) irqs > rather than one irq for all three. > * Instead of using the High-speed peripheral bus clock for gPTP, it has > a separate gPTP reference clock. > > The dts patches depend on v4 of the following patch set: > "Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support" > > Phil Edworthy (9): > clk: renesas: r9a09g011: Add eth clock and reset entries > dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC > ravb: Separate use of GIC reg for PTME from multi_irqs > ravb: Separate handling of irq enable/disable regs into feature > ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs > ravb: Use separate clock for gPTP > ravb: Add support for RZ/V2M > arm64: dts: renesas: r9a09g011: Add ethernet nodes > arm64: dts: renesas: rzv2m evk: Enable ethernet How are you expecting this to be merged? I think you should drop the first (clk) patch from this series so we can apply the series to net-next. And route the clk patch thru Geert's tree separately? Right now patchwork thinks the series is incomplete because it hasn't received patch 1. ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/9] Add Renesas RZ/V2M Ethernet support 2022-05-05 0:57 ` [PATCH 0/9] Add Renesas RZ/V2M Ethernet support Jakub Kicinski @ 2022-05-05 6:59 ` Geert Uytterhoeven 2022-05-05 9:14 ` Phil Edworthy 0 siblings, 1 reply; 6+ messages in thread From: Geert Uytterhoeven @ 2022-05-05 6:59 UTC (permalink / raw) To: Jakub Kicinski Cc: Phil Edworthy, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, David S. Miller, Eric Dumazet, Paolo Abeni, Geert Uytterhoeven, Sergey Shtylyov, Sergei Shtylyov, Biju Das, Lad Prabhakar, Chris Paterson, Magnus Damm, linux-clk, netdev, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux-Renesas Hi Jakub, On Thu, May 5, 2022 at 2:58 AM Jakub Kicinski <kuba@kernel.org> wrote: > On Wed, 4 May 2022 15:54:45 +0100 Phil Edworthy wrote: > > The RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though > > some small parts are the same as R-Car Gen2. > > Other differences are: > > * It has separate data (DI), error (Line 1) and management (Line 2) irqs > > rather than one irq for all three. > > * Instead of using the High-speed peripheral bus clock for gPTP, it has > > a separate gPTP reference clock. > > > > The dts patches depend on v4 of the following patch set: > > "Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support" > > > > Phil Edworthy (9): > > clk: renesas: r9a09g011: Add eth clock and reset entries > > dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC > > ravb: Separate use of GIC reg for PTME from multi_irqs > > ravb: Separate handling of irq enable/disable regs into feature > > ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs > > ravb: Use separate clock for gPTP > > ravb: Add support for RZ/V2M > > arm64: dts: renesas: r9a09g011: Add ethernet nodes > > arm64: dts: renesas: rzv2m evk: Enable ethernet > > How are you expecting this to be merged? > > I think you should drop the first (clk) patch from this series > so we can apply the series to net-next. And route the clk patch > thru Geert's tree separately? Same for the last two DTS patches, they should go through the renesas-devel and SoC trees. > Right now patchwork thinks the series is incomplete because it > hasn't received patch 1. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 0/9] Add Renesas RZ/V2M Ethernet support 2022-05-05 6:59 ` Geert Uytterhoeven @ 2022-05-05 9:14 ` Phil Edworthy 0 siblings, 0 replies; 6+ messages in thread From: Phil Edworthy @ 2022-05-05 9:14 UTC (permalink / raw) To: Geert Uytterhoeven, Jakub Kicinski Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, David S. Miller, Eric Dumazet, Paolo Abeni, Geert Uytterhoeven, Sergey Shtylyov, Sergei Shtylyov, Biju Das, Prabhakar Mahadev Lad, Chris Paterson, Magnus Damm, linux-clk, netdev, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Linux-Renesas Hi Jakub, Geert, On 05 May 2022 07:59 Geert Uytterhoeven wrote: > On Thu, May 5, 2022 at 2:58 AM Jakub Kicinski wrote: > > On Wed, 4 May 2022 15:54:45 +0100 Phil Edworthy wrote: > > > The RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, > > > though some small parts are the same as R-Car Gen2. > > > Other differences are: > > > * It has separate data (DI), error (Line 1) and management (Line 2) > irqs > > > rather than one irq for all three. > > > * Instead of using the High-speed peripheral bus clock for gPTP, it > has > > > a separate gPTP reference clock. > > > > > > The dts patches depend on v4 of the following patch set: > > > "Add new Renesas RZ/V2M SoC and Renesas RZ/V2M EVK support" > > > > > > Phil Edworthy (9): > > > clk: renesas: r9a09g011: Add eth clock and reset entries > > > dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC > > > ravb: Separate use of GIC reg for PTME from multi_irqs > > > ravb: Separate handling of irq enable/disable regs into feature > > > ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) > irqs > > > ravb: Use separate clock for gPTP > > > ravb: Add support for RZ/V2M > > > arm64: dts: renesas: r9a09g011: Add ethernet nodes > > > arm64: dts: renesas: rzv2m evk: Enable ethernet > > > > How are you expecting this to be merged? > > > > I think you should drop the first (clk) patch from this series so we > > can apply the series to net-next. And route the clk patch thru Geert's > > tree separately? > > Same for the last two DTS patches, they should go through the renesas- > devel and SoC trees. Sorry, I mistakenly assumed this was all going via Geert's tree, but of course it's not. I'll split the series in two. > > Right now patchwork thinks the series is incomplete because it hasn't > > received patch 1. Thanks Phil ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-05-05 9:19 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-05-04 14:54 [PATCH 0/9] Add Renesas RZ/V2M Ethernet support Phil Edworthy 2022-05-04 14:54 ` [PATCH 1/9] clk: renesas: r9a09g011: Add eth clock and reset entries Phil Edworthy 2022-05-05 9:19 ` Geert Uytterhoeven 2022-05-05 0:57 ` [PATCH 0/9] Add Renesas RZ/V2M Ethernet support Jakub Kicinski 2022-05-05 6:59 ` Geert Uytterhoeven 2022-05-05 9:14 ` Phil Edworthy
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