* [PATCH 07/17] dt-bindings: clock: mpfs-ccc: Add PIC64GX compatibility
[not found] <20240725121609.13101-1-pierre-henry.moussay@microchip.com>
@ 2024-07-25 12:15 ` pierre-henry.moussay
2024-07-25 14:19 ` Conor Dooley
2024-07-25 12:16 ` [PATCH 08/17] dt-bindings: clock: mpfs-clkcfg: " pierre-henry.moussay
2024-07-25 12:16 ` [PATCH 15/17] dt-bindings: clk: microchip: Add Microchip PIC64GX host binding pierre-henry.moussay
2 siblings, 1 reply; 6+ messages in thread
From: pierre-henry.moussay @ 2024-07-25 12:15 UTC (permalink / raw)
To: Conor Dooley, Daire McNamara, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski
Cc: Pierre-Henry Moussay, linux-riscv, linux-clk, devicetree,
linux-kernel
From: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
PIC64GX SoC has clock compatibles with the MPFS IP
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
---
.../devicetree/bindings/clock/microchip,mpfs-ccc.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
index f1770360798f..9a6b50527c42 100644
--- a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
+++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
@@ -17,7 +17,11 @@ description: |
properties:
compatible:
- const: microchip,mpfs-ccc
+ oneOf:
+ - items:
+ - const: microchip,pic64gx-ccc
+ - const: microchip,mpfs-ccc
+ - const: microchip,mpfs-ccc
reg:
items:
--
2.30.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 08/17] dt-bindings: clock: mpfs-clkcfg: Add PIC64GX compatibility
[not found] <20240725121609.13101-1-pierre-henry.moussay@microchip.com>
2024-07-25 12:15 ` [PATCH 07/17] dt-bindings: clock: mpfs-ccc: Add PIC64GX compatibility pierre-henry.moussay
@ 2024-07-25 12:16 ` pierre-henry.moussay
2024-07-25 14:22 ` Conor Dooley
2024-07-25 12:16 ` [PATCH 15/17] dt-bindings: clk: microchip: Add Microchip PIC64GX host binding pierre-henry.moussay
2 siblings, 1 reply; 6+ messages in thread
From: pierre-henry.moussay @ 2024-07-25 12:16 UTC (permalink / raw)
To: Conor Dooley, Daire McNamara, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski
Cc: Pierre-Henry Moussay, linux-riscv, linux-clk, devicetree,
linux-kernel
From: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
PIC64GX has a clock controller compatible whith mpfs-clkcfg
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
---
.../devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
index e4e1c31267d2..ca889f5df87a 100644
--- a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
+++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
@@ -19,7 +19,11 @@ description: |
properties:
compatible:
- const: microchip,mpfs-clkcfg
+ oneOf:
+ - items:
+ - const: microchip,pic64gx-clkcfg
+ - const: microchip,mpfs-clkcfg
+ - const: microchip,mpfs-clkcfg
reg:
items:
--
2.30.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 15/17] dt-bindings: clk: microchip: Add Microchip PIC64GX host binding
[not found] <20240725121609.13101-1-pierre-henry.moussay@microchip.com>
2024-07-25 12:15 ` [PATCH 07/17] dt-bindings: clock: mpfs-ccc: Add PIC64GX compatibility pierre-henry.moussay
2024-07-25 12:16 ` [PATCH 08/17] dt-bindings: clock: mpfs-clkcfg: " pierre-henry.moussay
@ 2024-07-25 12:16 ` pierre-henry.moussay
2024-07-25 14:18 ` Conor Dooley
2 siblings, 1 reply; 6+ messages in thread
From: pierre-henry.moussay @ 2024-07-25 12:16 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pierre-Henry Moussay, linux-kernel, linux-clk, devicetree
From: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Add device tree bindings for the Microchip PIC64GX system
clock controller
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
---
.../clock/microchip,pic64gx-clock.h | 76 +++++++++++++++++++
1 file changed, 76 insertions(+)
create mode 100644 include/dt-bindings/clock/microchip,pic64gx-clock.h
diff --git a/include/dt-bindings/clock/microchip,pic64gx-clock.h b/include/dt-bindings/clock/microchip,pic64gx-clock.h
new file mode 100644
index 000000000000..91687c9da516
--- /dev/null
+++ b/include/dt-bindings/clock/microchip,pic64gx-clock.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Daire McNamara,<daire.mcnamara@microchip.com>
+ * Copyright (C) 2024 Microchip Technology Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC64GX_H_
+#define _DT_BINDINGS_CLK_MICROCHIP_PIC64GX_H_
+
+#define CLK_CPU 0
+#define CLK_AXI 1
+#define CLK_AHB 2
+
+#define CLK_ENVM 3
+#define CLK_MAC0 4
+#define CLK_MAC1 5
+#define CLK_MMC 6
+#define CLK_TIMER 7
+#define CLK_MMUART0 8
+#define CLK_MMUART1 9
+#define CLK_MMUART2 10
+#define CLK_MMUART3 11
+#define CLK_MMUART4 12
+#define CLK_SPI0 13
+#define CLK_SPI1 14
+#define CLK_I2C0 15
+#define CLK_I2C1 16
+#define CLK_CAN0 17
+#define CLK_CAN1 18
+#define CLK_USB 19
+#define CLK_RESERVED 20
+#define CLK_RTC 21
+#define CLK_QSPI 22
+#define CLK_GPIO0 23
+#define CLK_GPIO1 24
+#define CLK_GPIO2 25
+#define CLK_DDRC 26
+#define CLK_FIC0 27
+#define CLK_FIC1 28
+#define CLK_FIC2 29
+#define CLK_FIC3 30
+#define CLK_ATHENA 31
+#define CLK_CFM 32
+
+#define CLK_RTCREF 33
+#define CLK_MSSPLL 34
+#define CLK_MSSPLL0 34
+#define CLK_MSSPLL1 35
+#define CLK_MSSPLL2 36
+#define CLK_MSSPLL3 37
+/* 38 is reserved for MSS PLL internals */
+
+/* Clock Conditioning Circuitry Clock IDs */
+
+#define CLK_CCC_PLL0 0
+#define CLK_CCC_PLL1 1
+#define CLK_CCC_DLL0 2
+#define CLK_CCC_DLL1 3
+
+#define CLK_CCC_PLL0_OUT0 4
+#define CLK_CCC_PLL0_OUT1 5
+#define CLK_CCC_PLL0_OUT2 6
+#define CLK_CCC_PLL0_OUT3 7
+
+#define CLK_CCC_PLL1_OUT0 8
+#define CLK_CCC_PLL1_OUT1 9
+#define CLK_CCC_PLL1_OUT2 10
+#define CLK_CCC_PLL1_OUT3 11
+
+#define CLK_CCC_DLL0_OUT0 12
+#define CLK_CCC_DLL0_OUT1 13
+
+#define CLK_CCC_DLL1_OUT0 14
+#define CLK_CCC_DLL1_OUT1 15
+
+#endif /* _DT_BINDINGS_CLK_MICROCHIP_PIC64GX_H_ */
--
2.30.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 15/17] dt-bindings: clk: microchip: Add Microchip PIC64GX host binding
2024-07-25 12:16 ` [PATCH 15/17] dt-bindings: clk: microchip: Add Microchip PIC64GX host binding pierre-henry.moussay
@ 2024-07-25 14:18 ` Conor Dooley
0 siblings, 0 replies; 6+ messages in thread
From: Conor Dooley @ 2024-07-25 14:18 UTC (permalink / raw)
To: pierre-henry.moussay
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-kernel, linux-clk, devicetree
[-- Attachment #1: Type: text/plain, Size: 2913 bytes --]
On Thu, Jul 25, 2024 at 01:16:07PM +0100, pierre-henry.moussay@microchip.com wrote:
> From: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
>
> Add device tree bindings for the Microchip PIC64GX system
> clock controller
>
> Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
I don't see a point in duplicating this header from mpfs. The defines
are all identical.
Cheers,
Conor.
> ---
> .../clock/microchip,pic64gx-clock.h | 76 +++++++++++++++++++
> 1 file changed, 76 insertions(+)
> create mode 100644 include/dt-bindings/clock/microchip,pic64gx-clock.h
>
> diff --git a/include/dt-bindings/clock/microchip,pic64gx-clock.h b/include/dt-bindings/clock/microchip,pic64gx-clock.h
> new file mode 100644
> index 000000000000..91687c9da516
> --- /dev/null
> +++ b/include/dt-bindings/clock/microchip,pic64gx-clock.h
> @@ -0,0 +1,76 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Daire McNamara,<daire.mcnamara@microchip.com>
> + * Copyright (C) 2024 Microchip Technology Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC64GX_H_
> +#define _DT_BINDINGS_CLK_MICROCHIP_PIC64GX_H_
> +
> +#define CLK_CPU 0
> +#define CLK_AXI 1
> +#define CLK_AHB 2
> +
> +#define CLK_ENVM 3
> +#define CLK_MAC0 4
> +#define CLK_MAC1 5
> +#define CLK_MMC 6
> +#define CLK_TIMER 7
> +#define CLK_MMUART0 8
> +#define CLK_MMUART1 9
> +#define CLK_MMUART2 10
> +#define CLK_MMUART3 11
> +#define CLK_MMUART4 12
> +#define CLK_SPI0 13
> +#define CLK_SPI1 14
> +#define CLK_I2C0 15
> +#define CLK_I2C1 16
> +#define CLK_CAN0 17
> +#define CLK_CAN1 18
> +#define CLK_USB 19
> +#define CLK_RESERVED 20
> +#define CLK_RTC 21
> +#define CLK_QSPI 22
> +#define CLK_GPIO0 23
> +#define CLK_GPIO1 24
> +#define CLK_GPIO2 25
> +#define CLK_DDRC 26
> +#define CLK_FIC0 27
> +#define CLK_FIC1 28
> +#define CLK_FIC2 29
> +#define CLK_FIC3 30
> +#define CLK_ATHENA 31
> +#define CLK_CFM 32
> +
> +#define CLK_RTCREF 33
> +#define CLK_MSSPLL 34
> +#define CLK_MSSPLL0 34
> +#define CLK_MSSPLL1 35
> +#define CLK_MSSPLL2 36
> +#define CLK_MSSPLL3 37
> +/* 38 is reserved for MSS PLL internals */
> +
> +/* Clock Conditioning Circuitry Clock IDs */
> +
> +#define CLK_CCC_PLL0 0
> +#define CLK_CCC_PLL1 1
> +#define CLK_CCC_DLL0 2
> +#define CLK_CCC_DLL1 3
> +
> +#define CLK_CCC_PLL0_OUT0 4
> +#define CLK_CCC_PLL0_OUT1 5
> +#define CLK_CCC_PLL0_OUT2 6
> +#define CLK_CCC_PLL0_OUT3 7
> +
> +#define CLK_CCC_PLL1_OUT0 8
> +#define CLK_CCC_PLL1_OUT1 9
> +#define CLK_CCC_PLL1_OUT2 10
> +#define CLK_CCC_PLL1_OUT3 11
> +
> +#define CLK_CCC_DLL0_OUT0 12
> +#define CLK_CCC_DLL0_OUT1 13
> +
> +#define CLK_CCC_DLL1_OUT0 14
> +#define CLK_CCC_DLL1_OUT1 15
> +
> +#endif /* _DT_BINDINGS_CLK_MICROCHIP_PIC64GX_H_ */
> --
> 2.30.2
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 07/17] dt-bindings: clock: mpfs-ccc: Add PIC64GX compatibility
2024-07-25 12:15 ` [PATCH 07/17] dt-bindings: clock: mpfs-ccc: Add PIC64GX compatibility pierre-henry.moussay
@ 2024-07-25 14:19 ` Conor Dooley
0 siblings, 0 replies; 6+ messages in thread
From: Conor Dooley @ 2024-07-25 14:19 UTC (permalink / raw)
To: pierre-henry.moussay
Cc: Conor Dooley, Daire McNamara, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, linux-riscv, linux-clk,
devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1469 bytes --]
On Thu, Jul 25, 2024 at 01:15:59PM +0100, pierre-henry.moussay@microchip.com wrote:
> From: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
>
> PIC64GX SoC has clock compatibles with the MPFS IP
These commit messages don't really make sense. It should read something
like "The pic64gx SoC has has Clock Conditioning Circuitry compatible
with that on PolarFire SoC" or something along those lines.
>
> Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
> ---
> .../devicetree/bindings/clock/microchip,mpfs-ccc.yaml | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
> index f1770360798f..9a6b50527c42 100644
> --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
> +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
> @@ -17,7 +17,11 @@ description: |
>
> properties:
> compatible:
> - const: microchip,mpfs-ccc
> + oneOf:
> + - items:
> + - const: microchip,pic64gx-ccc
> + - const: microchip,mpfs-ccc
> + - const: microchip,mpfs-ccc
>
> reg:
> items:
> --
> 2.30.2
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 08/17] dt-bindings: clock: mpfs-clkcfg: Add PIC64GX compatibility
2024-07-25 12:16 ` [PATCH 08/17] dt-bindings: clock: mpfs-clkcfg: " pierre-henry.moussay
@ 2024-07-25 14:22 ` Conor Dooley
0 siblings, 0 replies; 6+ messages in thread
From: Conor Dooley @ 2024-07-25 14:22 UTC (permalink / raw)
To: pierre-henry.moussay
Cc: Conor Dooley, Daire McNamara, Michael Turquette, Stephen Boyd,
Rob Herring, Krzysztof Kozlowski, linux-riscv, linux-clk,
devicetree, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1577 bytes --]
On Thu, Jul 25, 2024 at 01:16:00PM +0100, pierre-henry.moussay@microchip.com wrote:
> From: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
>
> PIC64GX has a clock controller compatible whith mpfs-clkcfg
>
> Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
> ---
> .../devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
> index e4e1c31267d2..ca889f5df87a 100644
> --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
> +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
> @@ -19,7 +19,11 @@ description: |
>
> properties:
> compatible:
> - const: microchip,mpfs-clkcfg
> + oneOf:
> + - items:
> + - const: microchip,pic64gx-clkcfg
> + - const: microchip,mpfs-clkcfg
> + - const: microchip,mpfs-clkcfg
Ditto here, the mpfs binding is wrong and I don't want the pic64gx to
ape that. Instead, we should take the opportunity to fix the binding.
You're gonna need to do that so that the pinctrl driver can access the
IOMUX registers correctly. As with the mailbox, either simplemfd or
syscon are needed here. I mocked something up a few weeks ago while
talking to someone about a hwmon driver, I'll dig it up when I am back
to work.
Cheers,
Conor.
>
> reg:
> items:
> --
> 2.30.2
>
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
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[not found] <20240725121609.13101-1-pierre-henry.moussay@microchip.com>
2024-07-25 12:15 ` [PATCH 07/17] dt-bindings: clock: mpfs-ccc: Add PIC64GX compatibility pierre-henry.moussay
2024-07-25 14:19 ` Conor Dooley
2024-07-25 12:16 ` [PATCH 08/17] dt-bindings: clock: mpfs-clkcfg: " pierre-henry.moussay
2024-07-25 14:22 ` Conor Dooley
2024-07-25 12:16 ` [PATCH 15/17] dt-bindings: clk: microchip: Add Microchip PIC64GX host binding pierre-henry.moussay
2024-07-25 14:18 ` Conor Dooley
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