* [PATCH] clk: sophgo: Cast an operand to u64 to prevent potential unsigned long overflow on 32-bit machine in sg2042_pll_recalc_rate()
@ 2024-10-21 20:51 Gax-c
2024-10-22 0:18 ` Chen Wang
2024-10-22 7:58 ` Dan Carpenter
0 siblings, 2 replies; 5+ messages in thread
From: Gax-c @ 2024-10-21 20:51 UTC (permalink / raw)
To: mturquette, sboyd, unicorn_wang, inochiama, dan.carpenter, nathan
Cc: linux-clk, zzjas98, chenyuan0y, Zichen Xie
From: Zichen Xie <zichenxie0106@gmail.com>
This was found by a static analyzer.
There may be a potential integer overflow issue in
sg2042_pll_recalc_rate(). numerator is defined as u64 while
parent_rate is defined as unsigned long and ctrl_table.fbdiv
is defined as unsigned int. On 32-bit machine, the result of
the calculation will be limited to "u32" without correct casting.
Integer overflow may occur on high-performance systems.
For the same reason, adding a cast to denominator could be better.
So, we recommend adding an extra cast to prevent potential
integer overflow.
Fixes: 48cf7e01386e ("clk: sophgo: Add SG2042 clock driver")
Signed-off-by: Zichen Xie <zichenxie0106@gmail.com>
---
drivers/clk/sophgo/clk-sg2042-pll.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sophgo/clk-sg2042-pll.c b/drivers/clk/sophgo/clk-sg2042-pll.c
index ff9deeef509b..e0f92f7a21bd 100644
--- a/drivers/clk/sophgo/clk-sg2042-pll.c
+++ b/drivers/clk/sophgo/clk-sg2042-pll.c
@@ -153,8 +153,8 @@ static unsigned long sg2042_pll_recalc_rate(unsigned int reg_value,
sg2042_pll_ctrl_decode(reg_value, &ctrl_table);
- numerator = parent_rate * ctrl_table.fbdiv;
- denominator = ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
+ numerator = (u64)parent_rate * ctrl_table.fbdiv;
+ denominator = (u64)ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
do_div(numerator, denominator);
return numerator;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] clk: sophgo: Cast an operand to u64 to prevent potential unsigned long overflow on 32-bit machine in sg2042_pll_recalc_rate()
2024-10-21 20:51 [PATCH] clk: sophgo: Cast an operand to u64 to prevent potential unsigned long overflow on 32-bit machine in sg2042_pll_recalc_rate() Gax-c
@ 2024-10-22 0:18 ` Chen Wang
2024-10-22 7:58 ` Dan Carpenter
1 sibling, 0 replies; 5+ messages in thread
From: Chen Wang @ 2024-10-22 0:18 UTC (permalink / raw)
To: Gax-c, mturquette, sboyd, inochiama, dan.carpenter, nathan
Cc: linux-clk, zzjas98, chenyuan0y
On 2024/10/22 4:51, Gax-c wrote:
> From: Zichen Xie <zichenxie0106@gmail.com>
>
> This was found by a static analyzer.
> There may be a potential integer overflow issue in
> sg2042_pll_recalc_rate(). numerator is defined as u64 while
> parent_rate is defined as unsigned long and ctrl_table.fbdiv
> is defined as unsigned int. On 32-bit machine, the result of
> the calculation will be limited to "u32" without correct casting.
> Integer overflow may occur on high-performance systems.
> For the same reason, adding a cast to denominator could be better.
> So, we recommend adding an extra cast to prevent potential
> integer overflow.
>
> Fixes: 48cf7e01386e ("clk: sophgo: Add SG2042 clock driver")
> Signed-off-by: Zichen Xie <zichenxie0106@gmail.com>
> ---
> drivers/clk/sophgo/clk-sg2042-pll.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/sophgo/clk-sg2042-pll.c b/drivers/clk/sophgo/clk-sg2042-pll.c
> index ff9deeef509b..e0f92f7a21bd 100644
> --- a/drivers/clk/sophgo/clk-sg2042-pll.c
> +++ b/drivers/clk/sophgo/clk-sg2042-pll.c
> @@ -153,8 +153,8 @@ static unsigned long sg2042_pll_recalc_rate(unsigned int reg_value,
>
> sg2042_pll_ctrl_decode(reg_value, &ctrl_table);
>
> - numerator = parent_rate * ctrl_table.fbdiv;
> - denominator = ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
> + numerator = (u64)parent_rate * ctrl_table.fbdiv;
> + denominator = (u64)ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
> do_div(numerator, denominator);
> return numerator;
> }
LGTM, thanks.
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] clk: sophgo: Cast an operand to u64 to prevent potential unsigned long overflow on 32-bit machine in sg2042_pll_recalc_rate()
2024-10-21 20:51 [PATCH] clk: sophgo: Cast an operand to u64 to prevent potential unsigned long overflow on 32-bit machine in sg2042_pll_recalc_rate() Gax-c
2024-10-22 0:18 ` Chen Wang
@ 2024-10-22 7:58 ` Dan Carpenter
2024-10-22 15:39 ` Zichen Xie
1 sibling, 1 reply; 5+ messages in thread
From: Dan Carpenter @ 2024-10-22 7:58 UTC (permalink / raw)
To: Gax-c
Cc: mturquette, sboyd, unicorn_wang, inochiama, nathan, linux-clk,
zzjas98, chenyuan0y
On Mon, Oct 21, 2024 at 03:51:02PM -0500, Gax-c wrote:
> From: Zichen Xie <zichenxie0106@gmail.com>
>
> This was found by a static analyzer.
> There may be a potential integer overflow issue in
> sg2042_pll_recalc_rate(). numerator is defined as u64 while
> parent_rate is defined as unsigned long and ctrl_table.fbdiv
> is defined as unsigned int. On 32-bit machine, the result of
> the calculation will be limited to "u32" without correct casting.
> Integer overflow may occur on high-performance systems.
> For the same reason, adding a cast to denominator could be better.
> So, we recommend adding an extra cast to prevent potential
> integer overflow.
>
> Fixes: 48cf7e01386e ("clk: sophgo: Add SG2042 clock driver")
> Signed-off-by: Zichen Xie <zichenxie0106@gmail.com>
> ---
> drivers/clk/sophgo/clk-sg2042-pll.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/sophgo/clk-sg2042-pll.c b/drivers/clk/sophgo/clk-sg2042-pll.c
> index ff9deeef509b..e0f92f7a21bd 100644
> --- a/drivers/clk/sophgo/clk-sg2042-pll.c
> +++ b/drivers/clk/sophgo/clk-sg2042-pll.c
> @@ -153,8 +153,8 @@ static unsigned long sg2042_pll_recalc_rate(unsigned int reg_value,
>
> sg2042_pll_ctrl_decode(reg_value, &ctrl_table);
^^^^^^^^^^^
>
> - numerator = parent_rate * ctrl_table.fbdiv;
> - denominator = ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
> + numerator = (u64)parent_rate * ctrl_table.fbdiv;
This seems reasonable.
> + denominator = (u64)ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
These values from sg2042_pll_ctrl_decode() and there is no way they can
overflow. The highest they can be is 63 * 7 * 7 = 3087.
regards,
dan carpenter
> do_div(numerator, denominator);
> return numerator;
> }
> --
> 2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] clk: sophgo: Cast an operand to u64 to prevent potential unsigned long overflow on 32-bit machine in sg2042_pll_recalc_rate()
2024-10-22 7:58 ` Dan Carpenter
@ 2024-10-22 15:39 ` Zichen Xie
2024-10-22 18:11 ` Dan Carpenter
0 siblings, 1 reply; 5+ messages in thread
From: Zichen Xie @ 2024-10-22 15:39 UTC (permalink / raw)
To: Dan Carpenter
Cc: mturquette, sboyd, unicorn_wang, inochiama, nathan, linux-clk,
zzjas98, chenyuan0y
On 2024/10/22 2:58, Dan Carpenter wrote:
> On Mon, Oct 21, 2024 at 03:51:02PM -0500, Gax-c wrote:
>> From: Zichen Xie <zichenxie0106@gmail.com>
>>
>> This was found by a static analyzer.
>> There may be a potential integer overflow issue in
>> sg2042_pll_recalc_rate(). numerator is defined as u64 while
>> parent_rate is defined as unsigned long and ctrl_table.fbdiv
>> is defined as unsigned int. On 32-bit machine, the result of
>> the calculation will be limited to "u32" without correct casting.
>> Integer overflow may occur on high-performance systems.
>> For the same reason, adding a cast to denominator could be better.
>> So, we recommend adding an extra cast to prevent potential
>> integer overflow.
>>
>> Fixes: 48cf7e01386e ("clk: sophgo: Add SG2042 clock driver")
>> Signed-off-by: Zichen Xie <zichenxie0106@gmail.com>
>> ---
>> drivers/clk/sophgo/clk-sg2042-pll.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/sophgo/clk-sg2042-pll.c b/drivers/clk/sophgo/clk-sg2042-pll.c
>> index ff9deeef509b..e0f92f7a21bd 100644
>> --- a/drivers/clk/sophgo/clk-sg2042-pll.c
>> +++ b/drivers/clk/sophgo/clk-sg2042-pll.c
>> @@ -153,8 +153,8 @@ static unsigned long sg2042_pll_recalc_rate(unsigned int reg_value,
>>
>> sg2042_pll_ctrl_decode(reg_value, &ctrl_table);
> ^^^^^^^^^^^
>>
>> - numerator = parent_rate * ctrl_table.fbdiv;
>> - denominator = ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
>> + numerator = (u64)parent_rate * ctrl_table.fbdiv;
> This seems reasonable.
>
>> + denominator = (u64)ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
> These values from sg2042_pll_ctrl_decode() and there is no way they can
> overflow. The highest they can be is 63 * 7 * 7 = 3087.
You are right. But I think it could be better to add this cast to
demonstrate that
developers have realized the potential of integer overflow.
And it can also prevent some static analyzers from reporting such bugs.
Anyway, I can still provide a patch with "numerator" cast only if it's
better.
Best,
Zichen
>
> regards,
> dan carpenter
>
>> do_div(numerator, denominator);
>> return numerator;
>> }
>> --
>> 2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] clk: sophgo: Cast an operand to u64 to prevent potential unsigned long overflow on 32-bit machine in sg2042_pll_recalc_rate()
2024-10-22 15:39 ` Zichen Xie
@ 2024-10-22 18:11 ` Dan Carpenter
0 siblings, 0 replies; 5+ messages in thread
From: Dan Carpenter @ 2024-10-22 18:11 UTC (permalink / raw)
To: Zichen Xie
Cc: mturquette, sboyd, unicorn_wang, inochiama, nathan, linux-clk,
zzjas98, chenyuan0y
On Tue, Oct 22, 2024 at 10:39:42AM -0500, Zichen Xie wrote:
>
> On 2024/10/22 2:58, Dan Carpenter wrote:
> > On Mon, Oct 21, 2024 at 03:51:02PM -0500, Gax-c wrote:
> > > From: Zichen Xie <zichenxie0106@gmail.com>
> > >
> > > This was found by a static analyzer.
> > > There may be a potential integer overflow issue in
> > > sg2042_pll_recalc_rate(). numerator is defined as u64 while
> > > parent_rate is defined as unsigned long and ctrl_table.fbdiv
> > > is defined as unsigned int. On 32-bit machine, the result of
> > > the calculation will be limited to "u32" without correct casting.
> > > Integer overflow may occur on high-performance systems.
> > > For the same reason, adding a cast to denominator could be better.
> > > So, we recommend adding an extra cast to prevent potential
> > > integer overflow.
> > >
> > > Fixes: 48cf7e01386e ("clk: sophgo: Add SG2042 clock driver")
> > > Signed-off-by: Zichen Xie <zichenxie0106@gmail.com>
> > > ---
> > > drivers/clk/sophgo/clk-sg2042-pll.c | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/clk/sophgo/clk-sg2042-pll.c b/drivers/clk/sophgo/clk-sg2042-pll.c
> > > index ff9deeef509b..e0f92f7a21bd 100644
> > > --- a/drivers/clk/sophgo/clk-sg2042-pll.c
> > > +++ b/drivers/clk/sophgo/clk-sg2042-pll.c
> > > @@ -153,8 +153,8 @@ static unsigned long sg2042_pll_recalc_rate(unsigned int reg_value,
> > > sg2042_pll_ctrl_decode(reg_value, &ctrl_table);
> > ^^^^^^^^^^^
> > > - numerator = parent_rate * ctrl_table.fbdiv;
> > > - denominator = ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
> > > + numerator = (u64)parent_rate * ctrl_table.fbdiv;
> > This seems reasonable.
> >
> > > + denominator = (u64)ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2;
> > These values from sg2042_pll_ctrl_decode() and there is no way they can
> > overflow. The highest they can be is 63 * 7 * 7 = 3087.
>
> You are right. But I think it could be better to add this cast to
> demonstrate that
> developers have realized the potential of integer overflow.
>
> And it can also prevent some static analyzers from reporting such bugs.
Pointless casting is just confusing and harmful. The static checker could be
fixed to parse that code correctly.
>
> Anyway, I can still provide a patch with "numerator" cast only if it's
> better.
>
Yes, please.
regards,
dan carpenter
^ permalink raw reply [flat|nested] 5+ messages in thread
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2024-10-21 20:51 [PATCH] clk: sophgo: Cast an operand to u64 to prevent potential unsigned long overflow on 32-bit machine in sg2042_pll_recalc_rate() Gax-c
2024-10-22 0:18 ` Chen Wang
2024-10-22 7:58 ` Dan Carpenter
2024-10-22 15:39 ` Zichen Xie
2024-10-22 18:11 ` Dan Carpenter
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