* [PATCH 2/4] clk: fsl-sai: Add i.MX8M Mini support with 8 byte register offset
2024-12-26 15:30 [PATCH 1/4] dt-bindings: clock: fsl-sai: Document i.MX8M support Marek Vasut
@ 2024-12-26 15:30 ` Marek Vasut
2024-12-26 16:20 ` Marek Vasut
2024-12-26 15:30 ` [PATCH 3/4] dt-bindings: clock: fsl-sai: Document clock-cells = <1> support Marek Vasut
2024-12-26 15:30 ` [PATCH 4/4] clk: fsl-sai: Add MCLK generation support Marek Vasut
2 siblings, 1 reply; 5+ messages in thread
From: Marek Vasut @ 2024-12-26 15:30 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Conor Dooley, Fabio Estevam, Jaroslav Kysela,
Krzysztof Kozlowski, Liam Girdwood, Mark Brown, Michael Turquette,
Michael Walle, Nicolin Chen, Rob Herring, Shengjiu Wang,
Stephen Boyd, Takashi Iwai, Xiubo Li, devicetree, linux-sound
The i.MX8M Mini/Nano/Plus variant of the SAI IP has control registers
shifted by +8 bytes, add support for the i.MX8M Mini variant of the IP
with this register shift.
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Shengjiu Wang <shengjiu.wang@gmail.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Takashi Iwai <tiwai@suse.com>
Cc: Xiubo Li <Xiubo.Lee@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-sound@vger.kernel.org
---
drivers/clk/Kconfig | 2 +-
drivers/clk/clk-fsl-sai.c | 22 ++++++++++++++++++----
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 713573b6c86c7..575743d7e2c71 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -247,7 +247,7 @@ config COMMON_CLK_FSL_FLEXSPI
config COMMON_CLK_FSL_SAI
bool "Clock driver for BCLK of Freescale SAI cores"
- depends on ARCH_LAYERSCAPE || COMPILE_TEST
+ depends on ARCH_LAYERSCAPE || ARCH_MXC || COMPILE_TEST
help
This driver supports the Freescale SAI (Synchronous Audio Interface)
to be used as a generic clock output. Some SoCs have restrictions
diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
index cba45e07562da..628e53a3a26fa 100644
--- a/drivers/clk/clk-fsl-sai.c
+++ b/drivers/clk/clk-fsl-sai.c
@@ -26,9 +26,14 @@ struct fsl_sai_clk {
spinlock_t lock;
};
+struct fsl_sai_data {
+ unsigned int offset; /* Register offset */
+};
+
static int fsl_sai_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
+ const struct fsl_sai_data *data = device_get_match_data(dev);
struct fsl_sai_clk *sai_clk;
struct clk_parent_data pdata = { .index = 0 };
void __iomem *base;
@@ -44,17 +49,17 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
spin_lock_init(&sai_clk->lock);
- sai_clk->gate.reg = base + I2S_CSR;
+ sai_clk->gate.reg = base + data->offset + I2S_CSR;
sai_clk->gate.bit_idx = CSR_BCE_BIT;
sai_clk->gate.lock = &sai_clk->lock;
- sai_clk->div.reg = base + I2S_CR2;
+ sai_clk->div.reg = base + data->offset + I2S_CR2;
sai_clk->div.shift = CR2_DIV_SHIFT;
sai_clk->div.width = CR2_DIV_WIDTH;
sai_clk->div.lock = &sai_clk->lock;
/* set clock direction, we are the BCLK master */
- writel(CR2_BCD, base + I2S_CR2);
+ writel(CR2_BCD, base + data->offset + I2S_CR2);
hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name,
&pdata, 1, NULL, NULL,
@@ -69,8 +74,17 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
}
+static const struct fsl_sai_data fsl_sai_vf610_data = {
+ .offset = 0,
+};
+
+static const struct fsl_sai_data fsl_sai_imx8mq_data = {
+ .offset = 8,
+};
+
static const struct of_device_id of_fsl_sai_clk_ids[] = {
- { .compatible = "fsl,vf610-sai-clock" },
+ { .compatible = "fsl,vf610-sai-clock", .data = &fsl_sai_vf610_data },
+ { .compatible = "fsl,imx8mq-sai-clock", .data = &fsl_sai_imx8mq_data },
{ }
};
MODULE_DEVICE_TABLE(of, of_fsl_sai_clk_ids);
--
2.45.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 2/4] clk: fsl-sai: Add i.MX8M Mini support with 8 byte register offset
2024-12-26 15:30 ` [PATCH 2/4] clk: fsl-sai: Add i.MX8M Mini support with 8 byte register offset Marek Vasut
@ 2024-12-26 16:20 ` Marek Vasut
0 siblings, 0 replies; 5+ messages in thread
From: Marek Vasut @ 2024-12-26 16:20 UTC (permalink / raw)
To: linux-clk
Cc: Conor Dooley, Fabio Estevam, Jaroslav Kysela, Krzysztof Kozlowski,
Liam Girdwood, Mark Brown, Michael Turquette, Michael Walle,
Nicolin Chen, Rob Herring, Shengjiu Wang, Stephen Boyd,
Takashi Iwai, Xiubo Li, devicetree, linux-sound
On 12/26/24 4:30 PM, Marek Vasut wrote:
> The i.MX8M Mini/Nano/Plus variant of the SAI IP has control registers
> shifted by +8 bytes, add support for the i.MX8M Mini variant of the IP
> with this register shift.
Ugh, V2 with updated commit message is coming.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 3/4] dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
2024-12-26 15:30 [PATCH 1/4] dt-bindings: clock: fsl-sai: Document i.MX8M support Marek Vasut
2024-12-26 15:30 ` [PATCH 2/4] clk: fsl-sai: Add i.MX8M Mini support with 8 byte register offset Marek Vasut
@ 2024-12-26 15:30 ` Marek Vasut
2024-12-26 15:30 ` [PATCH 4/4] clk: fsl-sai: Add MCLK generation support Marek Vasut
2 siblings, 0 replies; 5+ messages in thread
From: Marek Vasut @ 2024-12-26 15:30 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Conor Dooley, Fabio Estevam, Jaroslav Kysela,
Krzysztof Kozlowski, Liam Girdwood, Mark Brown, Michael Turquette,
Michael Walle, Nicolin Chen, Rob Herring, Shengjiu Wang,
Stephen Boyd, Takashi Iwai, Xiubo Li, devicetree, linux-sound
The driver now supports generation of both BCLK and MCLK, document
support for #clock-cells = <0> for legacy case and #clock-cells = <1>
for the new case which can differentiate between BCLK and MCLK.
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Shengjiu Wang <shengjiu.wang@gmail.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Takashi Iwai <tiwai@suse.com>
Cc: Xiubo Li <Xiubo.Lee@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-sound@vger.kernel.org
---
Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
index e62543deeb7da..250d7ec729c6e 100644
--- a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
@@ -10,7 +10,7 @@ maintainers:
- Michael Walle <michael@walle.cc>
description: |
- It is possible to use the BCLK pin of a SAI module as a generic
+ It is possible to use the BCLK or MCLK pin of a SAI module as a generic
clock output. Some SoC are very constrained in their pin multiplexer
configuration. E.g. pins can only be changed in groups. For example, on
the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
@@ -40,7 +40,7 @@ properties:
maxItems: 1
'#clock-cells':
- const: 0
+ maximum: 1
allOf:
- if:
--
2.45.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 4/4] clk: fsl-sai: Add MCLK generation support
2024-12-26 15:30 [PATCH 1/4] dt-bindings: clock: fsl-sai: Document i.MX8M support Marek Vasut
2024-12-26 15:30 ` [PATCH 2/4] clk: fsl-sai: Add i.MX8M Mini support with 8 byte register offset Marek Vasut
2024-12-26 15:30 ` [PATCH 3/4] dt-bindings: clock: fsl-sai: Document clock-cells = <1> support Marek Vasut
@ 2024-12-26 15:30 ` Marek Vasut
2 siblings, 0 replies; 5+ messages in thread
From: Marek Vasut @ 2024-12-26 15:30 UTC (permalink / raw)
To: linux-clk
Cc: Marek Vasut, Conor Dooley, Fabio Estevam, Jaroslav Kysela,
Krzysztof Kozlowski, Liam Girdwood, Mark Brown, Michael Turquette,
Michael Walle, Nicolin Chen, Rob Herring, Shengjiu Wang,
Stephen Boyd, Takashi Iwai, Xiubo Li, devicetree, linux-sound
The driver currently supports generating BCLK. There are systems which
require generation of MCLK instead. Register new MCLK clock and handle
clock-cells = <1> to differentiate between BCLK and MCLK. In case of a
legacy system with clock-cells = <0>, the driver behaves as before, i.e.
always returns BCLK.
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Shengjiu Wang <shengjiu.wang@gmail.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Takashi Iwai <tiwai@suse.com>
Cc: Xiubo Li <Xiubo.Lee@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-sound@vger.kernel.org
---
drivers/clk/clk-fsl-sai.c | 81 ++++++++++++++++++++++++++++++++-------
1 file changed, 67 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
index 628e53a3a26fa..0f8e2f2662d87 100644
--- a/drivers/clk/clk-fsl-sai.c
+++ b/drivers/clk/clk-fsl-sai.c
@@ -7,6 +7,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
+#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/of.h>
@@ -15,27 +16,44 @@
#define I2S_CSR 0x00
#define I2S_CR2 0x08
+#define I2S_MCR 0x100
#define CSR_BCE_BIT 28
+#define CSR_TE_BIT 31
#define CR2_BCD BIT(24)
#define CR2_DIV_SHIFT 0
#define CR2_DIV_WIDTH 8
+#define MCR_MOE BIT(30)
struct fsl_sai_clk {
- struct clk_divider div;
- struct clk_gate gate;
+ struct clk_divider bclk_div;
+ struct clk_divider mclk_div;
+ struct clk_gate bclk_gate;
+ struct clk_gate mclk_gate;
+ struct clk_hw *bclk_hw;
+ struct clk_hw *mclk_hw;
spinlock_t lock;
};
struct fsl_sai_data {
unsigned int offset; /* Register offset */
+ bool have_mclk; /* Have MCLK control */
};
+static struct clk_hw *
+fsl_sai_of_clk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct fsl_sai_clk *sai_clk = data;
+
+ return clkspec->args[0] ? sai_clk->mclk_hw : sai_clk->bclk_hw;
+}
+
static int fsl_sai_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct fsl_sai_data *data = device_get_match_data(dev);
- struct fsl_sai_clk *sai_clk;
struct clk_parent_data pdata = { .index = 0 };
+ struct fsl_sai_clk *sai_clk;
+ struct clk *clk_bus;
void __iomem *base;
struct clk_hw *hw;
@@ -47,39 +65,74 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
+ clk_bus = devm_clk_get_enabled(dev, "bus");
+ if (IS_ERR(clk_bus))
+ return PTR_ERR(clk_bus);
+
spin_lock_init(&sai_clk->lock);
- sai_clk->gate.reg = base + data->offset + I2S_CSR;
- sai_clk->gate.bit_idx = CSR_BCE_BIT;
- sai_clk->gate.lock = &sai_clk->lock;
+ sai_clk->bclk_gate.reg = base + data->offset + I2S_CSR;
+ sai_clk->bclk_gate.bit_idx = CSR_BCE_BIT;
+ sai_clk->bclk_gate.lock = &sai_clk->lock;
- sai_clk->div.reg = base + data->offset + I2S_CR2;
- sai_clk->div.shift = CR2_DIV_SHIFT;
- sai_clk->div.width = CR2_DIV_WIDTH;
- sai_clk->div.lock = &sai_clk->lock;
+ sai_clk->bclk_div.reg = base + data->offset + I2S_CR2;
+ sai_clk->bclk_div.shift = CR2_DIV_SHIFT;
+ sai_clk->bclk_div.width = CR2_DIV_WIDTH;
+ sai_clk->bclk_div.lock = &sai_clk->lock;
/* set clock direction, we are the BCLK master */
writel(CR2_BCD, base + data->offset + I2S_CR2);
- hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name,
+ hw = devm_clk_hw_register_composite_pdata(dev, "BCLK",
&pdata, 1, NULL, NULL,
- &sai_clk->div.hw,
+ &sai_clk->bclk_div.hw,
&clk_divider_ops,
- &sai_clk->gate.hw,
+ &sai_clk->bclk_gate.hw,
&clk_gate_ops,
CLK_SET_RATE_GATE);
if (IS_ERR(hw))
return PTR_ERR(hw);
- return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
+ sai_clk->bclk_hw = hw;
+
+ if (data->have_mclk) {
+ sai_clk->mclk_gate.reg = base + data->offset + I2S_CSR;
+ sai_clk->mclk_gate.bit_idx = CSR_TE_BIT;
+ sai_clk->mclk_gate.lock = &sai_clk->lock;
+
+ sai_clk->mclk_div.reg = base + I2S_MCR;
+ sai_clk->mclk_div.shift = CR2_DIV_SHIFT;
+ sai_clk->mclk_div.width = CR2_DIV_WIDTH;
+ sai_clk->mclk_div.lock = &sai_clk->lock;
+
+ pdata.index = 1; /* MCLK1 */
+ hw = devm_clk_hw_register_composite_pdata(dev, "MCLK",
+ &pdata, 1, NULL, NULL,
+ &sai_clk->mclk_div.hw,
+ &clk_divider_ops,
+ &sai_clk->mclk_gate.hw,
+ &clk_gate_ops,
+ CLK_SET_RATE_GATE);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+
+ sai_clk->mclk_hw = hw;
+
+ /* set clock direction, we are the MCLK output */
+ writel(MCR_MOE, base + I2S_MCR);
+ }
+
+ return devm_of_clk_add_hw_provider(dev, fsl_sai_of_clk_get, sai_clk);
}
static const struct fsl_sai_data fsl_sai_vf610_data = {
.offset = 0,
+ .have_mclk = false,
};
static const struct fsl_sai_data fsl_sai_imx8mq_data = {
.offset = 8,
+ .have_mclk = true,
};
static const struct of_device_id of_fsl_sai_clk_ids[] = {
--
2.45.2
^ permalink raw reply related [flat|nested] 5+ messages in thread