[PATCH 3/3] dt-bindings: clock: xilinx: Update VCU bindings for reset GPIO

[Rohit Visavalia <rohit.visavalia@amd.com>]

Updated VCU binding for reset GPIO pin as optional property.
It is marked as optional as some of the ZynqMP designs are having vcu_reset
(reset pin of VCU IP) is driven by proc_sys_reset, proc_sys_reset is another
PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by
axi_gpio or PS GPIO so there will be no GPIO entry.

Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com>
---
 Documentation/devicetree/bindings/clock/xlnx,vcu.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
index bdb14594c40b..b3061309f8dd 100644
--- a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
+++ b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml
@@ -36,6 +36,11 @@ properties:
       - const: pll_ref
       - const: aclk
 
+  reset-gpios:
+    description: Optional GPIO used to reset the VCU, if available. Need use this
+      reset gpio when in design 'vcu_resetn' is driven by gpio.
+    maxItems: 1
+
 required:
   - reg
   - clocks
@@ -52,6 +57,7 @@ examples:
         xlnx_vcu: vcu@a0040000 {
             compatible = "xlnx,vcu-logicoreip-1.0";
             reg = <0x0 0xa0040000 0x0 0x1000>;
+            reset-gpios = <&gpio 0x4e GPIO_ACTIVE_HIGH>;
             clocks = <&si570_1>, <&clkc 71>;
             clock-names = "pll_ref", "aclk";
         };
-- 
2.25.1