[PATCH 0/4] Add support for Mali-G52 to RZ/G3E SoC

[PATCH 0/4] Add support for Mali-G52 to RZ/G3E SoC

[Tommaso Merciai]

Dear All,

This patch series adds support for the Mali-G52 GPU on the RZ/G3E SoC.
The changes include updating the device tree bindings, adding the GPU node
to the SoC device tree, and enabling the GPU on the R9A09G047E57 SMARC SoM board.

Note:
This patchset is applied on top of:
 - https://web.git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/log/
 - https://patchwork.kernel.org/project/linux-renesas-soc/patch/20250207113653.21641-13-biju.das.jz@bp.renesas.com/
 - https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=942041

Thanks & Regards,
Tommaso

Tommaso Merciai (4):
  clk: renesas: r9a09g047: Add clock and reset entries for GE3D
  dt-bindings: gpu: mali-bifrost: Add compatible for RZ/G3E SoC
  arm64: dts: renesas: r9a09g047: Add Mali-G52 GPU node
  arm64: dts: renesas: rzg3e-smarc-som: Enable Mali-G52

 .../bindings/gpu/arm,mali-bifrost.yaml        |  2 +
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 49 +++++++++++++++++++
 .../boot/dts/renesas/rzg3e-smarc-som.dtsi     | 15 ++++++
 drivers/clk/renesas/r9a09g047-cpg.c           | 11 +++++
 4 files changed, 77 insertions(+)

-- 
2.43.0

[PATCH 1/4] clk: renesas: r9a09g047: Add clock and reset entries for GE3D

[Tommaso Merciai]

Add CLK_PLLVDO_GPU along with the necessary clock and reset entries for
GE3D.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 drivers/clk/renesas/r9a09g047-cpg.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index e9cf4342d0cfb..2aa1e0aa4d36d 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -41,6 +41,7 @@ enum clk_ids {
 	CLK_PLLDTY_ACPU_DIV4,
 	CLK_PLLDTY_DIV16,
 	CLK_PLLVDO_CRU0,
+	CLK_PLLVDO_GPU,
 
 	/* Module Clocks */
 	MOD_CLK_BASE,
@@ -96,6 +97,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
 	DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
 
 	DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
+	DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
 
 	/* Core Clocks */
 	DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
@@ -185,6 +187,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
 						BUS_MSTOP(9, BIT(4))),
 	DEF_MOD("tsu_1_pclk",			CLK_QEXTAL, 16, 10, 8, 10,
 						BUS_MSTOP(2, BIT(15))),
+	DEF_MOD("ge3d_clk",			CLK_PLLVDO_GPU, 15, 0, 7, 16,
+						BUS_MSTOP(3, BIT(4))),
+	DEF_MOD("ge3d_axi_clk",			CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
+						BUS_MSTOP(3, BIT(4))),
+	DEF_MOD("ge3d_ace_clk",			CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
+						BUS_MSTOP(3, BIT(4))),
 };
 
 static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
@@ -214,6 +222,9 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
 	DEF_RST(12, 6, 5, 23),		/* CRU_0_ARESETN */
 	DEF_RST(12, 7, 5, 24),		/* CRU_0_S_RESETN */
 	DEF_RST(15, 8, 7, 9),		/* TSU_1_PRESETN */
+	DEF_RST(13, 13, 6, 14),		/* GE3D_0_RESETN */
+	DEF_RST(13, 14, 6, 15),		/* GE3D_0_AXI_RESETN */
+	DEF_RST(13, 15, 6, 16),		/* GE3D_0_ACE_RESETN */
 };
 
 const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
-- 
2.43.0

Re: [PATCH 1/4] clk: renesas: r9a09g047: Add clock and reset entries for GE3D

[Geert Uytterhoeven]

Hi Tommaso,

On Wed, 2 Apr 2025 at 15:12, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> Add CLK_PLLVDO_GPU along with the necessary clock and reset entries for
> GE3D.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -185,6 +187,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
>                                                 BUS_MSTOP(9, BIT(4))),
>         DEF_MOD("tsu_1_pclk",                   CLK_QEXTAL, 16, 10, 8, 10,
>                                                 BUS_MSTOP(2, BIT(15))),
> +       DEF_MOD("ge3d_clk",                     CLK_PLLVDO_GPU, 15, 0, 7, 16,
> +                                               BUS_MSTOP(3, BIT(4))),
> +       DEF_MOD("ge3d_axi_clk",                 CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
> +                                               BUS_MSTOP(3, BIT(4))),
> +       DEF_MOD("ge3d_ace_clk",                 CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
> +                                               BUS_MSTOP(3, BIT(4))),

Moving up to preserve sort order (by CPG_CLKON module number).

>  };
>
>  static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
> @@ -214,6 +222,9 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
>         DEF_RST(12, 6, 5, 23),          /* CRU_0_ARESETN */
>         DEF_RST(12, 7, 5, 24),          /* CRU_0_S_RESETN */
>         DEF_RST(15, 8, 7, 9),           /* TSU_1_PRESETN */
> +       DEF_RST(13, 13, 6, 14),         /* GE3D_0_RESETN */
> +       DEF_RST(13, 14, 6, 15),         /* GE3D_0_AXI_RESETN */
> +       DEF_RST(13, 15, 6, 16),         /* GE3D_0_ACE_RESETN */

Moving up to preserve sort order (by CPF_RST module number).
The documentation does not have the "_0" part in the reset names,
so I will drop these while applying, too.

>  };
>
>  const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.16 with the above fixed.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 2/4] dt-bindings: gpu: mali-bifrost: Add compatible for RZ/G3E SoC

[Tommaso Merciai]

Add a compatible string for the Renesas RZ/G3E SoC variants that
include a Mali-G52 GPU. These variants share the same restrictions on
interrupts, clocks, and power domains as the RZ/G2L SoC, so extend
the existing schema validation accordingly.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
index 019bd28a29f19..e25478f2ce521 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
@@ -25,6 +25,7 @@ properties:
               - realtek,rtd1619-mali
               - renesas,r9a07g044-mali
               - renesas,r9a07g054-mali
+              - renesas,r9a09g047-mali
               - renesas,r9a09g057-mali
               - rockchip,px30-mali
               - rockchip,rk3562-mali
@@ -145,6 +146,7 @@ allOf:
             enum:
               - renesas,r9a07g044-mali
               - renesas,r9a07g054-mali
+              - renesas,r9a09g047-mali
               - renesas,r9a09g057-mali
     then:
       properties:
-- 
2.43.0

Re: [PATCH 2/4] dt-bindings: gpu: mali-bifrost: Add compatible for RZ/G3E SoC

[Krzysztof Kozlowski]

On Wed, Apr 02, 2025 at 03:11:39PM GMT, Tommaso Merciai wrote:
> Add a compatible string for the Renesas RZ/G3E SoC variants that
> include a Mali-G52 GPU. These variants share the same restrictions on
> interrupts, clocks, and power domains as the RZ/G2L SoC, so extend
> the existing schema validation accordingly.
> 
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 2 ++
>  1 file changed, 2 insertions(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: gpu: mali-bifrost: Add compatible for RZ/G3E SoC

[Geert Uytterhoeven]

On Wed, 2 Apr 2025 at 15:12, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> Add a compatible string for the Renesas RZ/G3E SoC variants that
> include a Mali-G52 GPU. These variants share the same restrictions on
> interrupts, clocks, and power domains as the RZ/G2L SoC, so extend
> the existing schema validation accordingly.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 3/4] arm64: dts: renesas: r9a09g047: Add Mali-G52 GPU node

[Tommaso Merciai]

Add Mali-G52 GPU node to SoC DTSI.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 4bc0b77f721ab..9ab83e949c0ea 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -105,6 +105,35 @@ L3_CA55: cache-controller-0 {
 		};
 	};
 
+	gpu_opp_table: opp-table-1 {
+		compatible = "operating-points-v2";
+
+		opp-630000000 {
+			opp-hz = /bits/ 64 <630000000>;
+			opp-microvolt = <800000>;
+		};
+
+		opp-315000000 {
+			opp-hz = /bits/ 64 <315000000>;
+			opp-microvolt = <800000>;
+		};
+
+		opp-157500000 {
+			opp-hz = /bits/ 64 <157500000>;
+			opp-microvolt = <800000>;
+		};
+
+		opp-78750000 {
+			opp-hz = /bits/ 64 <78750000>;
+			opp-microvolt = <800000>;
+		};
+
+		opp-19687500 {
+			opp-hz = /bits/ 64 <19687500>;
+			opp-microvolt = <800000>;
+		};
+	};
+
 	psci {
 		compatible = "arm,psci-1.0", "arm,psci-0.2";
 		method = "smc";
@@ -491,6 +520,26 @@ i2c8: i2c@11c01000 {
 			status = "disabled";
 		};
 
+		gpu: gpu@14850000 {
+			compatible = "renesas,r9a09g047-mali",
+				     "arm,mali-bifrost";
+			reg = <0x0 0x14850000 0x0 0x10000>;
+			interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "job", "mmu", "gpu", "event";
+			clocks = <&cpg CPG_MOD 0xf0>,
+				 <&cpg CPG_MOD 0xf1>,
+				 <&cpg CPG_MOD 0xf2>;
+			clock-names = "gpu", "bus", "bus_ace";
+			power-domains = <&cpg>;
+			resets = <&cpg 0xdd>, <&cpg 0xde>, <&cpg 0xdf>;
+			reset-names = "rst", "axi_rst", "ace_rst";
+			operating-points-v2 = <&gpu_opp_table>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@14900000 {
 			compatible = "arm,gic-v3";
 			reg = <0x0 0x14900000 0 0x20000>,
-- 
2.43.0

Re: [PATCH 3/4] arm64: dts: renesas: r9a09g047: Add Mali-G52 GPU node

[Geert Uytterhoeven]

On Wed, 2 Apr 2025 at 15:12, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> Add Mali-G52 GPU node to SoC DTSI.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.16.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 4/4] arm64: dts: renesas: rzg3e-smarc-som: Enable Mali-G52

[Tommaso Merciai]

Enable Mali-G52 (GPU) node on RZ/G3E SMARC SoM board.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
index 72b42a81bcf34..5c4596dea2160 100644
--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -45,6 +45,16 @@ reg_3p3v: regulator-3p3v {
 		regulator-boot-on;
 		regulator-always-on;
 	};
+
+	reg_vdd0p8v_others: regulator-vdd0p8v-others {
+		compatible = "regulator-fixed";
+
+		regulator-name = "fixed-0.8V";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
 };
 
 &audio_extal_clk {
@@ -123,6 +133,11 @@ sd2-pwen {
 	};
 };
 
+&gpu {
+	status = "okay";
+	mali-supply = <&reg_vdd0p8v_others>;
+};
+
 &qextal_clk {
 	clock-frequency = <24000000>;
 };
-- 
2.43.0

Re: [PATCH 4/4] arm64: dts: renesas: rzg3e-smarc-som: Enable Mali-G52

[Geert Uytterhoeven]

Hi Tommaso,

On Wed, 2 Apr 2025 at 15:13, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> Enable Mali-G52 (GPU) node on RZ/G3E SMARC SoM board.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> @@ -45,6 +45,16 @@ reg_3p3v: regulator-3p3v {
>                 regulator-boot-on;
>                 regulator-always-on;
>         };
> +
> +       reg_vdd0p8v_others: regulator-vdd0p8v-others {
> +               compatible = "regulator-fixed";
> +
> +               regulator-name = "fixed-0.8V";
> +               regulator-min-microvolt = <800000>;
> +               regulator-max-microvolt = <800000>;
> +               regulator-boot-on;
> +               regulator-always-on;
> +       };
>  };
>
>  &audio_extal_clk {
> @@ -123,6 +133,11 @@ sd2-pwen {
>         };
>  };
>
> +&gpu {

Moving up to preserve sort order (alphabetical).

> +       status = "okay";
> +       mali-supply = <&reg_vdd0p8v_others>;
> +};
> +
>  &qextal_clk {
>         clock-frequency = <24000000>;
>  };

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.16 with the above fixed.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds