[PATCH v1] clk: samsung: exynosautov920: add block hsi2 clock support

[PATCH v1] clk: samsung: exynosautov920: add block hsi2 clock support

[Raghav Sharma]

Register compatible and cmu_info data to support clocks.
CMU_HSI2, this provides clocks for HSI2 block

Signed-off-by: Raghav Sharma <raghav.s@samsung.com>
---
 drivers/clk/samsung/clk-exynosautov920.c | 72 ++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c
index f8168eed4a66..89d6ea10515d 100644
--- a/drivers/clk/samsung/clk-exynosautov920.c
+++ b/drivers/clk/samsung/clk-exynosautov920.c
@@ -26,6 +26,7 @@
 #define CLKS_NR_MISC			(CLK_DOUT_MISC_OSC_DIV2 + 1)
 #define CLKS_NR_HSI0			(CLK_DOUT_HSI0_PCIE_APB + 1)
 #define CLKS_NR_HSI1			(CLK_MOUT_HSI1_USBDRD + 1)
+#define CLKS_NR_HSI2			(CLK_DOUT_HSI2_ETHERNET_PTP + 1)
 
 /* ---- CMU_TOP ------------------------------------------------------------ */
 
@@ -1752,6 +1753,74 @@ static const struct samsung_cmu_info hsi1_cmu_info __initconst = {
 	.clk_name		= "noc",
 };
 
+/* ---- CMU_HSI2 --------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_HSI2 (0x16b00000) */
+#define PLL_LOCKTIME_PLL_ETH                    0x0
+#define PLL_CON3_PLL_ETH			0x10c
+#define PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER  0x600
+#define PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER   0x610
+#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER  0x630
+#define CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET       0x1000
+#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET       0x1800
+#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP   0x1804
+
+static const unsigned long hsi2_clk_regs[] __initconst = {
+	PLL_LOCKTIME_PLL_ETH,
+	PLL_CON3_PLL_ETH,
+	PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER,
+	PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER,
+	PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
+	CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET,
+	CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,
+	CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,
+};
+
+static const struct samsung_pll_clock hsi2_pll_clks[] __initconst = {
+	/* CMU_HSI2_PLL */
+	PLL(pll_531x, FOUT_PLL_ETH, "fout_pll_eth", "oscclk",
+	    PLL_LOCKTIME_PLL_ETH, PLL_CON3_PLL_ETH, NULL),
+};
+
+/* List of parent clocks for Muxes in CMU_HSI2 */
+PNAME(mout_clkcmu_hsi2_noc_ufs_user_p) = { "oscclk", "dout_clkcmu_hsi2_noc_ufs" };
+PNAME(mout_clkcmu_hsi2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_hsi2_ufs_embd" };
+PNAME(mout_hsi2_ethernet_p) = { "fout_pll_eth", "mout_clkcmu_hsi2_ethernet_user" };
+PNAME(mout_clkcmu_hsi2_ethernet_user_p) = { "oscclk", "dout_clkcmu_hsi2_ethernet" };
+
+static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_HSI2_NOC_UFS_USER, "mout_clkcmu_hsi2_noc_ufs_user",
+	    mout_clkcmu_hsi2_noc_ufs_user_p, PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER, 4, 1),
+	MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_clkcmu_hsi2_ufs_embd_user",
+	    mout_clkcmu_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 4, 1),
+	MUX(CLK_MOUT_HSI2_ETHERNET, "mout_hsi2_ethernet",
+	    mout_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET, 0, 1),
+	MUX(CLK_MOUT_HSI2_ETHERNET_USER, "mout_clkcmu_hsi2_ethernet_user",
+	    mout_clkcmu_hsi2_ethernet_user_p, PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER, 4, 1),
+};
+
+static const struct samsung_div_clock hsi2_div_clks[] __initconst = {
+	DIV(CLK_DOUT_HSI2_ETHERNET, "dout_hsi2_ethernet",
+	    "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,
+	    0, 4),
+	DIV(CLK_DOUT_HSI2_ETHERNET_PTP, "dout_hsi2_ethernet_ptp",
+	    "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,
+	    0, 4),
+};
+
+static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
+	.pll_clks               = hsi2_pll_clks,
+	.nr_pll_clks            = ARRAY_SIZE(hsi2_pll_clks),
+	.mux_clks               = hsi2_mux_clks,
+	.nr_mux_clks            = ARRAY_SIZE(hsi2_mux_clks),
+	.div_clks               = hsi2_div_clks,
+	.nr_div_clks            = ARRAY_SIZE(hsi2_div_clks),
+	.nr_clk_ids             = CLKS_NR_HSI2,
+	.clk_regs               = hsi2_clk_regs,
+	.nr_clk_regs            = ARRAY_SIZE(hsi2_clk_regs),
+	.clk_name               = "noc",
+};
+
 static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
 {
 	const struct samsung_cmu_info *info;
@@ -1779,6 +1848,9 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = {
 	}, {
 		.compatible = "samsung,exynosautov920-cmu-hsi1",
 		.data = &hsi1_cmu_info,
+	}, {
+		.compatible = "samsung,exynosautov920-cmu-hsi2",
+		.data = &hsi2_cmu_info,
 	},
 	{ }
 };
-- 
2.34.1

Re: [PATCH v1] clk: samsung: exynosautov920: add block hsi2 clock support

[Krzysztof Kozlowski]

On 09/05/2025 15:12, Raghav Sharma wrote:
> Register compatible and cmu_info data to support clocks.
> CMU_HSI2, this provides clocks for HSI2 block
> 
> Signed-off-by: Raghav Sharma <raghav.s@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynosautov920.c | 72 ++++++++++++++++++++++++
>  1 file changed, 72 insertions(+)

That's some mess. You sent three separate patches, some duplicated, not
threaded, without bindings. Look at mailing list to learn how such
submission should look like.

Read carefully maintainer soc profiles listed under SAMSUNG maintainer's
entry.

Best regards,
Krzysztof

Re: [PATCH v1] clk: samsung: exynosautov920: add block hsi2 clock support

[kernel test robot]

Hi Raghav,

kernel test robot noticed the following build errors:

[auto build test ERROR on krzk/for-next]
[also build test ERROR on linus/master v6.15-rc5 next-20250509]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Raghav-Sharma/clk-samsung-exynosautov920-add-block-hsi2-clock-support/20250509-212922
base:   https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git for-next
patch link:    https://lore.kernel.org/r/20250509131210.3192208-1-raghav.s%40samsung.com
patch subject: [PATCH v1] clk: samsung: exynosautov920: add block hsi2 clock support
config: csky-randconfig-002-20250510 (https://download.01.org/0day-ci/archive/20250510/202505100814.gnMY3LoZ-lkp@intel.com/config)
compiler: csky-linux-gcc (GCC) 13.3.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250510/202505100814.gnMY3LoZ-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505100814.gnMY3LoZ-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from drivers/clk/samsung/clk-exynosautov920.c:16:
>> drivers/clk/samsung/clk-exynosautov920.c:1781:23: error: 'FOUT_PLL_ETH' undeclared here (not in a function)
    1781 |         PLL(pll_531x, FOUT_PLL_ETH, "fout_pll_eth", "oscclk",
         |                       ^~~~~~~~~~~~
   drivers/clk/samsung/clk.h:273:35: note: in definition of macro '__PLL'
     273 |                 .id             = _id,                                  \
         |                                   ^~~
   drivers/clk/samsung/clk-exynosautov920.c:1781:9: note: in expansion of macro 'PLL'
    1781 |         PLL(pll_531x, FOUT_PLL_ETH, "fout_pll_eth", "oscclk",
         |         ^~~
>> drivers/clk/samsung/clk-exynosautov920.c:1792:13: error: 'CLK_MOUT_HSI2_NOC_UFS_USER' undeclared here (not in a function); did you mean 'CLK_MOUT_HSI1_NOC_USER'?
    1792 |         MUX(CLK_MOUT_HSI2_NOC_UFS_USER, "mout_clkcmu_hsi2_noc_ufs_user",
         |             ^~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/clk/samsung/clk.h:133:35: note: in definition of macro '__MUX'
     133 |                 .id             = _id,                          \
         |                                   ^~~
   drivers/clk/samsung/clk-exynosautov920.c:1792:9: note: in expansion of macro 'MUX'
    1792 |         MUX(CLK_MOUT_HSI2_NOC_UFS_USER, "mout_clkcmu_hsi2_noc_ufs_user",
         |         ^~~
>> drivers/clk/samsung/clk-exynosautov920.c:1794:13: error: 'CLK_MOUT_HSI2_UFS_EMBD_USER' undeclared here (not in a function); did you mean 'CLK_MOUT_HSI1_USBDRD_USER'?
    1794 |         MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_clkcmu_hsi2_ufs_embd_user",
         |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/clk/samsung/clk.h:133:35: note: in definition of macro '__MUX'
     133 |                 .id             = _id,                          \
         |                                   ^~~
   drivers/clk/samsung/clk-exynosautov920.c:1794:9: note: in expansion of macro 'MUX'
    1794 |         MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_clkcmu_hsi2_ufs_embd_user",
         |         ^~~
>> drivers/clk/samsung/clk-exynosautov920.c:1796:13: error: 'CLK_MOUT_HSI2_ETHERNET' undeclared here (not in a function)
    1796 |         MUX(CLK_MOUT_HSI2_ETHERNET, "mout_hsi2_ethernet",
         |             ^~~~~~~~~~~~~~~~~~~~~~
   drivers/clk/samsung/clk.h:133:35: note: in definition of macro '__MUX'
     133 |                 .id             = _id,                          \
         |                                   ^~~
   drivers/clk/samsung/clk-exynosautov920.c:1796:9: note: in expansion of macro 'MUX'
    1796 |         MUX(CLK_MOUT_HSI2_ETHERNET, "mout_hsi2_ethernet",
         |         ^~~
>> drivers/clk/samsung/clk-exynosautov920.c:1798:13: error: 'CLK_MOUT_HSI2_ETHERNET_USER' undeclared here (not in a function); did you mean 'CLK_MOUT_HSI1_NOC_USER'?
    1798 |         MUX(CLK_MOUT_HSI2_ETHERNET_USER, "mout_clkcmu_hsi2_ethernet_user",
         |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/clk/samsung/clk.h:133:35: note: in definition of macro '__MUX'
     133 |                 .id             = _id,                          \
         |                                   ^~~
   drivers/clk/samsung/clk-exynosautov920.c:1798:9: note: in expansion of macro 'MUX'
    1798 |         MUX(CLK_MOUT_HSI2_ETHERNET_USER, "mout_clkcmu_hsi2_ethernet_user",
         |         ^~~
>> drivers/clk/samsung/clk-exynosautov920.c:1803:13: error: 'CLK_DOUT_HSI2_ETHERNET' undeclared here (not in a function)
    1803 |         DIV(CLK_DOUT_HSI2_ETHERNET, "dout_hsi2_ethernet",
         |             ^~~~~~~~~~~~~~~~~~~~~~
   drivers/clk/samsung/clk.h:183:35: note: in definition of macro '__DIV'
     183 |                 .id             = _id,                          \
         |                                   ^~~
   drivers/clk/samsung/clk-exynosautov920.c:1803:9: note: in expansion of macro 'DIV'
    1803 |         DIV(CLK_DOUT_HSI2_ETHERNET, "dout_hsi2_ethernet",
         |         ^~~
>> drivers/clk/samsung/clk-exynosautov920.c:1806:13: error: 'CLK_DOUT_HSI2_ETHERNET_PTP' undeclared here (not in a function)
    1806 |         DIV(CLK_DOUT_HSI2_ETHERNET_PTP, "dout_hsi2_ethernet_ptp",
         |             ^~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/clk/samsung/clk.h:183:35: note: in definition of macro '__DIV'
     183 |                 .id             = _id,                          \
         |                                   ^~~
   drivers/clk/samsung/clk-exynosautov920.c:1806:9: note: in expansion of macro 'DIV'
    1806 |         DIV(CLK_DOUT_HSI2_ETHERNET_PTP, "dout_hsi2_ethernet_ptp",
         |         ^~~


vim +/FOUT_PLL_ETH +1781 drivers/clk/samsung/clk-exynosautov920.c

  1778	
  1779	static const struct samsung_pll_clock hsi2_pll_clks[] __initconst = {
  1780		/* CMU_HSI2_PLL */
> 1781		PLL(pll_531x, FOUT_PLL_ETH, "fout_pll_eth", "oscclk",
  1782		    PLL_LOCKTIME_PLL_ETH, PLL_CON3_PLL_ETH, NULL),
  1783	};
  1784	
  1785	/* List of parent clocks for Muxes in CMU_HSI2 */
  1786	PNAME(mout_clkcmu_hsi2_noc_ufs_user_p) = { "oscclk", "dout_clkcmu_hsi2_noc_ufs" };
  1787	PNAME(mout_clkcmu_hsi2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_hsi2_ufs_embd" };
  1788	PNAME(mout_hsi2_ethernet_p) = { "fout_pll_eth", "mout_clkcmu_hsi2_ethernet_user" };
  1789	PNAME(mout_clkcmu_hsi2_ethernet_user_p) = { "oscclk", "dout_clkcmu_hsi2_ethernet" };
  1790	
  1791	static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {
> 1792		MUX(CLK_MOUT_HSI2_NOC_UFS_USER, "mout_clkcmu_hsi2_noc_ufs_user",
  1793		    mout_clkcmu_hsi2_noc_ufs_user_p, PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER, 4, 1),
> 1794		MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_clkcmu_hsi2_ufs_embd_user",
  1795		    mout_clkcmu_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 4, 1),
> 1796		MUX(CLK_MOUT_HSI2_ETHERNET, "mout_hsi2_ethernet",
  1797		    mout_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET, 0, 1),
> 1798		MUX(CLK_MOUT_HSI2_ETHERNET_USER, "mout_clkcmu_hsi2_ethernet_user",
  1799		    mout_clkcmu_hsi2_ethernet_user_p, PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER, 4, 1),
  1800	};
  1801	
  1802	static const struct samsung_div_clock hsi2_div_clks[] __initconst = {
> 1803		DIV(CLK_DOUT_HSI2_ETHERNET, "dout_hsi2_ethernet",
  1804		    "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,
  1805		    0, 4),
> 1806		DIV(CLK_DOUT_HSI2_ETHERNET_PTP, "dout_hsi2_ethernet_ptp",
  1807		    "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,
  1808		    0, 4),
  1809	};
  1810	

-- 
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https://github.com/intel/lkp-tests/wiki