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From: Svyatoslav Ryhel <clamor95@gmail.com>
To: "David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Thierry Reding" <thierry.reding@gmail.com>,
	"Jonathan Hunter" <jonathanh@nvidia.com>,
	"Sowjanya Komatineni" <skomatineni@nvidia.com>,
	"Luca Ceresoli" <luca.ceresoli@bootlin.com>,
	"Prashant Gaikwad" <pgaikwad@nvidia.com>,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Mikko Perttunen" <mperttunen@nvidia.com>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Mauro Carvalho Chehab" <mchehab@kernel.org>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Svyatoslav Ryhel" <clamor95@gmail.com>,
	"Jonas Schwöbel" <jonasschwoebel@yahoo.de>,
	"Dmitry Osipenko" <digetx@gmail.com>,
	"Charan Pedumuru" <charan.pedumuru@gmail.com>,
	"Diogo Ivo" <diogo.ivo@tecnico.ulisboa.pt>,
	"Aaron Kling" <webgeek1234@gmail.com>,
	"Arnd Bergmann" <arnd@arndb.de>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-media@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-gpio@vger.kernel.org, linux-staging@lists.linux.dev
Subject: [PATCH v3 21/22] ARM: tegra: add CSI nodes for Tegra20 and Tegra30
Date: Thu, 25 Sep 2025 18:16:47 +0300	[thread overview]
Message-ID: <20250925151648.79510-22-clamor95@gmail.com> (raw)
In-Reply-To: <20250925151648.79510-1-clamor95@gmail.com>

Add CSI node to Tegra20 and Tegra30 device trees.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 arch/arm/boot/dts/nvidia/tegra20.dtsi | 19 ++++++++++++++++++-
 arch/arm/boot/dts/nvidia/tegra30.dtsi | 24 ++++++++++++++++++++++--
 2 files changed, 40 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi b/arch/arm/boot/dts/nvidia/tegra20.dtsi
index 6ae07b316c8a..5cdbf1246cf8 100644
--- a/arch/arm/boot/dts/nvidia/tegra20.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi
@@ -64,7 +64,7 @@ mpe@54040000 {
 
 		vi@54080000 {
 			compatible = "nvidia,tegra20-vi";
-			reg = <0x54080000 0x00040000>;
+			reg = <0x54080000 0x00000800>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA20_CLK_VI>;
 			resets = <&tegra_car 20>;
@@ -72,6 +72,23 @@ vi@54080000 {
 			power-domains = <&pd_venc>;
 			operating-points-v2 = <&vi_dvfs_opp_table>;
 			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0x0 0x54080000 0x4000>;
+
+			csi: csi@800 {
+				compatible = "nvidia,tegra20-csi";
+				reg = <0x800 0x200>;
+				clocks = <&tegra_car TEGRA20_CLK_CSI>;
+				power-domains = <&pd_venc>;
+				#nvidia,mipi-calibrate-cells = <1>;
+				status = "disabled";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
 		};
 
 		epp@540c0000 {
diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi b/arch/arm/boot/dts/nvidia/tegra30.dtsi
index 20b3248d4d2f..be752a245a55 100644
--- a/arch/arm/boot/dts/nvidia/tegra30.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi
@@ -150,8 +150,8 @@ mpe@54040000 {
 		};
 
 		vi@54080000 {
-			compatible = "nvidia,tegra30-vi";
-			reg = <0x54080000 0x00040000>;
+			compatible = "nvidia,tegra30-vi", "nvidia,tegra20-vi";
+			reg = <0x54080000 0x00000800>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_VI>;
 			resets = <&tegra_car 20>;
@@ -162,6 +162,26 @@ vi@54080000 {
 			iommus = <&mc TEGRA_SWGROUP_VI>;
 
 			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ranges = <0x0 0x54080000 0x4000>;
+
+			csi: csi@800 {
+				compatible = "nvidia,tegra30-csi";
+				reg = <0x800 0x200>;
+				clocks = <&tegra_car TEGRA30_CLK_CSI>,
+					 <&tegra_car TEGRA30_CLK_CSIA_PAD>,
+					 <&tegra_car TEGRA30_CLK_CSIB_PAD>;
+				clock-names = "csi", "csia-pad", "csib-pad";
+				power-domains = <&pd_venc>;
+				#nvidia,mipi-calibrate-cells = <1>;
+				status = "disabled";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
 		};
 
 		epp@540c0000 {
-- 
2.48.1


  parent reply	other threads:[~2025-09-25 15:17 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-25 15:16 [PATCH v3 00/22] tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 01/22] clk: tegra: set CSUS as vi_sensor's gate for Tegra20, Tegra30 and Tegra114 Svyatoslav Ryhel
2025-10-01  4:02   ` Mikko Perttunen
2025-09-25 15:16 ` [PATCH v3 02/22] dt-bindings: clock: tegra30: Add IDs for CSI pad clocks Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 03/22] clk: tegra30: add CSI pad clock gates Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 04/22] dt-bindings: display: tegra: document Tegra30 VI and VIP Svyatoslav Ryhel
2025-10-02  1:19   ` Rob Herring (Arm)
2025-09-25 15:16 ` [PATCH v3 05/22] staging: media: tegra-video: expand VI and VIP support to Tegra30 Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 06/22] staging: media: tegra-video: vi: adjust get_selection op check Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 07/22] staging: media: tegra-video: vi: add flip controls only if no source controls are provided Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 08/22] staging: media: tegra-video: csi: move CSI helpers to header Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 09/22] gpu: host1x: convert MIPI to use operation function pointers Svyatoslav Ryhel
2025-10-01  4:18   ` Mikko Perttunen
2025-09-25 15:16 ` [PATCH v3 10/22] staging: media: tegra-video: vi: improve logic of source requesting Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 11/22] staging: media: tegra-video: csi: move avdd-dsi-csi-supply from VI to CSI Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 12/22] arm64: tegra: move avdd-dsi-csi-supply into CSI node Svyatoslav Ryhel
2025-10-01  4:27   ` Mikko Perttunen
2025-09-25 15:16 ` [PATCH v3 13/22] staging: media: tegra-video: tegra20: set correct maximum width and height Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 14/22] staging: media: tegra-video: tegra20: add support for second output of VI Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 15/22] staging: media: tegra-video: tegra20: simplify format align calculations Svyatoslav Ryhel
2025-10-01  4:38   ` Mikko Perttunen
2025-10-01  5:07     ` Svyatoslav Ryhel
2025-10-01  5:35       ` Svyatoslav Ryhel
2025-10-01  7:51         ` Mikko Perttunen
2025-10-01  7:59           ` Svyatoslav Ryhel
2025-10-02  4:00             ` Mikko Perttunen
2025-10-02  5:41               ` Svyatoslav Ryhel
2025-10-02  6:12                 ` Mikko Perttunen
2025-10-02  6:20                   ` Svyatoslav Ryhel
2025-10-06 18:54                     ` Luca Ceresoli
2025-10-07 16:02                       ` Svyatoslav Ryhel
2025-10-07 19:37                         ` Luca Ceresoli
2025-10-08  5:44                           ` Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 16/22] staging: media: tegra-video: tegra20: set VI HW revision Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 17/22] staging: media: tegra-video: tegra20: increase maximum VI clock frequency Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 18/22] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422 1X16 Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 19/22] staging: media: tegra-video: tegra20: adjust luma buffer stride Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 20/22] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI Svyatoslav Ryhel
2025-10-02  1:52   ` Rob Herring
2025-10-02  5:14     ` Svyatoslav Ryhel
2025-10-06 20:31       ` Rob Herring
2025-10-07  5:13         ` Svyatoslav Ryhel
2025-09-25 15:16 ` Svyatoslav Ryhel [this message]
2025-09-25 15:16 ` [PATCH v3 22/22] staging: media: tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-10-01  5:04   ` Mikko Perttunen
2025-10-01  5:15     ` Svyatoslav Ryhel
2025-10-01  6:38       ` Mikko Perttunen
2025-10-01 15:23         ` Svyatoslav Ryhel
2025-10-02  4:03           ` Mikko Perttunen
2025-10-02 17:49     ` Svyatoslav Ryhel

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