From: Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org>
To: Chuan Liu <chuan.liu@amlogic.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Xianwei Zhao <xianwei.zhao@amlogic.com>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 0/8] clk: amlogic: Add A5 SoC PLLs and Peripheral clock
Date: Thu, 08 Jan 2026 14:08:14 +0800 [thread overview]
Message-ID: <20260108-a5-clk-v5-0-9a69fc1ef00a@amlogic.com> (raw)
The patchset adds support for the peripheral and PLL clock controller
on the Amlogic A5 SoC family, such as A113X2.
Co-developed-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
Changes in v5:
- Add “Co-developed-by” tag for Xianwei.
- Change rtc_clk flags to CLK_SET_RATE_NO_REPARENT.
- Optimize the macro definitions for clock configuration.
- Unified naming of clock parent related variables.
- Link to v4: https://lore.kernel.org/r/20251028-a5-clk-v4-0-e62ca0aae243@amlogic.com
Changes in v4:
- dt-binding for peripheral clocks (kept Rob’s 'Reviewed-by' here):
- Added optional clock source rtc pll.
- Renamed rtc_clk’s clkid to better reflect its function.
- PLL/Clock driver:
- Adapted to Jerome’s refactored driver interface, naming
conventions, and macros.
- Updated related CONFIG entries in Kconfig.
- Added dts patch of PLL/Clock.
- Link to v3: https://lore.kernel.org/r/20250103-a5-clk-v3-0-a207ce83b9e9@amlogic.com
Changes in v3:
- Rename xtal_24m to xtal, and modify some description of Kconfig.
- Drop some comment of PLL source code.
- Move definition of A5_CLK_GATE_FW frome common code into A5 peripheral source code.
- Use hw instead of name to describe parent_data.
- Making SCMI binding the first to submit.
- Link to v2: https://lore.kernel.org/r/20241120-a5-clk-v2-0-1208621e961d@amlogic.com
Changes in v2:
- Move some sys clock and axi clock from peripheral to scmi impletement.
- Remove ARM_SCMI_PROTOCOL in Kconfig and correct name A5 but not A4.
- Add two optional clock inputs for the peripheral(ddr pll and clk-measure)
- Make some changes and adjustments according to suggestions.
- Link to v1: https://lore.kernel.org/r/20240914-a5-clk-v1-0-5ee2c4f1b08c@amlogic.com
---
Chuan Liu (8):
dt-bindings: clock: Add Amlogic A5 SCMI clock controller support
dt-bindings: clock: Add Amlogic A5 PLL clock controller
dt-bindings: clock: Add Amlogic A5 peripherals clock controller
clk: amlogic: Add A5 PLL clock controller driver
clk: amlogic: Add A5 clock peripherals controller driver
arm64: dts: amlogic: A5: Add scmi-clk node
arm64: dts: amlogic: A5: Add PLL controller node
arm64: dts: amlogic: A5: Add peripheral clock controller node
.../clock/amlogic,a5-peripherals-clkc.yaml | 134 ++++
.../bindings/clock/amlogic,a5-pll-clkc.yaml | 63 ++
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 86 +++
drivers/clk/meson/Kconfig | 27 +
drivers/clk/meson/Makefile | 2 +
drivers/clk/meson/a5-peripherals.c | 796 +++++++++++++++++++++
drivers/clk/meson/a5-pll.c | 478 +++++++++++++
.../clock/amlogic,a5-peripherals-clkc.h | 132 ++++
include/dt-bindings/clock/amlogic,a5-pll-clkc.h | 24 +
include/dt-bindings/clock/amlogic,a5-scmi-clkc.h | 44 ++
10 files changed, 1786 insertions(+)
---
base-commit: f0b9d8eb98dfee8d00419aa07543bdc2c1a44fb1
change-id: 20240911-a5-clk-35c49acb34e1
Best regards,
--
Chuan Liu <chuan.liu@amlogic.com>
next reply other threads:[~2026-01-08 6:08 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-08 6:08 Chuan Liu via B4 Relay [this message]
2026-01-08 6:08 ` [PATCH v5 1/8] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support Chuan Liu via B4 Relay
2026-01-08 6:08 ` [PATCH v5 2/8] dt-bindings: clock: Add Amlogic A5 PLL clock controller Chuan Liu via B4 Relay
2026-01-08 6:08 ` [PATCH v5 3/8] dt-bindings: clock: Add Amlogic A5 peripherals " Chuan Liu via B4 Relay
2026-01-08 6:08 ` [PATCH v5 4/8] clk: amlogic: Add A5 PLL clock controller driver Chuan Liu via B4 Relay
2026-01-08 6:08 ` [PATCH v5 5/8] clk: amlogic: Add A5 clock peripherals " Chuan Liu via B4 Relay
2026-01-14 9:25 ` Jerome Brunet
2026-01-19 12:16 ` Chuan Liu
2026-01-19 13:27 ` Jerome Brunet
2026-03-20 10:42 ` Chuan Liu
2026-01-08 6:08 ` [PATCH v5 6/8] arm64: dts: amlogic: A5: Add scmi-clk node Chuan Liu via B4 Relay
2026-01-10 22:08 ` Martin Blumenstingl
2026-01-12 2:36 ` Chuan Liu
2026-01-08 6:08 ` [PATCH v5 7/8] arm64: dts: amlogic: A5: Add PLL controller node Chuan Liu via B4 Relay
2026-01-08 6:08 ` [PATCH v5 8/8] arm64: dts: amlogic: A5: Add peripheral clock " Chuan Liu via B4 Relay
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