From: Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org>
To: Chuan Liu <chuan.liu@amlogic.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Xianwei Zhao <xianwei.zhao@amlogic.com>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 8/8] arm64: dts: amlogic: A5: Add peripheral clock controller node
Date: Thu, 08 Jan 2026 14:08:22 +0800 [thread overview]
Message-ID: <20260108-a5-clk-v5-8-9a69fc1ef00a@amlogic.com> (raw)
In-Reply-To: <20260108-a5-clk-v5-0-9a69fc1ef00a@amlogic.com>
From: Chuan Liu <chuan.liu@amlogic.com>
Add peripheral clock controller node for A5 SoC family.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 43 +++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
index 70deeab220e0..7324e427ed39 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/power/amlogic,a5-pwrc.h>
#include <dt-bindings/clock/amlogic,a5-scmi-clkc.h>
#include <dt-bindings/clock/amlogic,a5-pll-clkc.h>
+#include <dt-bindings/clock/amlogic,a5-peripherals-clkc.h>
/ {
cpus {
@@ -83,6 +84,48 @@ scmi_clk: protocol@14 {
};
&apb {
+ clkc_periphs: clock-controller@0 {
+ compatible = "amlogic,a5-peripherals-clkc";
+ reg = <0x0 0x0 0x0 0x224>;
+ #clock-cells = <1>;
+ clocks = <&xtal>,
+ <&scmi_clk CLKID_OSC>,
+ <&scmi_clk CLKID_FIXED_PLL>,
+ <&scmi_clk CLKID_FCLK_DIV2>,
+ <&scmi_clk CLKID_FCLK_DIV2P5>,
+ <&scmi_clk CLKID_FCLK_DIV3>,
+ <&scmi_clk CLKID_FCLK_DIV4>,
+ <&scmi_clk CLKID_FCLK_DIV5>,
+ <&scmi_clk CLKID_FCLK_DIV7>,
+ <&clkc_pll CLKID_MPLL2>,
+ <&clkc_pll CLKID_MPLL3>,
+ <&clkc_pll CLKID_GP0_PLL>,
+ <&scmi_clk CLKID_GP1_PLL>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&scmi_clk CLKID_SYS_CLK>,
+ <&scmi_clk CLKID_AXI_CLK>,
+ <&scmi_clk CLKID_SYS_PLL_DIV16>,
+ <&scmi_clk CLKID_CPU_CLK_DIV16>;
+ clock-names = "xtal",
+ "oscin",
+ "fix",
+ "fdiv2",
+ "fdiv2p5",
+ "fdiv3",
+ "fdiv4",
+ "fdiv5",
+ "fdiv7",
+ "mpll2",
+ "mpll3",
+ "gp0",
+ "gp1",
+ "hifi",
+ "sysclk",
+ "axiclk",
+ "sysplldiv16",
+ "cpudiv16";
+ };
+
reset: reset-controller@2000 {
compatible = "amlogic,a5-reset",
"amlogic,meson-s4-reset";
--
2.42.0
prev parent reply other threads:[~2026-01-08 6:08 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-08 6:08 [PATCH v5 0/8] clk: amlogic: Add A5 SoC PLLs and Peripheral clock Chuan Liu via B4 Relay
2026-01-08 6:08 ` [PATCH v5 1/8] dt-bindings: clock: Add Amlogic A5 SCMI clock controller support Chuan Liu via B4 Relay
2026-01-08 6:08 ` [PATCH v5 2/8] dt-bindings: clock: Add Amlogic A5 PLL clock controller Chuan Liu via B4 Relay
2026-01-08 6:08 ` [PATCH v5 3/8] dt-bindings: clock: Add Amlogic A5 peripherals " Chuan Liu via B4 Relay
2026-01-08 6:08 ` [PATCH v5 4/8] clk: amlogic: Add A5 PLL clock controller driver Chuan Liu via B4 Relay
2026-01-08 6:08 ` [PATCH v5 5/8] clk: amlogic: Add A5 clock peripherals " Chuan Liu via B4 Relay
2026-01-14 9:25 ` Jerome Brunet
2026-01-19 12:16 ` Chuan Liu
2026-01-19 13:27 ` Jerome Brunet
2026-03-20 10:42 ` Chuan Liu
2026-01-08 6:08 ` [PATCH v5 6/8] arm64: dts: amlogic: A5: Add scmi-clk node Chuan Liu via B4 Relay
2026-01-10 22:08 ` Martin Blumenstingl
2026-01-12 2:36 ` Chuan Liu
2026-01-08 6:08 ` [PATCH v5 7/8] arm64: dts: amlogic: A5: Add PLL controller node Chuan Liu via B4 Relay
2026-01-08 6:08 ` Chuan Liu via B4 Relay [this message]
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