* [PATCH v2 1/3] dt-bindings: clock: Add ESWIN eic7700 HSP clock and reset generator
2026-04-20 9:39 [PATCH v2 0/3] Add driver support for ESWIN EIC7700 HSP clock and reset generator dongxuyang
@ 2026-04-20 9:40 ` dongxuyang
2026-04-20 16:06 ` Conor Dooley
2026-04-20 9:47 ` [PATCH v2 2/3] clk: eswin: Add eic7700 HSP clock driver dongxuyang
2026-04-20 9:47 ` [PATCH v2 3/3] reset: eswin: Add eic7700 HSP reset driver dongxuyang
2 siblings, 1 reply; 5+ messages in thread
From: dongxuyang @ 2026-04-20 9:40 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, linux-clk, devicetree,
linux-kernel, p.zabel, huangyifeng, dongxuyang, benoit.monin,
bmasney
Cc: ningyu, linmin, pinkesh.vaghela
From: Xuyang Dong <dongxuyang@eswincomputing.com>
Add bindings for the high-speed peripherals clock and reset generator
on the ESWIN EIC7700 HSP.
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
.../bindings/clock/eswin,eic7700-hspcrg.yaml | 63 +++++++++++++++++++
MAINTAINERS | 5 +-
.../dt-bindings/clock/eswin,eic7700-hspcrg.h | 33 ++++++++++
.../dt-bindings/reset/eswin,eic7700-hspcrg.h | 21 +++++++
4 files changed, 120 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
create mode 100644 include/dt-bindings/clock/eswin,eic7700-hspcrg.h
create mode 100644 include/dt-bindings/reset/eswin,eic7700-hspcrg.h
diff --git a/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml b/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
new file mode 100644
index 000000000000..43df689ae647
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/eswin,eic7700-hspcrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ESWIN EIC7700 HSP Clock and Reset Generator
+
+maintainers:
+ - Xuyang Dong <dongxuyang@eswincomputing.com>
+
+description:
+ Clock and reset generator for the ESWIN EIC7700 HSP (high-speed peripherals).
+
+properties:
+ compatible:
+ const: eswin,eic7700-hspcrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: HSP configuration top clock
+ - description: MMC top clock
+ - description: SATA top clock
+
+ clock-names:
+ items:
+ - const: cfg
+ - const: mmc
+ - const: sata
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/eswin,eic7700-hspcrg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/eswin,eic7700-hspcrg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@50440000 {
+ compatible = "eswin,eic7700-hspcrg";
+ reg = <0x50440000 0x2000>;
+ clocks = <&clock 171>, <&clock 254>, <&clock 187>;
+ clock-names = "cfg", "mmc", "sata";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index fe81fd3baedc..639fd11ebdd7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9573,9 +9573,10 @@ ESWIN EIC7700 CLOCK DRIVER
M: Yifeng Huang <huangyifeng@eswincomputing.com>
M: Xuyang Dong <dongxuyang@eswincomputing.com>
S: Maintained
-F: Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
+F: Documentation/devicetree/bindings/clock/eswin,eic7700*
F: drivers/clk/eswin/
-F: include/dt-bindings/clock/eswin,eic7700-clock.h
+F: include/dt-bindings/clock/eswin,eic7700*
+F: include/dt-bindings/reset/eswin,eic7700-hspcrg.h
ET131X NETWORK DRIVER
M: Mark Einon <mark.einon@gmail.com>
diff --git a/include/dt-bindings/clock/eswin,eic7700-hspcrg.h b/include/dt-bindings/clock/eswin,eic7700-hspcrg.h
new file mode 100644
index 000000000000..1d1ff15c1154
--- /dev/null
+++ b/include/dt-bindings/clock/eswin,eic7700-hspcrg.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 HSP clock controller.
+ *
+ * Authors: Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#ifndef _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_
+#define _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_
+
+#define EIC7700_HSP_CLK_FAC_CFG_DIV2 0
+#define EIC7700_HSP_CLK_FAC_CFG_DIV4 1
+#define EIC7700_HSP_CLK_FAC_MMC_DIV10 2
+#define EIC7700_HSP_CLK_MUX_EMMC_3MUX1 3
+#define EIC7700_HSP_CLK_MUX_SD0_3MUX1 4
+#define EIC7700_HSP_CLK_MUX_SD1_3MUX1 5
+#define EIC7700_HSP_CLK_MUX_EMMC_CQE_2MUX1 6
+#define EIC7700_HSP_CLK_MUX_SD0_CQE_2MUX1 7
+#define EIC7700_HSP_CLK_MUX_SD1_CQE_2MUX1 8
+#define EIC7700_HSP_CLK_GATE_MSHC0_TMR 9
+#define EIC7700_HSP_CLK_GATE_EMMC 10
+#define EIC7700_HSP_CLK_GATE_MSHC1_TMR 11
+#define EIC7700_HSP_CLK_GATE_SD0 12
+#define EIC7700_HSP_CLK_GATE_MSHC2_TMR 13
+#define EIC7700_HSP_CLK_GATE_SD1 14
+#define EIC7700_HSP_CLK_GATE_USB0 15
+#define EIC7700_HSP_CLK_GATE_USB1 16
+#define EIC7700_HSP_CLK_GATE_SATA 17
+
+#endif /* _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_CLOCK_H_ */
diff --git a/include/dt-bindings/reset/eswin,eic7700-hspcrg.h b/include/dt-bindings/reset/eswin,eic7700-hspcrg.h
new file mode 100644
index 000000000000..413fcd08c701
--- /dev/null
+++ b/include/dt-bindings/reset/eswin,eic7700-hspcrg.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 HSP reset controller.
+ *
+ * Authors: Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#ifndef _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_RESET_H_
+#define _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_RESET_H_
+
+#define EIC7700_HSP_RST_SATA_P0 0
+#define EIC7700_HSP_RST_SATA_PHY 1
+#define EIC7700_HSP_RST_USB0 2
+#define EIC7700_HSP_RST_USB1 3
+#define EIC7700_HSP_RST_USB0_PHY 4
+#define EIC7700_HSP_RST_USB1_PHY 5
+
+#endif /* _DT_BINDINGS_ESWIN_EIC7700_HSPCRG_RESET_H_ */
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v2 2/3] clk: eswin: Add eic7700 HSP clock driver
2026-04-20 9:39 [PATCH v2 0/3] Add driver support for ESWIN EIC7700 HSP clock and reset generator dongxuyang
2026-04-20 9:40 ` [PATCH v2 1/3] dt-bindings: clock: Add ESWIN eic7700 " dongxuyang
@ 2026-04-20 9:47 ` dongxuyang
2026-04-20 9:47 ` [PATCH v2 3/3] reset: eswin: Add eic7700 HSP reset driver dongxuyang
2 siblings, 0 replies; 5+ messages in thread
From: dongxuyang @ 2026-04-20 9:47 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, linux-clk, devicetree,
linux-kernel, p.zabel, huangyifeng, dongxuyang, benoit.monin,
bmasney
Cc: ningyu, linmin, pinkesh.vaghela
From: Xuyang Dong <dongxuyang@eswincomputing.com>
Add driver for the ESWIN EIC7700 high-speed peripherals system
clock controller and register an auxiliary device for system
reset controller which is named as "hsp-reset".
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
drivers/clk/eswin/Kconfig | 12 +
drivers/clk/eswin/Makefile | 1 +
drivers/clk/eswin/clk-eic7700-hsp.c | 385 ++++++++++++++++++++++++++++
3 files changed, 398 insertions(+)
create mode 100644 drivers/clk/eswin/clk-eic7700-hsp.c
diff --git a/drivers/clk/eswin/Kconfig b/drivers/clk/eswin/Kconfig
index 0406ec499ec9..e6cc2a407bac 100644
--- a/drivers/clk/eswin/Kconfig
+++ b/drivers/clk/eswin/Kconfig
@@ -13,3 +13,15 @@ config COMMON_CLK_EIC7700
SoC. The clock controller generates and supplies clocks to various
peripherals within the SoC.
Say yes here to support the clock controller on the EIC7700 SoC.
+
+config COMMON_CLK_EIC7700_HSP
+ tristate "EIC7700 HSP Clock Driver"
+ depends on ARCH_ESWIN || COMPILE_TEST
+ select AUXILIARY_BUS
+ select COMMON_CLK_EIC7700
+ select RESET_EIC7700_HSP if RESET_CONTROLLER
+ help
+ This driver provides support for clock controller on ESWIN EIC7700
+ HSP. The clock controller generates and supplies clocks to high
+ speed peripherals within the SoC.
+ Say yes here to support the clock controller on the EIC7700 HSP.
diff --git a/drivers/clk/eswin/Makefile b/drivers/clk/eswin/Makefile
index 4a7c2af82164..21a09a3396df 100644
--- a/drivers/clk/eswin/Makefile
+++ b/drivers/clk/eswin/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_COMMON_CLK_ESWIN) += clk.o
obj-$(CONFIG_COMMON_CLK_EIC7700) += clk-eic7700.o
+obj-$(CONFIG_COMMON_CLK_EIC7700_HSP) += clk-eic7700-hsp.o
diff --git a/drivers/clk/eswin/clk-eic7700-hsp.c b/drivers/clk/eswin/clk-eic7700-hsp.c
new file mode 100644
index 000000000000..d8f5493b45e7
--- /dev/null
+++ b/drivers/clk/eswin/clk-eic7700-hsp.c
@@ -0,0 +1,385 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * ESWIN EIC7700 HSP Clock Driver
+ *
+ * Authors: Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#include <linux/auxiliary_bus.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/eswin,eic7700-hspcrg.h>
+
+#include "common.h"
+
+#define EIC7700_HSP_SATA_REG 0x300
+#define EIC7700_HSP_MSHC0_REG 0x510
+#define EIC7700_HSP_MSHC1_REG 0x610
+#define EIC7700_HSP_MSHC2_REG 0x710
+#define EIC7700_HSP_USB0_REG 0x800
+#define EIC7700_HSP_USB0_REF_REG 0x83c
+#define EIC7700_HSP_USB1_REG 0x900
+#define EIC7700_HSP_USB1_REF_REG 0x93c
+
+#define USB_REF_XTAL24M 0x2a
+#define EIC7700_HSP_NR_CLKS (EIC7700_HSP_CLK_GATE_SATA + 1)
+
+struct eic7700_hsp_clk_gate {
+ struct clk_hw hw;
+ unsigned int id;
+ void __iomem *reg;
+ void __iomem *ref_reg;
+ const char *name;
+ const struct clk_parent_data *parent_data;
+ unsigned long flags;
+ unsigned long offset;
+ unsigned long ref_offset;
+ u8 bit_idx;
+ u8 gate_flags;
+ spinlock_t *lock; /* protect register read-modify-write cycle */
+};
+
+/*
+ * The USB clock gate (hsp_clk_gate_endisable) and the reset driver both
+ * perform read-modify-write cycles on registers 0x800 and 0x900. Use
+ * custom regmap lock callbacks so that regmap operations hold data->lock
+ * with IRQs disabled, the same lock the clock gate path uses, preventing
+ * concurrent RMW races on those shared registers.
+ */
+struct eic7700_hsp_regmap_lock {
+ spinlock_t *lock; /* protect register read-modify-write cycle */
+ unsigned long flags;
+};
+
+static void eic7700_hsp_regmap_lock_fn(void *arg)
+{
+ struct eic7700_hsp_regmap_lock *ctx = arg;
+
+ spin_lock_irqsave(ctx->lock, ctx->flags);
+}
+
+static void eic7700_hsp_regmap_unlock_fn(void *arg)
+{
+ struct eic7700_hsp_regmap_lock *ctx = arg;
+
+ spin_unlock_irqrestore(ctx->lock, ctx->flags);
+}
+
+static inline struct eic7700_hsp_clk_gate *to_gate_clk(struct clk_hw *hw)
+{
+ return container_of(hw, struct eic7700_hsp_clk_gate, hw);
+}
+
+#define EIC7700_HSP_GATE(_id, _name, _pdata, _flags, _offset, _idx, \
+ _ref_offset) \
+ { \
+ .id = _id, \
+ .name = _name, \
+ .parent_data = _pdata, \
+ .flags = _flags, \
+ .offset = _offset, \
+ .ref_offset = _ref_offset, \
+ .bit_idx = _idx, \
+ }
+
+static void hsp_clk_gate_endisable(struct clk_hw *hw, int enable)
+{
+ struct eic7700_hsp_clk_gate *gate = to_gate_clk(hw);
+ u32 reg;
+
+ guard(spinlock_irqsave)(gate->lock);
+
+ reg = readl(gate->reg);
+
+ if (enable)
+ reg |= BIT(gate->bit_idx);
+ else
+ reg &= ~BIT(gate->bit_idx);
+
+ /*
+ * Hardware bug: The reference clock is 24MHz, but the reference clock
+ * register reset to an incorrect default value.
+ * Workaround: Rewrite the correct value before enabling/disabling
+ * the gate clock.
+ */
+ writel(USB_REF_XTAL24M, gate->ref_reg);
+ writel(reg, gate->reg);
+}
+
+static int hsp_clk_gate_enable(struct clk_hw *hw)
+{
+ hsp_clk_gate_endisable(hw, 1);
+
+ return 0;
+}
+
+static void hsp_clk_gate_disable(struct clk_hw *hw)
+{
+ hsp_clk_gate_endisable(hw, 0);
+}
+
+static int hsp_clk_gate_is_enabled(struct clk_hw *hw)
+{
+ struct eic7700_hsp_clk_gate *gate = to_gate_clk(hw);
+ u32 reg;
+
+ reg = readl(gate->reg);
+ reg &= BIT(gate->bit_idx);
+
+ return reg ? 1 : 0;
+}
+
+static const struct clk_ops hsp_clk_gate_ops = {
+ .enable = hsp_clk_gate_enable,
+ .disable = hsp_clk_gate_disable,
+ .is_enabled = hsp_clk_gate_is_enabled,
+};
+
+static struct clk_hw *
+hsp_clk_register_gate(struct device *dev, unsigned int id, const char *name,
+ const struct clk_parent_data *parent_data,
+ unsigned long flags, void __iomem *reg,
+ void __iomem *ref_reg, u8 bit_idx, u8 clk_gate_flags,
+ spinlock_t *lock)
+{
+ struct eic7700_hsp_clk_gate *gate;
+ struct clk_init_data init = {};
+ struct clk_hw *hw;
+ int ret;
+
+ gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &hsp_clk_gate_ops;
+ init.flags = flags;
+ init.parent_data = parent_data;
+ init.num_parents = 1;
+
+ gate->id = id;
+ gate->reg = reg;
+ gate->ref_reg = ref_reg;
+ gate->bit_idx = bit_idx;
+ gate->gate_flags = clk_gate_flags;
+ gate->lock = lock;
+ gate->hw.init = &init;
+
+ hw = &gate->hw;
+ ret = devm_clk_hw_register(dev, hw);
+ if (ret)
+ hw = ERR_PTR(ret);
+
+ return hw;
+}
+
+static const struct clk_parent_data hsp_cfg[] = {
+ { .index = 0 }
+};
+
+static const struct clk_parent_data hsp_mmc[] = {
+ { .index = 1 }
+};
+
+static const struct clk_parent_data hsp_usb_sata[] = {
+ { .index = 2 }
+};
+
+static struct eswin_fixed_factor_clock eic7700_hsp_factor_clks[] = {
+ ESWIN_FACTOR(EIC7700_HSP_CLK_FAC_CFG_DIV2, "factor_hsp_cfg_div2",
+ hsp_cfg, 1, 2, 0),
+ ESWIN_FACTOR(EIC7700_HSP_CLK_FAC_CFG_DIV4, "factor_hsp_cfg_div4",
+ hsp_cfg, 1, 4, 0),
+ ESWIN_FACTOR(EIC7700_HSP_CLK_FAC_MMC_DIV10, "factor_hsp_mmc_div10",
+ hsp_mmc, 1, 10, 0),
+};
+
+static struct eswin_gate_clock eic7700_hsp_gate_clks[] = {
+ ESWIN_GATE(EIC7700_HSP_CLK_GATE_SATA, "gate_clk_hsp_sata", hsp_usb_sata,
+ CLK_SET_RATE_PARENT, EIC7700_HSP_SATA_REG, 28, 0),
+ ESWIN_GATE(EIC7700_HSP_CLK_GATE_MSHC0_TMR, "gate_clk_hsp_mshc0_tmr",
+ hsp_mmc, CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC0_REG, 8, 0),
+ ESWIN_GATE(EIC7700_HSP_CLK_GATE_MSHC1_TMR, "gate_clk_hsp_mshc1_tmr",
+ hsp_mmc, CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC1_REG, 8, 0),
+ ESWIN_GATE(EIC7700_HSP_CLK_GATE_MSHC2_TMR, "gate_clk_hsp_mshc2_tmr",
+ hsp_mmc, CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC2_REG, 8, 0),
+};
+
+static struct eic7700_hsp_clk_gate eic7700_hsp_spec_gate_clks[] = {
+ EIC7700_HSP_GATE(EIC7700_HSP_CLK_GATE_USB0, "gate_clk_hsp_usb0",
+ hsp_usb_sata, CLK_SET_RATE_PARENT,
+ EIC7700_HSP_USB0_REG, 28, EIC7700_HSP_USB0_REF_REG),
+ EIC7700_HSP_GATE(EIC7700_HSP_CLK_GATE_USB1, "gate_clk_hsp_usb1",
+ hsp_usb_sata, CLK_SET_RATE_PARENT,
+ EIC7700_HSP_USB1_REG, 28, EIC7700_HSP_USB1_REF_REG),
+};
+
+static const struct clk_parent_data mux_mmc_3mux1_p[] = {
+ { .fw_name = "cfg" },
+ { .hw = &eic7700_hsp_factor_clks[0].hw },
+ { .hw = &eic7700_hsp_factor_clks[1].hw },
+};
+
+static const struct clk_parent_data mux_mmc_2mux1_p[] = {
+ { .fw_name = "mmc" },
+ { .hw = &eic7700_hsp_factor_clks[2].hw },
+};
+
+static u32 mux_mmc_3mux1_tbl[] = { 0x0, 0x1, 0x3 };
+
+static struct eswin_mux_clock eic7700_hsp_mux_clks[] = {
+ ESWIN_MUX_TBL(EIC7700_HSP_CLK_MUX_EMMC_3MUX1, "mux_hsp_emmc_3mux1",
+ mux_mmc_3mux1_p, ARRAY_SIZE(mux_mmc_3mux1_p),
+ CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC0_REG, 16, 2, 0,
+ mux_mmc_3mux1_tbl),
+ ESWIN_MUX_TBL(EIC7700_HSP_CLK_MUX_SD0_3MUX1, "mux_hsp_sd0_3mux1",
+ mux_mmc_3mux1_p, ARRAY_SIZE(mux_mmc_3mux1_p),
+ CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC1_REG, 16, 2, 0,
+ mux_mmc_3mux1_tbl),
+ ESWIN_MUX_TBL(EIC7700_HSP_CLK_MUX_SD1_3MUX1, "mux_hsp_sd1_3mux1",
+ mux_mmc_3mux1_p, ARRAY_SIZE(mux_mmc_3mux1_p),
+ CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC2_REG, 16, 2, 0,
+ mux_mmc_3mux1_tbl),
+ ESWIN_MUX(EIC7700_HSP_CLK_MUX_EMMC_CQE_2MUX1, "mux_hsp_emmc_cqe_2mux1",
+ mux_mmc_2mux1_p, ARRAY_SIZE(mux_mmc_2mux1_p),
+ CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC0_REG, 0, 1, 0),
+ ESWIN_MUX(EIC7700_HSP_CLK_MUX_SD0_CQE_2MUX1, "mux_hsp_sd0_cqe_2mux1",
+ mux_mmc_2mux1_p, ARRAY_SIZE(mux_mmc_2mux1_p),
+ CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC1_REG, 0, 1, 0),
+ ESWIN_MUX(EIC7700_HSP_CLK_MUX_SD1_CQE_2MUX1, "mux_hsp_sd1_cqe_2mux1",
+ mux_mmc_2mux1_p, ARRAY_SIZE(mux_mmc_2mux1_p),
+ CLK_SET_RATE_PARENT, EIC7700_HSP_MSHC2_REG, 0, 1, 0),
+};
+
+static struct eswin_clk_info eic7700_hsp_clks[] = {
+ ESWIN_GATE_TYPE(EIC7700_HSP_CLK_GATE_EMMC, "gate_clk_hsp_emmc",
+ EIC7700_HSP_CLK_MUX_EMMC_3MUX1,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ EIC7700_HSP_MSHC0_REG, 24, 0),
+ ESWIN_GATE_TYPE(EIC7700_HSP_CLK_GATE_SD0, "gate_clk_hsp_sd0",
+ EIC7700_HSP_CLK_MUX_SD0_3MUX1,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ EIC7700_HSP_MSHC1_REG, 24, 0),
+ ESWIN_GATE_TYPE(EIC7700_HSP_CLK_GATE_SD1, "gate_clk_hsp_sd1",
+ EIC7700_HSP_CLK_MUX_SD1_3MUX1,
+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+ EIC7700_HSP_MSHC2_REG, 24, 0),
+};
+
+static int eic7700_hsp_clk_probe(struct platform_device *pdev)
+{
+ struct eic7700_hsp_regmap_lock *lock_ctx;
+ struct device *dev = &pdev->dev;
+ struct auxiliary_device *adev;
+ struct eswin_clock_data *data;
+ struct regmap *regmap;
+ struct clk_hw *hw;
+ int i, ret;
+
+ data = eswin_clk_init(pdev, EIC7700_HSP_NR_CLKS);
+ if (IS_ERR(data))
+ return dev_err_probe(dev, PTR_ERR(data),
+ "failed to get clk data!\n");
+
+ lock_ctx = devm_kzalloc(dev, sizeof(*lock_ctx), GFP_KERNEL);
+ if (!lock_ctx)
+ return dev_err_probe(dev, -ENOMEM,
+ "failed to alloc regmap lock ctx\n");
+
+ lock_ctx->lock = &data->lock;
+ const struct regmap_config eic7700_hsp_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .max_register = 0x1ffc,
+ .reg_stride = 4,
+ .lock = eic7700_hsp_regmap_lock_fn,
+ .unlock = eic7700_hsp_regmap_unlock_fn,
+ .lock_arg = lock_ctx,
+ };
+
+ regmap = devm_regmap_init_mmio(dev, data->base,
+ &eic7700_hsp_regmap_config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap),
+ "failed to get regmap!\n");
+
+ ret = eswin_clk_register_fixed_factor(dev, eic7700_hsp_factor_clks,
+ ARRAY_SIZE(eic7700_hsp_factor_clks),
+ data);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "failed to register fixed factor clock\n");
+
+ ret = eswin_clk_register_gate(dev, eic7700_hsp_gate_clks,
+ ARRAY_SIZE(eic7700_hsp_gate_clks), data);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "failed to register gate clock\n");
+
+ ret = eswin_clk_register_mux(dev, eic7700_hsp_mux_clks,
+ ARRAY_SIZE(eic7700_hsp_mux_clks),
+ data);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "failed to register mux clock\n");
+
+ ret = eswin_clk_register_clks(dev, eic7700_hsp_clks,
+ ARRAY_SIZE(eic7700_hsp_clks), data);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "failed to register clock\n");
+
+ for (i = 0; i < ARRAY_SIZE(eic7700_hsp_spec_gate_clks); i++) {
+ struct eic7700_hsp_clk_gate *gate;
+
+ gate = &eic7700_hsp_spec_gate_clks[i];
+ hw = hsp_clk_register_gate(dev, gate->id, gate->name,
+ gate->parent_data, gate->flags,
+ data->base + gate->offset,
+ data->base + gate->ref_offset,
+ gate->bit_idx, 0, &data->lock);
+ if (IS_ERR(hw))
+ return dev_err_probe(dev, PTR_ERR(hw),
+ "failed to register gate clock\n");
+
+ data->clk_data.hws[gate->id] = hw;
+ }
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+ &data->clk_data);
+ if (ret)
+ return dev_err_probe(dev, ret, "add clk provider failed\n");
+
+ adev = devm_auxiliary_device_create(dev, "hsp-reset", NULL);
+ if (!adev)
+ return dev_err_probe(dev, -ENODEV,
+ "register hsp-reset device failed\n");
+
+ return 0;
+}
+
+static const struct of_device_id eic7700_hsp_clock_dt_ids[] = {
+ { .compatible = "eswin,eic7700-hspcrg", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, eic7700_hsp_clock_dt_ids);
+
+static struct platform_driver eic7700_hsp_clock_driver = {
+ .probe = eic7700_hsp_clk_probe,
+ .driver = {
+ .name = "eic7700-hsp-clock",
+ .of_match_table = eic7700_hsp_clock_dt_ids,
+ },
+};
+
+module_platform_driver(eic7700_hsp_clock_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Xuyang Dong <dongxuyang@eswincomputing.com>");
+MODULE_DESCRIPTION("ESWIN EIC7700 HSP clock controller driver");
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v2 3/3] reset: eswin: Add eic7700 HSP reset driver
2026-04-20 9:39 [PATCH v2 0/3] Add driver support for ESWIN EIC7700 HSP clock and reset generator dongxuyang
2026-04-20 9:40 ` [PATCH v2 1/3] dt-bindings: clock: Add ESWIN eic7700 " dongxuyang
2026-04-20 9:47 ` [PATCH v2 2/3] clk: eswin: Add eic7700 HSP clock driver dongxuyang
@ 2026-04-20 9:47 ` dongxuyang
2 siblings, 0 replies; 5+ messages in thread
From: dongxuyang @ 2026-04-20 9:47 UTC (permalink / raw)
To: mturquette, sboyd, robh, krzk+dt, conor+dt, linux-clk, devicetree,
linux-kernel, p.zabel, huangyifeng, dongxuyang, benoit.monin,
bmasney
Cc: ningyu, linmin, pinkesh.vaghela
From: Xuyang Dong <dongxuyang@eswincomputing.com>
Add auxiliary driver to support ESWIN EIC7700 high-speed peripherals
system. The reset controller is created using the auxiliary device
framework and set up in the clock driver.
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
drivers/reset/Kconfig | 11 +++
drivers/reset/Makefile | 1 +
drivers/reset/reset-eic7700-hsp.c | 118 ++++++++++++++++++++++++++++++
3 files changed, 130 insertions(+)
create mode 100644 drivers/reset/reset-eic7700-hsp.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index d009eb0849a3..f63e89ed6a4e 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -83,6 +83,17 @@ config RESET_EIC7700
The driver supports eic7700 series chips and provides functionality for
asserting and deasserting resets on the chip.
+config RESET_EIC7700_HSP
+ tristate "EIC7700 HSP Reset controller"
+ depends on ARCH_ESWIN || COMPILE_TEST
+ select AUXILIARY_BUS
+ help
+ This enables the HSP reset controller driver for ESWIN SoCs. This
+ driver is specific to ESWIN SoCs and should only be enabled if using
+ such hardware.
+ The driver supports EIC7700 series chips and provides functionality
+ for asserting and deasserting resets on the chip.
+
config RESET_EYEQ
bool "Mobileye EyeQ reset controller"
depends on EYEQ || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 3e52569bd276..a75af831ef58 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
obj-$(CONFIG_RESET_EIC7700) += reset-eic7700.o
+obj-$(CONFIG_RESET_EIC7700_HSP) += reset-eic7700-hsp.o
obj-$(CONFIG_RESET_EYEQ) += reset-eyeq.o
obj-$(CONFIG_RESET_GPIO) += reset-gpio.o
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
diff --git a/drivers/reset/reset-eic7700-hsp.c b/drivers/reset/reset-eic7700-hsp.c
new file mode 100644
index 000000000000..dde1f9bffa61
--- /dev/null
+++ b/drivers/reset/reset-eic7700-hsp.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * ESWIN EIC7700 HSP Reset Driver
+ *
+ * Authors: Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#include <linux/auxiliary_bus.h>
+#include <linux/device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/reset/eswin,eic7700-hspcrg.h>
+
+/**
+ * struct eic7700_hsp_reset_data - reset controller information structure
+ * @rcdev: reset controller entity
+ * @regmap: regmap handle containing the memory-mapped reset registers
+ */
+struct eic7700_hsp_reset_data {
+ struct reset_controller_dev rcdev;
+ struct regmap *regmap;
+};
+
+struct eic7700_hsp_reg {
+ u32 reg;
+ u32 bit;
+ bool active_low;
+};
+
+static inline struct eic7700_hsp_reset_data *
+to_eic7700_hsp_reset(struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct eic7700_hsp_reset_data, rcdev);
+}
+
+static const struct eic7700_hsp_reg eic7700_hsp_reset[] = {
+ [EIC7700_HSP_RST_SATA_P0] = {0x340, BIT(0), false},
+ [EIC7700_HSP_RST_SATA_PHY] = {0x340, BIT(1), false},
+ [EIC7700_HSP_RST_USB0] = {0x800, BIT(24), true},
+ [EIC7700_HSP_RST_USB1] = {0x900, BIT(24), true},
+ [EIC7700_HSP_RST_USB0_PHY] = {0x800, BIT(25), false},
+ [EIC7700_HSP_RST_USB1_PHY] = {0x900, BIT(25), false},
+};
+
+static int eic7700_hsp_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct eic7700_hsp_reset_data *data = to_eic7700_hsp_reset(rcdev);
+ int ret;
+
+ ret = regmap_assign_bits(data->regmap, eic7700_hsp_reset[id].reg,
+ eic7700_hsp_reset[id].bit,
+ !eic7700_hsp_reset[id].active_low);
+
+ return ret;
+}
+
+static int eic7700_hsp_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct eic7700_hsp_reset_data *data = to_eic7700_hsp_reset(rcdev);
+ int ret;
+
+ ret = regmap_assign_bits(data->regmap, eic7700_hsp_reset[id].reg,
+ eic7700_hsp_reset[id].bit,
+ eic7700_hsp_reset[id].active_low);
+
+ return ret;
+}
+
+static const struct reset_control_ops eic7700_hsp_reset_ops = {
+ .assert = eic7700_hsp_reset_assert,
+ .deassert = eic7700_hsp_reset_deassert,
+};
+
+static int eic7700_hsp_reset_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ struct eic7700_hsp_reset_data *data;
+ struct device *dev = &adev->dev;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->regmap = dev_get_regmap(dev->parent, NULL);
+ if (!data->regmap)
+ return dev_err_probe(dev, -EINVAL, "failed to get regmap!\n");
+
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.ops = &eic7700_hsp_reset_ops;
+ data->rcdev.of_node = dev->parent->of_node;
+ data->rcdev.dev = dev;
+ data->rcdev.nr_resets = ARRAY_SIZE(eic7700_hsp_reset);
+
+ return devm_reset_controller_register(dev, &data->rcdev);
+}
+
+static const struct auxiliary_device_id eic7700_hsp_reset_dt_ids[] = {
+ { .name = "clk_eic7700_hsp.hsp-reset", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(auxiliary, eic7700_hsp_reset_dt_ids);
+
+static struct auxiliary_driver eic7700_hsp_reset_driver = {
+ .probe = eic7700_hsp_reset_probe,
+ .id_table = eic7700_hsp_reset_dt_ids,
+};
+
+module_auxiliary_driver(eic7700_hsp_reset_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Xuyang Dong <dongxuyang@eswincomputing.com>");
+MODULE_DESCRIPTION("ESWIN EIC7700 HSP Reset Controller Driver");
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread