[PATCH v2 00/16] clk: qcom: Tie CX power domains to GCCs

[PATCH v2 00/16] clk: qcom: Tie CX power domains to GCCs

[Abel Vesa]

Tie the CX power domain to GCC clock controller for SM8250, SM8350,
SM8450, SM8550, SM8650, SM8750, Kaanapali, and QCS615.

Also enable the runtime PM in each of the GCC provider drivers.

The existing common GCC schema accepts the standard power-domains property,
so the bindings require no update.

Only Kaanapali requires a Fixes tag, as runtime PM support was not
available when the other platforms were upstreamed.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
Changes in v2:
- Clarify the runtime PM rationale in the GCC driver commit messages.
- Picked up Konrad's R-b tag for the dts patches.
- Link to v1: https://patch.msgid.link/20260819-qcom-tie-cx-to-gcc-v1-0-840034124e73@oss.qualcomm.com

---
Abel Vesa (16):
      clk: qcom: gcc-sm8250: Tie the CX power domain to controller
      clk: qcom: gcc-sm8350: Tie the CX power domain to controller
      clk: qcom: gcc-sm8450: Tie the CX power domain to controller
      clk: qcom: gcc-sm8550: Tie the CX power domain to controller
      clk: qcom: gcc-sm8650: Tie the CX power domain to controller
      clk: qcom: gcc-sm8750: Tie the CX power domain to controller
      clk: qcom: gcc-kaanapali: Tie the CX power domain to controller
      clk: qcom: gcc-qcs615: Tie the CX power domain to controller
      arm64: dts: qcom: sm8250: Add GCC CX power domain
      arm64: dts: qcom: sm8350: Add GCC CX power domain
      arm64: dts: qcom: sm8450: Add GCC CX power domain
      arm64: dts: qcom: sm8550: Add GCC CX power domain
      arm64: dts: qcom: sm8650: Add GCC CX power domain
      arm64: dts: qcom: sm8750: Add GCC CX power domain
      arm64: dts: qcom: kaanapali: Add GCC CX power domain
      arm64: dts: qcom: talos: Add GCC CX power domain

 arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2 ++
 arch/arm64/boot/dts/qcom/sm8250.dtsi    | 1 +
 arch/arm64/boot/dts/qcom/sm8350.dtsi    | 1 +
 arch/arm64/boot/dts/qcom/sm8450.dtsi    | 1 +
 arch/arm64/boot/dts/qcom/sm8550.dtsi    | 1 +
 arch/arm64/boot/dts/qcom/sm8650.dtsi    | 2 ++
 arch/arm64/boot/dts/qcom/sm8750.dtsi    | 2 ++
 arch/arm64/boot/dts/qcom/talos.dtsi     | 2 ++
 drivers/clk/qcom/gcc-kaanapali.c        | 1 +
 drivers/clk/qcom/gcc-qcs615.c           | 1 +
 drivers/clk/qcom/gcc-sm8250.c           | 1 +
 drivers/clk/qcom/gcc-sm8350.c           | 1 +
 drivers/clk/qcom/gcc-sm8450.c           | 1 +
 drivers/clk/qcom/gcc-sm8550.c           | 1 +
 drivers/clk/qcom/gcc-sm8650.c           | 1 +
 drivers/clk/qcom/gcc-sm8750.c           | 1 +
 16 files changed, 20 insertions(+)
---
base-commit: 5453bc3279e9f8578ac3e534d476240e40c879e1
change-id: 20260819-qcom-tie-cx-to-gcc-67e6697639b5

Best regards,
--  
Abel Vesa <abel.vesa@oss.qualcomm.com>

[PATCH v2 01/16] clk: qcom: gcc-sm8250: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8250.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c
index 1c59d70e0f96..86c2be3804c1 100644
--- a/drivers/clk/qcom/gcc-sm8250.c
+++ b/drivers/clk/qcom/gcc-sm8250.c
@@ -3618,6 +3618,7 @@ static const struct qcom_cc_desc gcc_sm8250_desc = {
 	.resets = gcc_sm8250_resets,
 	.num_resets = ARRAY_SIZE(gcc_sm8250_resets),
 	.gdscs = gcc_sm8250_gdscs,
+	.use_rpm = true,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8250_gdscs),
 };
 

-- 
2.54.0

Re: [PATCH v2 01/16] clk: qcom: gcc-sm8250: Tie the CX power domain to controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The patch's intended power savings are defeated because `gcc_cpuss_ahb_clk` is flagged `CLK_IS_CRITICAL`, permanently holding a runtime PM reference and preventing the CX domain from powering down.
--

--- Patch [1]: [PATCH v2 01/16] clk: qcom: gcc-sm8250: Tie the CX power domain to controller ---
commit e29c0e17d3927082fc53c778fba9e97b8d02b015
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-sm8250: Tie the CX power domain to controller

This commit enables runtime PM for the GCC controller. The intention is to
allow the CX power domain to be powered down once all GCC consumers release
their clocks and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c
> --- a/drivers/clk/qcom/gcc-sm8250.c
> +++ b/drivers/clk/qcom/gcc-sm8250.c
> @@ -3618,6 +3618,7 @@ static const struct qcom_cc_desc gcc_sm8250_desc = {
>  	.resets = gcc_sm8250_resets,
>  	.num_resets = ARRAY_SIZE(gcc_sm8250_resets),
>  	.gdscs = gcc_sm8250_gdscs,
> +	.use_rpm = true,

[Severity: Medium]
Does this actually allow the controller to power down in practice?

Looking at gcc_cpuss_ahb_clk in this driver, it is registered with the
CLK_IS_CRITICAL flag:

static struct clk_branch gcc_cpuss_ahb_clk = {
        ...
        .clkr = {
                .hw.init = &(struct clk_init_data){
                        .name = "gcc_cpuss_ahb_clk",
                        .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
                        ...
                },
        },
};

When the clock core prepares a critical clock during registration, it calls
clk_pm_runtime_get(), which permanently increments the runtime PM usage
counter for the GCC controller device. Because a critical clock is never
unprepared, this runtime PM reference is held forever.

Will the device's PM usage counter ever be able to reach 0 to allow the
CX domain to power down, or does the critical clock structurally block the
intended power savings?

>  	.num_gdscs = ARRAY_SIZE(gcc_sm8250_gdscs),
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260820-qcom-tie-cx-to-gcc-v2-0-e67ea30d8b7b@oss.qualcomm.com?part=1

Re: [PATCH v2 01/16] clk: qcom: gcc-sm8250: Tie the CX power domain to controller

[Konrad Dybcio]

On 8/20/26 12:07 PM, Abel Vesa wrote:
> Enable runtime PM for the controller, allowing CX to be powered down
> once all GCC consumers have released their clocks and GDSCs.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH v2 02/16] clk: qcom: gcc-sm8350: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8350.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
index 2d94f3046b71..996ee8592fab 100644
--- a/drivers/clk/qcom/gcc-sm8350.c
+++ b/drivers/clk/qcom/gcc-sm8350.c
@@ -3786,6 +3786,7 @@ static const struct qcom_cc_desc gcc_sm8350_desc = {
 	.resets = gcc_sm8350_resets,
 	.num_resets = ARRAY_SIZE(gcc_sm8350_resets),
 	.gdscs = gcc_sm8350_gdscs,
+	.use_rpm = true,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8350_gdscs),
 };
 

-- 
2.54.0

Re: [PATCH v2 02/16] clk: qcom: gcc-sm8350: Tie the CX power domain to controller

[Konrad Dybcio]

On 8/20/26 12:07 PM, Abel Vesa wrote:
> Enable runtime PM for the controller, allowing CX to be powered down
> once all GCC consumers have released their clocks and GDSCs.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH v2 03/16] clk: qcom: gcc-sm8450: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8450.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c
index b18bb34889ab..b3ab458048dc 100644
--- a/drivers/clk/qcom/gcc-sm8450.c
+++ b/drivers/clk/qcom/gcc-sm8450.c
@@ -3399,6 +3399,7 @@ static const struct qcom_cc_desc gcc_sm8450_desc = {
 	.resets = gcc_sm8450_resets,
 	.num_resets = ARRAY_SIZE(gcc_sm8450_resets),
 	.gdscs = gcc_sm8450_gdscs,
+	.use_rpm = true,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8450_gdscs),
 };
 

-- 
2.54.0

Re: [PATCH v2 03/16] clk: qcom: gcc-sm8450: Tie the CX power domain to controller

[Konrad Dybcio]

On 8/20/26 12:07 PM, Abel Vesa wrote:
> Enable runtime PM for the controller, allowing CX to be powered down
> once all GCC consumers have released their clocks and GDSCs.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH v2 04/16] clk: qcom: gcc-sm8550: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8550.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c
index 36a5b7de5b55..427ae9cf28c1 100644
--- a/drivers/clk/qcom/gcc-sm8550.c
+++ b/drivers/clk/qcom/gcc-sm8550.c
@@ -3326,6 +3326,7 @@ static const struct qcom_cc_desc gcc_sm8550_desc = {
 	.resets = gcc_sm8550_resets,
 	.num_resets = ARRAY_SIZE(gcc_sm8550_resets),
 	.gdscs = gcc_sm8550_gdscs,
+	.use_rpm = true,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8550_gdscs),
 };
 

-- 
2.54.0

Re: [PATCH v2 04/16] clk: qcom: gcc-sm8550: Tie the CX power domain to controller

[Konrad Dybcio]

On 8/20/26 12:07 PM, Abel Vesa wrote:
> Enable runtime PM for the controller, allowing CX to be powered down
> once all GCC consumers have released their clocks and GDSCs.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH v2 05/16] clk: qcom: gcc-sm8650: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8650.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c
index f7e2d7ec60c9..b5cd4e3917b7 100644
--- a/drivers/clk/qcom/gcc-sm8650.c
+++ b/drivers/clk/qcom/gcc-sm8650.c
@@ -3784,6 +3784,7 @@ static const struct qcom_cc_desc gcc_sm8650_desc = {
 	.resets = gcc_sm8650_resets,
 	.num_resets = ARRAY_SIZE(gcc_sm8650_resets),
 	.gdscs = gcc_sm8650_gdscs,
+	.use_rpm = true,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8650_gdscs),
 };
 

-- 
2.54.0

Re: [PATCH v2 05/16] clk: qcom: gcc-sm8650: Tie the CX power domain to controller

[Konrad Dybcio]

On 8/20/26 12:07 PM, Abel Vesa wrote:
> Enable runtime PM for the controller, allowing CX to be powered down
> once all GCC consumers have released their clocks and GDSCs.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH v2 06/16] clk: qcom: gcc-sm8750: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8750.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8750.c b/drivers/clk/qcom/gcc-sm8750.c
index 6cfe90122268..a4a3ece74f40 100644
--- a/drivers/clk/qcom/gcc-sm8750.c
+++ b/drivers/clk/qcom/gcc-sm8750.c
@@ -3195,6 +3195,7 @@ static const struct qcom_cc_desc gcc_sm8750_desc = {
 	.resets = gcc_sm8750_resets,
 	.num_resets = ARRAY_SIZE(gcc_sm8750_resets),
 	.gdscs = gcc_sm8750_gdscs,
+	.use_rpm = true,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8750_gdscs),
 };
 

-- 
2.54.0

Re: [PATCH v2 06/16] clk: qcom: gcc-sm8750: Tie the CX power domain to controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The reset controller operations lack runtime PM protection, allowing unpowered register accesses and potential system crashes.
--

--- Patch [6]: [PATCH v2 06/16] clk: qcom: gcc-sm8750: Tie the CX power domain to controller ---
commit 9120e413d73e4cfcd0de420eacf417424a6d9257
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-sm8750: Tie the CX power domain to controller

This commit enables runtime PM for the controller, allowing the CX power
domain to be powered down once all GCC consumers have released their clocks
and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-sm8750.c b/drivers/clk/qcom/gcc-sm8750.c
> index 6cfe90122268a..a4a3ece74f401 100644
> --- a/drivers/clk/qcom/gcc-sm8750.c
> +++ b/drivers/clk/qcom/gcc-sm8750.c
> @@ -3195,6 +3195,7 @@ static const struct qcom_cc_desc gcc_sm8750_desc = {
>  	.resets = gcc_sm8750_resets,
>  	.num_resets = ARRAY_SIZE(gcc_sm8750_resets),
>  	.gdscs = gcc_sm8750_gdscs,
> +	.use_rpm = true,

[Severity: High]
Does enabling runtime PM here expose the reset controller operations to
unpowered register accesses?

If a consumer driver (such as a PHY driver) asserts or deasserts a reset
provided by the GCC controller before it enables a clock, the GCC device
might be suspended and the CX power domain turned off. 

Looking at drivers/clk/qcom/reset.c, qcom_reset_set_assert() performs
register access via regmap_update_bits() without acquiring a runtime PM
reference on the GCC device:

drivers/clk/qcom/reset.c:qcom_reset_set_assert() {
    ...
    return regmap_update_bits(rst->regmap, map->reg, map->bit, map->bit);
}

Can this sequence cause a synchronous external abort or kernel crash when
the hardware registers are accessed while the power domain is suspended?

>  	.num_gdscs = ARRAY_SIZE(gcc_sm8750_gdscs),
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260820-qcom-tie-cx-to-gcc-v2-0-e67ea30d8b7b@oss.qualcomm.com?part=6

Re: [PATCH v2 06/16] clk: qcom: gcc-sm8750: Tie the CX power domain to controller

[Konrad Dybcio]

On 8/20/26 12:07 PM, Abel Vesa wrote:
> Enable runtime PM for the controller, allowing CX to be powered down
> once all GCC consumers have released their clocks and GDSCs.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH v2 07/16] clk: qcom: gcc-kaanapali: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Fixes: d1919c375f21 ("clk: qcom: Add support for Global clock controller on Kaanapali")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-kaanapali.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-kaanapali.c b/drivers/clk/qcom/gcc-kaanapali.c
index 5bcbcd178657..c40d2da1086a 100644
--- a/drivers/clk/qcom/gcc-kaanapali.c
+++ b/drivers/clk/qcom/gcc-kaanapali.c
@@ -3502,6 +3502,7 @@ static const struct qcom_cc_desc gcc_kaanapali_desc = {
 	.num_resets = ARRAY_SIZE(gcc_kaanapali_resets),
 	.gdscs = gcc_kaanapali_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_kaanapali_gdscs),
+	.use_rpm = true,
 	.driver_data = &gcc_kaanapali_driver_data,
 };
 

-- 
2.54.0

Re: [PATCH v2 07/16] clk: qcom: gcc-kaanapali: Tie the CX power domain to controller

[Konrad Dybcio]

On 8/20/26 12:07 PM, Abel Vesa wrote:
> Enable runtime PM for the controller, allowing CX to be powered down
> once all GCC consumers have released their clocks and GDSCs.
> 
> Fixes: d1919c375f21 ("clk: qcom: Add support for Global clock controller on Kaanapali")
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH v2 08/16] clk: qcom: gcc-qcs615: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-qcs615.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-qcs615.c b/drivers/clk/qcom/gcc-qcs615.c
index 57f8c80c6f32..601c81c84450 100644
--- a/drivers/clk/qcom/gcc-qcs615.c
+++ b/drivers/clk/qcom/gcc-qcs615.c
@@ -2967,6 +2967,7 @@ static const struct qcom_cc_desc gcc_qcs615_desc = {
 	.resets = gcc_qcs615_resets,
 	.num_resets = ARRAY_SIZE(gcc_qcs615_resets),
 	.gdscs = gcc_qcs615_gdscs,
+	.use_rpm = true,
 	.num_gdscs = ARRAY_SIZE(gcc_qcs615_gdscs),
 };
 

-- 
2.54.0

Re: [PATCH v2 08/16] clk: qcom: gcc-qcs615: Tie the CX power domain to controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Unclocked register access during reset assertion because qcom_reset_ops do not wake the device from RPM suspend.
--

--- Patch [8]: [PATCH v2 08/16] clk: qcom: gcc-qcs615: Tie the CX power domain to controller ---
commit c06f319be5cd4791e28ad1c311d665bbd4af3230
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

clk: qcom: gcc-qcs615: Tie the CX power domain to controller
    
Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-qcs615.c b/drivers/clk/qcom/gcc-qcs615.c
> index 57f8c80c6f324..601c81c844505 100644
> --- a/drivers/clk/qcom/gcc-qcs615.c
> +++ b/drivers/clk/qcom/gcc-qcs615.c
> @@ -2967,6 +2967,7 @@ static const struct qcom_cc_desc gcc_qcs615_desc = {
>  	.resets = gcc_qcs615_resets,
>  	.num_resets = ARRAY_SIZE(gcc_qcs615_resets),
>  	.gdscs = gcc_qcs615_gdscs,
> +	.use_rpm = true,

[Severity: High]
Will enabling runtime PM here cause unclocked register accesses during reset 
assertions?

When use_rpm is set to true, the GCC controller can be runtime suspended. If a 
consumer device driver calls reset_control_assert() before enabling its clocks, 
the underlying reset callback executes a register write without first waking up 
the GCC device.

Looking at the qcom reset operations:

drivers/clk/qcom/reset.c:qcom_reset_set_assert() {
    ...
    regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0);

    /* Read back the register to ensure write completion, ignore the value */
    regmap_read(rst->regmap, map->reg, &mask);
    ...
}

Since there is no pm_runtime_resume_and_get() or similar mechanism to wake the 
controller before the regmap_update_bits() call, will this write to a powered-off 
MMIO space and trigger a synchronous external abort?

>  	.num_gdscs = ARRAY_SIZE(gcc_qcs615_gdscs),
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260820-qcom-tie-cx-to-gcc-v2-0-e67ea30d8b7b@oss.qualcomm.com?part=8

Re: [PATCH v2 08/16] clk: qcom: gcc-qcs615: Tie the CX power domain to controller

[Konrad Dybcio]

On 8/20/26 12:07 PM, Abel Vesa wrote:
> Enable runtime PM for the controller, allowing CX to be powered down
> once all GCC consumers have released their clocks and GDSCs.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH v2 09/16] arm64: dts: qcom: sm8250: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8250 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 90f8b091634e..50790cf1c3ca 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -971,6 +971,7 @@ gcc: clock-controller@100000 {
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&rpmhcc RPMH_CXO_CLK_A>,
 				 <&sleep_clk>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 		};
 
 		ipcc: mailbox@408000 {

-- 
2.54.0

Re: [PATCH v2 09/16] arm64: dts: qcom: sm8250: Add GCC CX power domain

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] DT Binding Violation: The `power-domains` property is added to the `gcc` node but is not documented in the corresponding `qcom,gcc-sm8250.yaml` DT binding schema.
--

--- Patch [9]: [PATCH v2 09/16] arm64: dts: qcom: sm8250: Add GCC CX power domain ---
commit 734b5cf106da5d46876e8b4bb05d32739432959a
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

arm64: dts: qcom: sm8250: Add GCC CX power domain

This commit adds the RPMh CX power domain reference to the GCC node in the
SM8250 device tree. This ensures that votes from GCC GDSC consumers properly
propagate to the RPMh CX domain.

> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 90f8b091634e9..50790cf1c3ca1 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -971,6 +971,7 @@ gcc: clock-controller@100000 {
>  			clocks = <&rpmhcc RPMH_CXO_CLK>,
>  				 <&rpmhcc RPMH_CXO_CLK_A>,
>  				 <&sleep_clk>;
> +			power-domains = <&rpmhpd RPMHPD_CX>;

[Severity: Low]
Will running make dtbs_check produce a validation warning for this new
property?

Looking at Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml, the
binding enforces unevaluatedProperties: false but does not explicitly declare
power-domains.

Should the binding schema be updated alongside this change to allow
power-domains so we avoid build validation failures?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260820-qcom-tie-cx-to-gcc-v2-0-e67ea30d8b7b@oss.qualcomm.com?part=9

[PATCH v2 10/16] arm64: dts: qcom: sm8350: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8350 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 32b47f5ec1f6..84012a407c4b 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -699,6 +699,7 @@ gcc: clock-controller@100000 {
 				 <&ufs_mem_phy 2>,
 				 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 				 <0>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 		};
 
 		ipcc: mailbox@408000 {

-- 
2.54.0

Re: [PATCH v2 10/16] arm64: dts: qcom: sm8350: Add GCC CX power domain

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Missing 'power-domains' declaration in the qcom,gcc-sm8350.yaml device tree binding schema.
--

--- Patch [10]: [PATCH v2 10/16] arm64: dts: qcom: sm8350: Add GCC CX power domain ---
commit da0614dca1afbc3aae13d37f6ec085e9fcaa4394
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

arm64: dts: qcom: sm8350: Add GCC CX power domain

This commit updates the sm8350 devicetree to add the RPMh CX power domain
reference to the GCC clock controller node. This allows votes from GCC GDSC
consumers to properly propagate to RPMh CX.

> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 32b47f5ec1f67..84012a407c4be 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -699,6 +699,7 @@ gcc: clock-controller@100000 {
>  				 <&ufs_mem_phy 2>,
>  				 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
>  				 <0>;
> +			power-domains = <&rpmhpd RPMHPD_CX>;

[Severity: Low]
Should this new property also be declared in the corresponding device tree
binding schema?

Looking at Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml,
adding the power-domains property to the devicetree node without explicitly
listing it in the binding schema's properties block can leave it unconstrained
and trigger an undocumented property warning during dtbs_check.

>  		};
>  
>  		ipcc: mailbox@408000 {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260820-qcom-tie-cx-to-gcc-v2-0-e67ea30d8b7b@oss.qualcomm.com?part=10

[PATCH v2 11/16] arm64: dts: qcom: sm8450: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8450 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index b8793482b181..176cced72245 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -942,6 +942,7 @@ gcc: clock-controller@100000 {
 				      "ufs_phy_rx_symbol_1_clk",
 				      "ufs_phy_tx_symbol_0_clk",
 				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+			power-domains = <&rpmhpd RPMHPD_CX>;
 		};
 
 		gpi_dma2: dma-controller@800000 {

-- 
2.54.0

[PATCH v2 12/16] arm64: dts: qcom: sm8550: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8550 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 0e701e709235..7137efb45346 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1195,6 +1195,7 @@ gcc: clock-controller@100000 {
 				 <&ufs_mem_phy 1>,
 				 <&ufs_mem_phy 2>,
 				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 		};
 
 		ipcc: mailbox@408000 {

-- 
2.54.0

[PATCH v2 13/16] arm64: dts: qcom: sm8650: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8650 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index b679fd8afb7d..962797c15abf 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2019,6 +2019,8 @@ gcc: clock-controller@100000 {
 				 <&ufs_mem_phy 2>,
 				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 
+			power-domains = <&rpmhpd RPMHPD_CX>;
+
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;

-- 
2.54.0

Re: [PATCH v2 13/16] arm64: dts: qcom: sm8650: Add GCC CX power domain

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `power-domains` property is added to the SM8650 GCC device tree node without updating the corresponding binding schema, which will cause validation failures.
--

--- Patch [13]: [PATCH v2 13/16] arm64: dts: qcom: sm8650: Add GCC CX power domain ---
commit 2cea18fb279f0e36930dd295a87712e624b1a701
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

arm64: dts: qcom: sm8650: Add GCC CX power domain

This commit adds the RPMh CX power domain reference to the GCC node on
SM8650. This ensures that the required CX vote is held when consumers
enable their local GCC-provided GDSCs.

> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index b679fd8afb7d5..962797c15abf5 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -2019,6 +2019,8 @@ gcc: clock-controller@100000 {
>  				 <&ufs_mem_phy 2>,
>  				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
>  
> +			power-domains = <&rpmhpd RPMHPD_CX>;

[Severity: Low]
Will this new property cause dtbs_check validation failures?

Looking at Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml, the
schema enforces unevaluatedProperties: false. Does the binding schema also
need to be updated alongside this change to explicitly define and permit
the power-domains property for this node?

> +
>  			#clock-cells = <1>;
>  			#reset-cells = <1>;
>  			#power-domain-cells = <1>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260820-qcom-tie-cx-to-gcc-v2-0-e67ea30d8b7b@oss.qualcomm.com?part=13

[PATCH v2 14/16] arm64: dts: qcom: sm8750: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8750 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index dd738d13df8e..cda18d4dc6a1 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -676,6 +676,8 @@ gcc: clock-controller@100000 {
 				 <0>,
 				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 
+			power-domains = <&rpmhpd RPMHPD_CX>;
+
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;

-- 
2.54.0

[PATCH v2 15/16] arm64: dts: qcom: kaanapali: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on Kaanapali are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Fixes: 2eeb5767d53f ("arm64: dts: qcom: Introduce Kaanapali SoC")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 131fd2a16c54..c1528cc8b7b3 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -552,6 +552,8 @@ gcc: clock-controller@100000 {
 				 <&ufs_mem_phy 2>,
 				 <0>;
 
+			power-domains = <&rpmhpd RPMHPD_CX>;
+
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;

-- 
2.54.0

[PATCH v2 16/16] arm64: dts: qcom: talos: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on QCS615 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/talos.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index eedfdce3c479..06ca54acf565 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -706,6 +706,8 @@ gcc: clock-controller@100000 {
 				      "bi_tcxo_ao",
 				      "sleep_clk";
 
+			power-domains = <&rpmhpd RPMHPD_CX>;
+
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;

-- 
2.54.0

Re: [PATCH v2 16/16] arm64: dts: qcom: talos: Add GCC CX power domain

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `power-domains` property is added to the QCS615 GCC device tree node, but the corresponding YAML dt-binding schema was not updated to allow it.
--

--- Patch [16]: [PATCH v2 16/16] arm64: dts: qcom: talos: Add GCC CX power domain ---
commit 43d59202f59a2d72d12953fe62914471fdc7347f
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>

arm64: dts: qcom: talos: Add GCC CX power domain

This commit adds the RPMh CX power domain reference to the GCC node in
talos.dtsi. This ensures that GCC GDSC consumer votes can propagate
correctly to the required CX power domain.

> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
> index eedfdce3c479e..06ca54acf565f 100644
> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
[ ... ]
> @@ -706,6 +706,8 @@ gcc: clock-controller@100000 {
>  				      "bi_tcxo_ao",
>  				      "sleep_clk";
>  
> +			power-domains = <&rpmhpd RPMHPD_CX>;

[Severity: Low]
Will this new property cause device tree schema validation (make dtbs_check)
to fail?

It looks like the power-domains property is being added here, but the
corresponding dt-binding schema (qcom,qcs615-gcc.yaml) might not have been
updated to allow it. Since the schema typically specifies
unevaluatedProperties: false, adding this property to the dtsi file
without a companion dt-binding update usually introduces a schema violation.

Should there be a companion patch updating the dt-binding YAML?

> +
>  			#clock-cells = <1>;
>  			#reset-cells = <1>;
>  			#power-domain-cells = <1>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260820-qcom-tie-cx-to-gcc-v2-0-e67ea30d8b7b@oss.qualcomm.com?part=16

Re: [PATCH v2 00/16] clk: qcom: Tie CX power domains to GCCs

[Abel Vesa]

On 26-08-20 13:07:03, Abel Vesa wrote:
> Tie the CX power domain to GCC clock controller for SM8250, SM8350,
> SM8450, SM8550, SM8650, SM8750, Kaanapali, and QCS615.
> 
> Also enable the runtime PM in each of the GCC provider drivers.
> 
> The existing common GCC schema accepts the standard power-domains property,
> so the bindings require no update.

Argh, this is actually incorrect.

Bindings need updating.

Will respin.