* [PATCH v2 1/8] clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset
[not found] <20260918150730.122056-1-biju.das.jz@bp.renesas.com>
@ 2026-09-18 15:07 ` Biju Das
2026-09-18 15:23 ` sashiko-bot
0 siblings, 1 reply; 3+ messages in thread
From: Biju Das @ 2026-09-18 15:07 UTC (permalink / raw)
To: Geert Uytterhoeven, Stephen Boyd, Brian Masney, Jerome Brunet
Cc: Biju Das, linux-renesas-soc, linux-clk, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Add clock P20 (PLL2_DIV2/8), module clocks for ADC1 (ADCLK, PCLK)
and TSU (PCLK), along with the corresponding module resets for
ADC1 and TSU on the RZ/G3S (R9A08G046) SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* No change.
---
drivers/clk/renesas/r9a08g046-cpg.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
index 22821321a1d3..2c5ca5ab5f57 100644
--- a/drivers/clk/renesas/r9a08g046-cpg.c
+++ b/drivers/clk/renesas/r9a08g046-cpg.c
@@ -350,6 +350,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
dtable_1_8, 0, 200000000UL, 0, NULL),
DEF_G3S_DIV("P19", R9A08G046_CLK_P19, CLK_SEL_RSPI2, G3L_DIV_RSPI2, G3L_DIV_RSPI2_STS,
dtable_1_8, 0, 200000000UL, 0, NULL),
+ DEF_FIXED("P20", R9A08G046_CLK_P20, CLK_PLL2_DIV2, 1, 8),
DEF_G3S_DIV("SD0", R9A08G046_CLK_SD0, CLK_SEL_SDHI0, G3L_DIV_SDHI0, G3L_DIV_SDHI0_STS,
dtable_1_4, 800000000UL, 600000000UL, CLK_SET_RATE_PARENT,
rzg3s_cpg_div_clk_notifier),
@@ -559,6 +560,12 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
MSTOP(BUS_MCPU2, BIT(0))),
DEF_MOD("gpio_hclk", R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0,
MSTOP(BUS_PERI_CPU, BIT(6))),
+ DEF_MOD("adc1_adclk", R9A08G046_ADC1_ADCLK, R9A08G046_CLK_P20, 0x5a8, 2,
+ MSTOP(BUS_PERI_VIDEO, BIT(14))),
+ DEF_MOD("adc1_pclk", R9A08G046_ADC1_PCLK, R9A08G046_CLK_P20, 0x5a8, 3,
+ MSTOP(BUS_PERI_VIDEO, BIT(14))),
+ DEF_MOD("tsu_pclk", R9A08G046_TSU_PCLK, R9A08G046_CLK_P20, 0x5ac, 0,
+ MSTOP(BUS_PERI_VIDEO, BIT(15))),
DEF_MOD("pci_aclk", R9A08G046_PCI_ACLK, R9A08G046_CLK_P1, 0x608, 0,
MSTOP(BUS_PERI_COM, BIT(10))),
DEF_MOD("pci_clkl1pm", R9A08G046_PCI_CLKL1PM, R9A08G046_CLK_P8, 0x608, 1,
@@ -640,6 +647,9 @@ static const struct rzg2l_reset r9a08g046_resets[] = {
DEF_RST(R9A08G046_GPIO_RSTN, 0x898, 0),
DEF_RST(R9A08G046_GPIO_PORT_RESETN, 0x898, 1),
DEF_RST(R9A08G046_GPIO_SPARE_RESETN, 0x898, 2),
+ DEF_RST(R9A08G046_ADC1_PRESETN, 0x8a8, 2),
+ DEF_RST(R9A08G046_ADC1_ADRST_N, 0x8a8, 3),
+ DEF_RST(R9A08G046_TSU_PRESETN, 0x8ac, 0),
DEF_RST(R9A08G046_PCI_ARESETN, 0x908, 0),
DEF_RST(R9A08G046_RSCI0_PRESETN, 0x918, 0),
DEF_RST(R9A08G046_RSCI1_PRESETN, 0x918, 1),
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2 1/8] clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset
2026-09-18 15:07 ` [PATCH v2 1/8] clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset Biju Das
@ 2026-09-18 15:23 ` sashiko-bot
2026-09-18 15:34 ` Biju Das
0 siblings, 1 reply; 3+ messages in thread
From: sashiko-bot @ 2026-09-18 15:23 UTC (permalink / raw)
To: Biju Das; +Cc: wsa+renesas, linux-clk
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] clk: renesas: incorrect MSTOP bus for ADC1 and TSU clocks
--
commit e17a7f8fc3947f6cab70a435b3bbdc24af6057ce
Author: Biju Das <biju.das.jz@bp.renesas.com>
clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset
This commit adds clock P20, module clocks for ADC1 and TSU, and the
corresponding resets for the RZ/G3S (R9A08G046) SoC.
> diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
> index 22821321a1d37..2c5ca5ab5f578 100644
> --- a/drivers/clk/renesas/r9a08g046-cpg.c
> +++ b/drivers/clk/renesas/r9a08g046-cpg.c
[ ... ]
> @@ -559,6 +560,12 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
> MSTOP(BUS_MCPU2, BIT(0))),
> DEF_MOD("gpio_hclk", R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0,
> MSTOP(BUS_PERI_CPU, BIT(6))),
> + DEF_MOD("adc1_adclk", R9A08G046_ADC1_ADCLK, R9A08G046_CLK_P20, 0x5a8, 2,
> + MSTOP(BUS_PERI_VIDEO, BIT(14))),
> + DEF_MOD("adc1_pclk", R9A08G046_ADC1_PCLK, R9A08G046_CLK_P20, 0x5a8, 3,
> + MSTOP(BUS_PERI_VIDEO, BIT(14))),
> + DEF_MOD("tsu_pclk", R9A08G046_TSU_PCLK, R9A08G046_CLK_P20, 0x5ac, 0,
> + MSTOP(BUS_PERI_VIDEO, BIT(15))),
[Severity: Medium]
Looking at r9a08g046_mod_clks in drivers/clk/renesas/r9a08g046-cpg.c, are
the MSTOP bus assignments for these ADC1 and TSU clocks correct?
Based on similar architecture mapping in RZ/G2L and RZ/G3S (which use
BUS_MCPU2 for these identical register offsets), it seems this code
might be assigning BUS_PERI_VIDEO when it should use BUS_MCPU2.
If these devices actually reside on BUS_MCPU2, could this regression
cause a write to the wrong MSTOP register during initialization or
runtime PM? This might cause the ADC1 and TSU clocks to fail to ungate
while concurrently corrupting bits 14 and 15 of the video module stop
register when the devices are probed.
> DEF_MOD("pci_aclk", R9A08G046_PCI_ACLK, R9A08G046_CLK_P1, 0x608, 0,
> MSTOP(BUS_PERI_COM, BIT(10))),
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260918150730.122056-1-biju.das.jz@bp.renesas.com?part=1
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH v2 1/8] clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset
2026-09-18 15:23 ` sashiko-bot
@ 2026-09-18 15:34 ` Biju Das
0 siblings, 0 replies; 3+ messages in thread
From: Biju Das @ 2026-09-18 15:34 UTC (permalink / raw)
To: sashiko-reviews@lists.linux.dev; +Cc: wsa+renesas, linux-clk@vger.kernel.org
Hi Sashiko,
> -----Original Message-----
> From: sashiko-bot@kernel.org <sashiko-bot@kernel.org>
> Sent: 18 September 2026 16:24
> Subject: Re: [PATCH v2 1/8] clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset
>
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] clk: renesas: incorrect MSTOP bus for ADC1 and TSU clocks
> --
>
> commit e17a7f8fc3947f6cab70a435b3bbdc24af6057ce
> Author: Biju Das <biju.das.jz@bp.renesas.com>
>
> clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset
>
> This commit adds clock P20, module clocks for ADC1 and TSU, and the corresponding resets for the RZ/G3S
> (R9A08G046) SoC.
>
> > diff --git a/drivers/clk/renesas/r9a08g046-cpg.c
> > b/drivers/clk/renesas/r9a08g046-cpg.c
> > index 22821321a1d37..2c5ca5ab5f578 100644
> > --- a/drivers/clk/renesas/r9a08g046-cpg.c
> > +++ b/drivers/clk/renesas/r9a08g046-cpg.c
> [ ... ]
> > @@ -559,6 +560,12 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
> > MSTOP(BUS_MCPU2, BIT(0))),
> > DEF_MOD("gpio_hclk", R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0,
> > MSTOP(BUS_PERI_CPU, BIT(6))),
> > + DEF_MOD("adc1_adclk", R9A08G046_ADC1_ADCLK, R9A08G046_CLK_P20, 0x5a8, 2,
> > + MSTOP(BUS_PERI_VIDEO, BIT(14))),
> > + DEF_MOD("adc1_pclk", R9A08G046_ADC1_PCLK, R9A08G046_CLK_P20, 0x5a8, 3,
> > + MSTOP(BUS_PERI_VIDEO, BIT(14))),
> > + DEF_MOD("tsu_pclk", R9A08G046_TSU_PCLK, R9A08G046_CLK_P20, 0x5ac, 0,
> > + MSTOP(BUS_PERI_VIDEO, BIT(15))),
>
> [Severity: Medium]
> Looking at r9a08g046_mod_clks in drivers/clk/renesas/r9a08g046-cpg.c, are the MSTOP bus assignments for
> these ADC1 and TSU clocks correct?
It is correct as per RZ/G3L hardware manual.
Cheers,
Biju
^ permalink raw reply [flat|nested] 3+ messages in thread
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[not found] <20260918150730.122056-1-biju.das.jz@bp.renesas.com>
2026-09-18 15:07 ` [PATCH v2 1/8] clk: renesas: r9a08g046: Add TSU,ADC1 clocks and reset Biju Das
2026-09-18 15:23 ` sashiko-bot
2026-09-18 15:34 ` Biju Das
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