Re: [PATCH v2 04/11] arm64: renesas: r8a78000: Add FCPV[BI] nodes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] dt-bindings: FCP nodes use out-of-bounds MDLC module indices
- [Low] dts: FCP nodes use unrelated DisplayPort TX clock to bypass validation
--

commit aebdc4ecfb076110896cfa98b567ebc34c287a87
Author: Paul Elder <paul.elder+renesas@ideasonboard.com>

arm64: renesas: r8a78000: Add FCPV[BI] nodes

Add DT nodes for the FCPVB and FCPVI IP cores in the R-Car X5H SoC.

> diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> index 9a07753b22154..2f8886f8b6545 100644
> --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> @@ -1000,6 +1000,78 @@ mdlc_aon: system-controller@c1338000 {
>  			bootph-all;
>  		};
>  
> +		fcpvi0: fcp@c5030000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5030000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;

[Severity: Low]
Is it expected to assign the unrelated DisplayPort TX clock here, and in the
other added FCP nodes?

The rcar-fcp driver ignores this property at runtime because the actual clock is
implicitly acquired via SCMI through the MDLC power domain.

Should the generic renesas,fcp.yaml binding be amended to make the clock
property optional for SoCs where the PM domain handles it implicitly,
instead of providing an unrelated clock to bypass validation?

> +			power-domains = <&mdlc_vio 0x07 0x107>;
> +			resets = <&mdlc_vio 0x107>;

[Severity: Low]
Do these power-domains and resets use out-of-bounds MDLC module indices?

The dt binding documentation in renesas,r8a78000-mdlc.yaml explicitly specifies
a range of 0x00-0xff for module standby and reset indices. However, the newly
added fcpvi0 node uses 0x107.

Does the binding documentation need to be updated to account for the extended
hardware register space?

> +		};
> +
[ ... ]
> +		fcpvb0: fcp@c5038000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5038000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x102>;
> +			resets = <&mdlc_vio 0x102>;

[Severity: Low]
Similarly, does the fcpvb0 node use an out-of-bounds index with 0x102?

> +		};
> +

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260919-epaul-v7-3-rc1-x5h-vsp-fcp-v2-0-dbe9236bfd22@ideasonboard.com?part=4