Re: [PATCH v4 5/8] clk: sunxi-ng: a733: Add bus clocks support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] clk: sunxi-ng: undefined SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT macro
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commit b8d151f394e2b1110ebeb209884fb27f38da1c29
Author: Junhui Liu <junhui.liu@pigmoral.tech>

clk: sunxi-ng: a733: Add bus clocks support

This commit adds the essential bus clocks in the Allwinner A733 CCU,
including AHB, APB0, APB1, APB_UART, and MBUS. The MBUS clock is marked as
critical and sets an update bit requirement.

> diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c
> index 430a535919c65..00c61806c29b3 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c
[ ... ]
> +static const struct clk_parent_data mbus_parents[] = {
> +	{ .hw = &sys_24M_clk.hw },
> +	{ .hw = &pll_periph1_600M_clk.hw },
> +	{ .hw = &pll_ddr_clk.common.hw },
> +	{ .hw = &pll_periph1_480M_clk.common.hw },
> +	{ .hw = &pll_periph1_400M_clk.hw },
> +	{ .hw = &pll_npu_clk.common.hw },
> +};
> +static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x588,
> +					   0, 5,	/* M */
> +					   24, 3,	/* mux */
> +					   BIT(31),	/* gate */
> +					   CLK_IS_CRITICAL,
> +					   CCU_FEATURE_UPDATE_BIT);

[Severity: Low]
Does this cause a compilation failure?

The macro SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT appears to be undefined in the
codebase. Building the kernel with this configuration enabled may result in
a syntax error because the macro expanding the mbus_clk definition is missing.

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Sashiko AI review · https://sashiko.dev/#/patchset/20260921-a733-clk-v4-0-9c184ebe9ac1@pigmoral.tech?part=5