Re: [PATCH v4 7/8] clk: sunxi-ng: a733: Add bus clock gates

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] clk: build failure due to undefined SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT
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commit 6bb15948b143075d4af5280b2df23bac3488c163
Author: Junhui Liu <junhui.liu@pigmoral.tech>

clk: sunxi-ng: a733: Add bus clock gates

This commit adds bus clock gates that control access to the devices'
register interface on the Allwinner A733 SoC. It also marks the ahb-store
and mbus-store clocks as critical.

> diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c
> index 37e5fe1b327c0..1543c2d3f305b 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c
[ ... ]
> @@ -497,9 +509,118 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x588
>  					   BIT(31),	/* gate */
>  					   CLK_IS_CRITICAL,
>  					   CCU_FEATURE_UPDATE_BIT);
> +static const struct clk_hw *mbus_hws[] = { &mbus_clk.common.hw };

[Severity: Low]
Is the SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT macro defined in the current
kernel tree? It looks like this definition for mbus_clk might cause a direct
compilation failure due to the macro being undefined.

[ ... ]
> @@ -734,6 +867,8 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE_FEAT(dram0_clk, "dram0", dram_parents, 0xc
>  					   BIT(31),	/* gate */
>  					   CLK_IS_CRITICAL,
>  					   CCU_FEATURE_UPDATE_BIT);
> +static SUNXI_CCU_GATE_HWS(bus_dram0_clk, "bus-dram0", ahb_hws, 0xc0c,
> +			  BIT(0), CLK_IS_CRITICAL);

[Severity: Low]
Does this dram0_clk definition also rely on the missing macro? It appears
this location will also fail to compile for the same reason.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260921-a733-clk-v4-0-9c184ebe9ac1@pigmoral.tech?part=7