Re: [PATCH 2/2] clk: qcom: Introduce SM8350 VIDEOCC

[Stephen Boyd <sboyd@kernel.org>]

Quoting Konrad Dybcio (2023-04-13 11:44:59)
> diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c
> new file mode 100644
> index 000000000000..186a5bd9e184
> --- /dev/null
> +++ b/drivers/clk/qcom/videocc-sm8350.c
> @@ -0,0 +1,575 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_clock.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,sm8350-videocc.h>
> +#include <dt-bindings/reset/qcom,sm8350-videocc.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "common.h"
> +#include "reset.h"
> +#include "gdsc.h"
> +
> +enum {
> +       DT_BI_TCXO,
> +       DT_BI_TCXO_AO,
> +       DT_SLEEP_CLK,
> +};
> +
> +enum {
> +       P_BI_TCXO,
> +       P_BI_TCXO_AO,
> +       P_SLEEP_CLK,
> +       P_VIDEO_PLL0_OUT_MAIN,
> +       P_VIDEO_PLL1_OUT_MAIN,
> +};
> +
> +static struct pll_vco lucid_5lpe_vco[] = {

const

> +       { 249600000, 1750000000, 0 },
> +};
> +
> +static const struct alpha_pll_config video_pll0_config = {
> +       .l = 0x25,
> +       .alpha = 0x8000,
> +       .config_ctl_val = 0x20485699,
> +       .config_ctl_hi_val = 0x00002261,
> +       .config_ctl_hi1_val = 0x2a9a699c,
> +       .test_ctl_val = 0x00000000,
> +       .test_ctl_hi_val = 0x00000000,
> +       .test_ctl_hi1_val = 0x01800000,
> +       .user_ctl_val = 0x00000000,
> +       .user_ctl_hi_val = 0x00000805,
> +       .user_ctl_hi1_val = 0x00000000,
> +};
> +
> +static struct clk_alpha_pll video_pll0 = {
> +       .offset = 0x42c,
> +       .vco_table = lucid_5lpe_vco,
> +       .num_vco = ARRAY_SIZE(lucid_5lpe_vco),
> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
> +       .clkr = {
> +               .hw.init = &(struct clk_init_data){

const

> +                       .name = "video_pll0",
> +                       .parent_data = &(const struct clk_parent_data){
> +                               .index = DT_BI_TCXO,
> +                       },
> +                       .num_parents = 1,
> +                       .ops = &clk_alpha_pll_lucid_5lpe_ops,
> +               },
[...]
> +
> +static const struct regmap_config video_cc_sm8350_regmap_config = {
> +       .reg_bits = 32,
> +       .reg_stride = 4,
> +       .val_bits = 32,
> +       .max_register = 0x10000,
> +       .fast_io = true,
> +};
> +
> +static struct qcom_cc_desc video_cc_sm8350_desc = {
> +       .config = &video_cc_sm8350_regmap_config,
> +       .clks = video_cc_sm8350_clocks,
> +       .num_clks = ARRAY_SIZE(video_cc_sm8350_clocks),
> +       .resets = video_cc_sm8350_resets,
> +       .num_resets = ARRAY_SIZE(video_cc_sm8350_resets),
> +       .gdscs = video_cc_sm8350_gdscs,
> +       .num_gdscs = ARRAY_SIZE(video_cc_sm8350_gdscs),
> +};
> +
> +static void video_cc_sm8350_pm_runtime_disable(void *data)
> +{
> +       pm_runtime_disable(data);
> +}
> +
> +static int video_cc_sm8350_probe(struct platform_device *pdev)
> +{
> +       struct regmap *regmap;
> +       int ret;
> +
> +       pm_runtime_enable(&pdev->dev);
> +
> +       ret = devm_add_action_or_reset(&pdev->dev, video_cc_sm8350_pm_runtime_disable, &pdev->dev);

devm_pm_runtime_enable()?

> +       if (ret)
> +               return ret;
> +