Re: [PATCH] clk: tegra: super: Fix error handling and resolve unsigned compare warning

[Mikko Perttunen <mperttunen@nvidia.com>]

On Friday, August 29, 2025 10:16 AM Pei Xiao wrote:
> ./drivers/clk/tegra/clk-super.c:156:5-9: WARNING:
>         Unsigned expression compared with zero: rate < 0
> 
> The unsigned long 'rate' variable caused:
> - Incorrect handling of negative errors
> - Compile warning: "Unsigned expression compared with zero"
> 
> Fix by changing to long type and adding req->rate cast.
> 
> Signed-off-by: Pei Xiao <xiaopei01@kylinos.cn>
> ---
>  drivers/clk/tegra/clk-super.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
> index 7ec47942720c..643b3cb83cd0 100644
> --- a/drivers/clk/tegra/clk-super.c
> +++ b/drivers/clk/tegra/clk-super.c
> @@ -147,7 +147,7 @@ static int clk_super_determine_rate(struct clk_hw *hw,
>  {
>  	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
>  	struct clk_hw *div_hw = &super->frac_div.hw;
> -	unsigned long rate;
> +	long rate;
>  
>  	__clk_hw_set_clk(div_hw, hw);
>  
> @@ -156,7 +156,7 @@ static int clk_super_determine_rate(struct clk_hw *hw,
>  	if (rate < 0)
>  		return rate;
>  
> -	req->rate = rate;
> +	req->rate = (unsigned long)rate;
>  	return 0;
>  }
>  
> 

The proper fix for this would be to implement and call div_ops->determine_rate instead of round_rate. With the cast-to-long approach, rates above 2147MHz will incorrectly show as errors. While for this clock in particular I don't think we can reach those rates, I don't think this improves the situation either, as the round_rate implementation invoked here never returns errors.

Mikko