Re: [PATCH v10 01/10] clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs

[Taniya Das <quic_tdas@quicinc.com>]

On 6/27/2025 6:07 PM, Dmitry Baryshkov wrote:
> On 27/06/2025 13:13, Taniya Das wrote:
>>
>>
>> On 6/25/2025 5:17 PM, Dmitry Baryshkov wrote:
>>> On Wed, Jun 25, 2025 at 04:13:26PM +0530, Taniya Das wrote:
>>>> The alpha PLLs which slew to a new frequency at runtime would require
>>>> the PLL to calibrate at the mid point of the VCO. Add the new PLL ops
>>>> which can support the slewing of the PLL to a new frequency.
>>>>
>>>> Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com>
>>>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>>>> ---
>>>>   drivers/clk/qcom/clk-alpha-pll.c | 169 +++++++++++++++++++++++++++
>>>> ++++++++++++
>>>>   drivers/clk/qcom/clk-alpha-pll.h |   1 +
>>>>   2 files changed, 170 insertions(+)
>>>>
>>
>>>> +    /*
>>>> +     * Dynamic pll update will not support switching frequencies
>>>> across
>>>> +     * vco ranges. In those cases fall back to normal alpha set rate.
>>>> +     */
>>>> +    if (curr_vco->val != vco->val)
>>>> +        return clk_alpha_pll_set_rate(hw, rate, parent_rate);
>>>> +
>>>> +    a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
>>>> +
>>>> +    regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
>>>> +    regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll),
>>>> lower_32_bits(a));
>>>> +    regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
>>>> upper_32_bits(a));
>>>
>>> We have code that does this in __clk_alpha_pll_set_rate() and now you
>>> are adding two more copies. Please extract PLL_L_VAL, PLL_ALPHA_VAL and
>>> PLL_USER_CTL / PLL_VCO_MASK into a helper function.
>>>
>>
>> Dmitry, I was thinking of implementing the following as a reusable
>> helper since it can be leveraged by most of the functions. I'd
>> appreciate your suggestions or feedback.
> 
> The code below looks good to me. Please use 'alpha' instead of 'a'.

Thanks, I will use 'alpha' in the next patch.


Taniya