[PATCH v6 0/8] ARM64: juno: add SCPI mailbox protocol, clock and CPUFreq support

[PATCH v6 0/8] ARM64: juno: add SCPI mailbox protocol, clock and CPUFreq support

[Sudeep Holla]

Hi ARM-SoC guys,

It has been on the list for a while and have got all the necessary ACKs.
Can you please pull this series for v4.3 ?

Regards,
Sudeep

This patch series adds support for:
  1. SCPI(System Control and Power Interface) mailbox protocol driver.
     It uses ARM MHU mailbox controller driver on Juno but can work with
     any mailbox controllers using standard mailbox APIs
  2. Add support for clocks provided by SCP firmware through the SCPI
     interface
  3. Using the existing arm_big_little cpufreq driver and the newly
     added SCPI clock driver, it also adds support for CPU DVFS on
     ARM64 JUNO development platforms.

The SCPI protocol document is available @[1],[2]

Changes v5->v6:
	- Minor review comments on clock bindings and clock driver
	- Added all the ACKs necessary

Changes v4->v5:
	- Updated the SCPI clock bindings to correct the clock specifier
	  usage and other minor updates as per review feedback
	- Updated clock driver to use SCPI specifier clock specifier
	  decode function
	- Minor reshuffling in Juno DTS files, no functionality change

Changes v3->v4:
	- Updated the SCPI binding based on MarkR's feedback
	- Updated SCPI clock driver to incorporate Stephen Boyd's review
	  comments + used clk_set_rate_range to limit the clock range
	- Since no major changes are expected in SCPI DT, updated the
	  Juno DTS to support SCPI and dependent device nodes.

Changes v2->v3:
	- Minor fix in SCPI driver and added Tixy's reviewed-by tag
	- Updated scpi clock driver to incorporate all the comments from
	  Stephen
	- Added Viresh's ack

Changes v1->v2:
	- Updated the token handling in scpi driver as per Tixy's
	  suggestion along with other review comments
	- Removed multiple drivers in scpi clock as Lorenzo suggested
	- Added free_opp_table in scpi-cpufreq as Viresh suggested
	- Separated the DT binding document
	- Moved SCPI protocol driver to drivers/firmware

[1] http://community.arm.com/servlet/JiveServlet/download/8401-45-18326/DUI0922B_scp_message_interface.pdf
[2] https://wiki.linaro.org/ARM/Juno?action=AttachFile&do=get&target=DUI0922B_scp_message_interface.pdf
v1: https://lkml.org/lkml/2015/4/27/232
v2: https://lkml.org/lkml/2015/5/14/470
v3: https://lkml.org/lkml/2015/5/27/220
v4: https://lkml.org/lkml/2015/6/8/178
v5: https://lkml.org/lkml/2015/7/23/270

Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-pm@vger.kernel.org

Sudeep Holla (8):
  Documentation: add DT binding for ARM System Control and Power
    Interface(SCPI) protocol
  firmware: add support for ARM System Control and Power Interface(SCPI)
    protocol
  clk: add support for clocks provided by SCP(System Control Processor)
  clk: scpi: add support for cpufreq virtual device
  cpufreq: arm_big_little: add SCPI interface driver
  arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno
  arm64: dts: add CPU topology on Juno
  arm64: dts: add clock support for all the cpus

 Documentation/devicetree/bindings/arm/arm,scpi.txt | 150 +++++
 MAINTAINERS                                        |  10 +
 arch/arm64/boot/dts/arm/juno-base.dtsi             |  54 ++
 arch/arm64/boot/dts/arm/juno-r1.dts                |  32 +
 arch/arm64/boot/dts/arm/juno.dts                   |  32 +
 drivers/clk/Kconfig                                |  10 +
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-scpi.c                             | 325 ++++++++++
 drivers/cpufreq/Kconfig.arm                        |   9 +
 drivers/cpufreq/Makefile                           |   1 +
 drivers/cpufreq/scpi-cpufreq.c                     | 124 ++++
 drivers/firmware/Kconfig                           |  19 +
 drivers/firmware/Makefile                          |   1 +
 drivers/firmware/arm_scpi.c                        | 711 +++++++++++++++++++++
 include/linux/scpi_protocol.h                      |  61 ++
 15 files changed, 1540 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/arm,scpi.txt
 create mode 100644 drivers/clk/clk-scpi.c
 create mode 100644 drivers/cpufreq/scpi-cpufreq.c
 create mode 100644 drivers/firmware/arm_scpi.c
 create mode 100644 include/linux/scpi_protocol.h

-- 
1.9.1

[PATCH v6 3/8] clk: add support for clocks provided by SCP(System Control Processor)

[Sudeep Holla]

On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control. System Control and Power Interface(SCPI) Message Protocol
is defined for the communication between the Application Cores(AP)
and the SCP.

This patch adds support for the clocks provided by SCP using SCPI
protocol.

Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@baylibre.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
Cc: linux-clk@vger.kernel.org
---
 MAINTAINERS            |   1 +
 drivers/clk/Kconfig    |  10 ++
 drivers/clk/Makefile   |   1 +
 drivers/clk/clk-scpi.c | 312 +++++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 324 insertions(+)
 create mode 100644 drivers/clk/clk-scpi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 86bc2d03748f..690122bb4426 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8965,6 +8965,7 @@ M:	Sudeep Holla <sudeep.holla@arm.com>
 L:	linux-arm-kernel@lists.infradead.org
 S:	Maintained
 F:	Documentation/devicetree/bindings/arm/arm,scpi.txt
+F:	drivers/clk/clk-scpi.c
 F:	drivers/firmware/arm_scpi.c
 F:	include/linux/scpi_protocol.h
 
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 42f7120ca9ce..4aec54b90331 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -59,6 +59,16 @@ config COMMON_CLK_RK808
 	  clocked at 32KHz each. Clkout1 is always on, Clkout2 can off
 	  by control register.
 
+config COMMON_CLK_SCPI
+	tristate "Clock driver controlled via SCPI interface"
+	depends on ARM_SCPI_PROTOCOL || COMPILE_TEST
+	  ---help---
+	  This driver provides support for clocks that are controlled
+	  by firmware that implements the SCPI interface.
+
+	  This driver uses SCPI Message Protocol to interact with the
+	  firmware providing all the clock controls.
+
 config COMMON_CLK_SI5351
 	tristate "Clock driver for SiLabs 5351A/B/C"
 	depends on I2C
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index c4cf075a2320..bef9c7064e5b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_COMMON_CLK_PALMAS)		+= clk-palmas.o
 obj-$(CONFIG_CLK_QORIQ)			+= clk-qoriq.o
 obj-$(CONFIG_COMMON_CLK_RK808)		+= clk-rk808.o
 obj-$(CONFIG_COMMON_CLK_S2MPS11)	+= clk-s2mps11.o
+obj-$(CONFIG_COMMON_CLK_SCPI)           += clk-scpi.o
 obj-$(CONFIG_COMMON_CLK_SI5351)		+= clk-si5351.o
 obj-$(CONFIG_COMMON_CLK_SI570)		+= clk-si570.o
 obj-$(CONFIG_COMMON_CLK_CDCE925)	+= clk-cdce925.o
diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c
new file mode 100644
index 000000000000..c0766fdd6dbf
--- /dev/null
+++ b/drivers/clk/clk-scpi.c
@@ -0,0 +1,312 @@
+/*
+ * System Control and Power Interface (SCPI) Protocol based clock driver
+ *
+ * Copyright (C) 2015 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/scpi_protocol.h>
+
+struct scpi_clk {
+	u32 id;
+	struct clk_hw hw;
+	struct scpi_dvfs_info *info;
+	struct scpi_ops *scpi_ops;
+};
+
+#define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw)
+
+static unsigned long scpi_clk_recalc_rate(struct clk_hw *hw,
+					  unsigned long parent_rate)
+{
+	struct scpi_clk *clk = to_scpi_clk(hw);
+
+	return clk->scpi_ops->clk_get_val(clk->id);
+}
+
+static long scpi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+				unsigned long *parent_rate)
+{
+	/*
+	 * We can't figure out what rate it will be, so just return the
+	 * rate back to the caller. scpi_clk_recalc_rate() will be called
+	 * after the rate is set and we'll know what rate the clock is
+	 * running at then.
+	 */
+	return rate;
+}
+
+static int scpi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+			     unsigned long parent_rate)
+{
+	struct scpi_clk *clk = to_scpi_clk(hw);
+
+	return clk->scpi_ops->clk_set_val(clk->id, rate);
+}
+
+static const struct clk_ops scpi_clk_ops = {
+	.recalc_rate = scpi_clk_recalc_rate,
+	.round_rate = scpi_clk_round_rate,
+	.set_rate = scpi_clk_set_rate,
+};
+
+/* find closest match to given frequency in OPP table */
+static int __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigned long rate)
+{
+	int idx;
+	u32 fmin = 0, fmax = ~0, ftmp;
+	const struct scpi_opp *opp = clk->info->opps;
+
+	for (idx = 0; idx < clk->info->count; idx++, opp++) {
+		ftmp = opp->freq;
+		if (ftmp >= (u32)rate) {
+			if (ftmp <= fmax)
+				fmax = ftmp;
+			break;
+		} else if (ftmp >= fmin) {
+			fmin = ftmp;
+		}
+	}
+	return fmax != ~0 ? fmax : fmin;
+}
+
+static unsigned long scpi_dvfs_recalc_rate(struct clk_hw *hw,
+					   unsigned long parent_rate)
+{
+	struct scpi_clk *clk = to_scpi_clk(hw);
+	int idx = clk->scpi_ops->dvfs_get_idx(clk->id);
+	const struct scpi_opp *opp;
+
+	if (idx < 0)
+		return 0;
+
+	opp = clk->info->opps + idx;
+	return opp->freq;
+}
+
+static long scpi_dvfs_round_rate(struct clk_hw *hw, unsigned long rate,
+				 unsigned long *parent_rate)
+{
+	struct scpi_clk *clk = to_scpi_clk(hw);
+
+	return __scpi_dvfs_round_rate(clk, rate);
+}
+
+static int __scpi_find_dvfs_index(struct scpi_clk *clk, unsigned long rate)
+{
+	int idx, max_opp = clk->info->count;
+	const struct scpi_opp *opp = clk->info->opps;
+
+	for (idx = 0; idx < max_opp; idx++, opp++)
+		if (opp->freq == rate)
+			return idx;
+	return -EINVAL;
+}
+
+static int scpi_dvfs_set_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long parent_rate)
+{
+	struct scpi_clk *clk = to_scpi_clk(hw);
+	int ret = __scpi_find_dvfs_index(clk, rate);
+
+	if (ret < 0)
+		return ret;
+	return clk->scpi_ops->dvfs_set_idx(clk->id, (u8)ret);
+}
+
+static const struct clk_ops scpi_dvfs_ops = {
+	.recalc_rate = scpi_dvfs_recalc_rate,
+	.round_rate = scpi_dvfs_round_rate,
+	.set_rate = scpi_dvfs_set_rate,
+};
+
+static const struct of_device_id scpi_clk_match[] = {
+	{ .compatible = "arm,scpi-dvfs-clocks", .data = &scpi_dvfs_ops, },
+	{ .compatible = "arm,scpi-variable-clocks", .data = &scpi_clk_ops, },
+	{}
+};
+
+static struct clk *
+scpi_clk_ops_init(struct device *dev, const struct of_device_id *match,
+		  struct scpi_clk *sclk, const char *name)
+{
+	struct clk_init_data init;
+	struct clk *clk;
+	unsigned long min = 0, max = 0;
+
+	init.name = name;
+	init.flags = CLK_IS_ROOT;
+	init.num_parents = 0;
+	init.ops = match->data;
+	sclk->hw.init = &init;
+	sclk->scpi_ops = get_scpi_ops();
+
+	if (init.ops == &scpi_dvfs_ops) {
+		sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id);
+		if (IS_ERR(sclk->info))
+			return NULL;
+	} else if (init.ops == &scpi_clk_ops) {
+		if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max)
+			return NULL;
+	} else {
+		return NULL;
+	}
+
+	clk = devm_clk_register(dev, &sclk->hw);
+	if (!IS_ERR(clk) && max)
+		clk_set_rate_range(clk, min, max);
+	return clk;
+}
+
+struct scpi_clk_data {
+	struct scpi_clk **clk;
+	unsigned int clk_num;
+};
+
+static struct clk *
+scpi_of_clk_src_get(struct of_phandle_args *clkspec, void *data)
+{
+	struct scpi_clk *sclk;
+	struct scpi_clk_data *clk_data = data;
+	unsigned int idx = clkspec->args[0], count;
+
+	for (count = 0; count < clk_data->clk_num; count++) {
+		sclk = clk_data->clk[count];
+		if (idx == sclk->id)
+			return sclk->hw.clk;
+	}
+
+	return ERR_PTR(-EINVAL);
+}
+
+static int scpi_clk_add(struct device *dev, struct device_node *np,
+			const struct of_device_id *match)
+{
+	struct clk **clks;
+	int idx, count;
+	struct scpi_clk_data *clk_data;
+
+	count = of_property_count_strings(np, "clock-output-names");
+	if (count < 0) {
+		dev_err(dev, "%s: invalid clock output count\n", np->name);
+		return -EINVAL;
+	}
+
+	clk_data = devm_kmalloc(dev, sizeof(*clk_data), GFP_KERNEL);
+	if (!clk_data)
+		return -ENOMEM;
+
+	clk_data->clk_num = count;
+	clk_data->clk = devm_kcalloc(dev, count, sizeof(*clk_data->clk),
+				     GFP_KERNEL);
+	if (!clk_data->clk)
+		return -ENOMEM;
+
+	clks = devm_kcalloc(dev, count, sizeof(*clks), GFP_KERNEL);
+	if (!clks)
+		return -ENOMEM;
+
+	for (idx = 0; idx < count; idx++) {
+		struct scpi_clk *sclk;
+		const char *name;
+		u32 val;
+
+		sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
+		if (!sclk)
+			return -ENOMEM;
+
+		if (of_property_read_string_index(np, "clock-output-names",
+						  idx, &name)) {
+			dev_err(dev, "invalid clock name @ %s\n", np->name);
+			return -EINVAL;
+		}
+
+		if (of_property_read_u32_index(np, "clock-indices",
+					       idx, &val)) {
+			dev_err(dev, "invalid clock index @ %s\n", np->name);
+			return -EINVAL;
+		}
+
+		sclk->id = val;
+
+		clks[idx] = scpi_clk_ops_init(dev, match, sclk, name);
+		if (IS_ERR_OR_NULL(clks[idx]))
+			dev_err(dev, "failed to register clock '%s'\n", name);
+		else
+			dev_dbg(dev, "Registered clock '%s'\n", name);
+		clk_data->clk[idx] = sclk;
+	}
+
+	return of_clk_add_provider(np, scpi_of_clk_src_get, clk_data);
+}
+
+static int scpi_clocks_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *child, *np = dev->of_node;
+
+	for_each_available_child_of_node(np, child)
+		of_clk_del_provider(np);
+	return 0;
+}
+
+static int scpi_clocks_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct device *dev = &pdev->dev;
+	struct device_node *child, *np = dev->of_node;
+	const struct of_device_id *match;
+
+	if (!get_scpi_ops())
+		return -ENXIO;
+
+	for_each_available_child_of_node(np, child) {
+		match = of_match_node(scpi_clk_match, child);
+		if (!match)
+			continue;
+		ret = scpi_clk_add(dev, child, match);
+		if (ret) {
+			scpi_clocks_remove(pdev);
+			return ret;
+		}
+	}
+	return 0;
+}
+
+static const struct of_device_id scpi_clocks_ids[] = {
+	{ .compatible = "arm,scpi-clocks", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, scpi_clocks_id);
+
+static struct platform_driver scpi_clocks_driver = {
+	.driver	= {
+		.name = "scpi_clocks",
+		.of_match_table = scpi_clocks_ids,
+	},
+	.probe = scpi_clocks_probe,
+	.remove = scpi_clocks_remove,
+};
+module_platform_driver(scpi_clocks_driver);
+
+MODULE_AUTHOR("Sudeep Holla <sudeep.holla@arm.com>");
+MODULE_DESCRIPTION("ARM SCPI clock driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

[PATCH v6 4/8] clk: scpi: add support for cpufreq virtual device

[Sudeep Holla]

The clocks for the CPUs are provided by SCP and are managed by this
clock driver. So the cpufreq device needs to be added only after the
clock get registered and removed when this driver is unloaded.

This patch manages the cpufreq virtual device based on the clock
availability.

Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@baylibre.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
Cc: linux-clk@vger.kernel.org
---
 drivers/clk/clk-scpi.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c
index c0766fdd6dbf..b707f276395c 100644
--- a/drivers/clk/clk-scpi.c
+++ b/drivers/clk/clk-scpi.c
@@ -34,6 +34,8 @@ struct scpi_clk {
 
 #define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw)
 
+static struct platform_device *cpufreq_dev;
+
 static unsigned long scpi_clk_recalc_rate(struct clk_hw *hw,
 					  unsigned long parent_rate)
 {
@@ -263,6 +265,11 @@ static int scpi_clocks_remove(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct device_node *child, *np = dev->of_node;
 
+	if (cpufreq_dev) {
+		platform_device_unregister(cpufreq_dev);
+		cpufreq_dev = NULL;
+	}
+
 	for_each_available_child_of_node(np, child)
 		of_clk_del_provider(np);
 	return 0;
@@ -288,6 +295,12 @@ static int scpi_clocks_probe(struct platform_device *pdev)
 			return ret;
 		}
 	}
+	/* Add the virtual cpufreq device */
+	cpufreq_dev = platform_device_register_simple("scpi-cpufreq",
+						      -1, NULL, 0);
+	if (!cpufreq_dev)
+		pr_warn("unable to register cpufreq device");
+
 	return 0;
 }
 
-- 
1.9.1

Re: [PATCH v6 0/8] ARM64: juno: add SCPI mailbox protocol, clock and CPUFreq support

[Liviu Dudau]

On Fri, Jul 31, 2015 at 06:43:03PM +0100, Sudeep Holla wrote:
> Hi ARM-SoC guys,
> 
> It has been on the list for a while and have got all the necessary ACKs.
> Can you please pull this series for v4.3 ?
> 
> Regards,
> Sudeep
> 
> This patch series adds support for:
>   1. SCPI(System Control and Power Interface) mailbox protocol driver.
>      It uses ARM MHU mailbox controller driver on Juno but can work with
>      any mailbox controllers using standard mailbox APIs
>   2. Add support for clocks provided by SCP firmware through the SCPI
>      interface
>   3. Using the existing arm_big_little cpufreq driver and the newly
>      added SCPI clock driver, it also adds support for CPU DVFS on
>      ARM64 JUNO development platforms.

Hi Sudeep,

Is there a branch where I can pull this series from?

Best regards,
Liviu

> 
> The SCPI protocol document is available @[1],[2]
> 
> Changes v5->v6:
> 	- Minor review comments on clock bindings and clock driver
> 	- Added all the ACKs necessary
> 
> Changes v4->v5:
> 	- Updated the SCPI clock bindings to correct the clock specifier
> 	  usage and other minor updates as per review feedback
> 	- Updated clock driver to use SCPI specifier clock specifier
> 	  decode function
> 	- Minor reshuffling in Juno DTS files, no functionality change
> 
> Changes v3->v4:
> 	- Updated the SCPI binding based on MarkR's feedback
> 	- Updated SCPI clock driver to incorporate Stephen Boyd's review
> 	  comments + used clk_set_rate_range to limit the clock range
> 	- Since no major changes are expected in SCPI DT, updated the
> 	  Juno DTS to support SCPI and dependent device nodes.
> 
> Changes v2->v3:
> 	- Minor fix in SCPI driver and added Tixy's reviewed-by tag
> 	- Updated scpi clock driver to incorporate all the comments from
> 	  Stephen
> 	- Added Viresh's ack
> 
> Changes v1->v2:
> 	- Updated the token handling in scpi driver as per Tixy's
> 	  suggestion along with other review comments
> 	- Removed multiple drivers in scpi clock as Lorenzo suggested
> 	- Added free_opp_table in scpi-cpufreq as Viresh suggested
> 	- Separated the DT binding document
> 	- Moved SCPI protocol driver to drivers/firmware
> 
> [1] http://community.arm.com/servlet/JiveServlet/download/8401-45-18326/DUI0922B_scp_message_interface.pdf
> [2] https://wiki.linaro.org/ARM/Juno?action=AttachFile&do=get&target=DUI0922B_scp_message_interface.pdf
> v1: https://lkml.org/lkml/2015/4/27/232
> v2: https://lkml.org/lkml/2015/5/14/470
> v3: https://lkml.org/lkml/2015/5/27/220
> v4: https://lkml.org/lkml/2015/6/8/178
> v5: https://lkml.org/lkml/2015/7/23/270
> 
> Cc: devicetree@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: linux-pm@vger.kernel.org
> 
> Sudeep Holla (8):
>   Documentation: add DT binding for ARM System Control and Power
>     Interface(SCPI) protocol
>   firmware: add support for ARM System Control and Power Interface(SCPI)
>     protocol
>   clk: add support for clocks provided by SCP(System Control Processor)
>   clk: scpi: add support for cpufreq virtual device
>   cpufreq: arm_big_little: add SCPI interface driver
>   arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno
>   arm64: dts: add CPU topology on Juno
>   arm64: dts: add clock support for all the cpus
> 
>  Documentation/devicetree/bindings/arm/arm,scpi.txt | 150 +++++
>  MAINTAINERS                                        |  10 +
>  arch/arm64/boot/dts/arm/juno-base.dtsi             |  54 ++
>  arch/arm64/boot/dts/arm/juno-r1.dts                |  32 +
>  arch/arm64/boot/dts/arm/juno.dts                   |  32 +
>  drivers/clk/Kconfig                                |  10 +
>  drivers/clk/Makefile                               |   1 +
>  drivers/clk/clk-scpi.c                             | 325 ++++++++++
>  drivers/cpufreq/Kconfig.arm                        |   9 +
>  drivers/cpufreq/Makefile                           |   1 +
>  drivers/cpufreq/scpi-cpufreq.c                     | 124 ++++
>  drivers/firmware/Kconfig                           |  19 +
>  drivers/firmware/Makefile                          |   1 +
>  drivers/firmware/arm_scpi.c                        | 711 +++++++++++++++++++++
>  include/linux/scpi_protocol.h                      |  61 ++
>  15 files changed, 1540 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/arm,scpi.txt
>  create mode 100644 drivers/clk/clk-scpi.c
>  create mode 100644 drivers/cpufreq/scpi-cpufreq.c
>  create mode 100644 drivers/firmware/arm_scpi.c
>  create mode 100644 include/linux/scpi_protocol.h
> 
> -- 
> 1.9.1
> 

-- 
====================
| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---------------
    ¯\_(ツ)_/¯

Re: [PATCH v6 0/8] ARM64: juno: add SCPI mailbox protocol, clock and CPUFreq support

[Sudeep Holla]

On 03/08/15 11:18, Liviu Dudau wrote:
> On Fri, Jul 31, 2015 at 06:43:03PM +0100, Sudeep Holla wrote:
>> Hi ARM-SoC guys,
>>
>> It has been on the list for a while and have got all the necessary ACKs.
>> Can you please pull this series for v4.3 ?
>>
>> Regards,
>> Sudeep
>>
>> This patch series adds support for:
>>    1. SCPI(System Control and Power Interface) mailbox protocol driver.
>>       It uses ARM MHU mailbox controller driver on Juno but can work with
>>       any mailbox controllers using standard mailbox APIs
>>    2. Add support for clocks provided by SCP firmware through the SCPI
>>       interface
>>    3. Using the existing arm_big_little cpufreq driver and the newly
>>       added SCPI clock driver, it also adds support for CPU DVFS on
>>       ARM64 JUNO development platforms.
>
> Hi Sudeep,
>
> Is there a branch where I can pull this series from?
>

Yes, you can pull from
git://linux-arm.org/linux-skn.git juno_dvfs

Regards,
Sudeep

Re: [PATCH v6 0/8] ARM64: juno: add SCPI mailbox protocol, clock and CPUFreq support

[Sudeep Holla]

Hi Olof,

On 31/07/15 18:43, Sudeep Holla wrote:
> Hi ARM-SoC guys,
>
> It has been on the list for a while and have got all the necessary
> ACKs. Can you please pull this series for v4.3 ?
>

Can you pull this patch series directly from the mail or do you prefer
pull-request ?

Regards,
Sudeep

Re: [PATCH v6 0/8] ARM64: juno: add SCPI mailbox protocol, clock and CPUFreq support

[Sudeep Holla]

Hi Olof,

On 05/08/15 10:59, Sudeep Holla wrote:
> Hi Olof,
>
> On 31/07/15 18:43, Sudeep Holla wrote:
>> Hi ARM-SoC guys,
>>
>> It has been on the list for a while and have got all the necessary
>> ACKs. Can you please pull this series for v4.3 ?
>>
>
> Can you pull this patch series directly from the mail or do you prefer
> pull-request ?
>

Any issue with this series ? Let me know. I did send a pull request also
but I haven't got any response so far. Sorry for the nag.

Regards,
Sudeep

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