[PATCH 00/12] Add support for the Rockchip RV1106 and RV1103

[PATCH 00/12] Add support for the Rockchip RV1106 and RV1103

[Simon Glass]

This series adds initial support for the Rockchip RV1106, a Cortex-A7
SoC aimed at IP cameras, and its RV1103 package variant, together with
the Luckfox Pico Mini B, a small and widely available RV1103 board.

The series follows the structure of the recently merged RV1103B
support. The clock driver is ported from the vendor kernel and is the
work of Elaine Zhang; the pinctrl data also comes from the vendor
kernel. The clock binding header keeps the vendor clock IDs. As with
the RV1103B, no resets are exposed yet and the CPU pvtpll is
initialised but not calibrated.

The devicetrees cover the devices needed for a basic system: UARTs,
SD/eMMC, the SPI flash controller, SARADC, watchdog, GPIO and pinctrl.

The series is tested on the Luckfox Pico Mini B: the kernel boots to
the rootfs wait with a working console on UART2, timers, pinctrl and
GPIO, and an SD card running at high speed. It builds with W=1 without
warnings and dt_binding_check and dtbs_check are clean.


Simon Glass (12):
  dt-bindings: clock: rockchip: Add RV1106 CRU support
  clk: rockchip: Add clock controller for the RV1106
  dt-bindings: pinctrl: rockchip: Add RV1106 compatible
  pinctrl: rockchip: Add RV1106 pinctrl support
  dt-bindings: soc: rockchip: grf: Add RV1106 compatibles
  dt-bindings: serial: snps-dw-apb-uart: Add RV1106 compatible
  dt-bindings: mmc: rockchip-dw-mshc: Add RV1106 compatible
  dt-bindings: watchdog: snps,dw-wdt: Add RV1106 compatible
  dt-bindings: iio: adc: rockchip-saradc: Add RV1106 compatible
  ARM: dts: rockchip: Add support for RV1106 and RV1103
  dt-bindings: arm: rockchip: Add Luckfox Pico Mini B
  ARM: dts: rockchip: Add Luckfox Pico Mini B

 .../devicetree/bindings/arm/rockchip.yaml     |    5 +
 .../bindings/clock/rockchip,rv1106-cru.yaml   |   59 +
 .../bindings/iio/adc/rockchip-saradc.yaml     |    3 +
 .../bindings/mmc/rockchip-dw-mshc.yaml        |    1 +
 .../bindings/pinctrl/rockchip,pinctrl.yaml    |    1 +
 .../bindings/serial/snps-dw-apb-uart.yaml     |    1 +
 .../devicetree/bindings/soc/rockchip/grf.yaml |   30 +
 .../bindings/watchdog/snps,dw-wdt.yaml        |    1 +
 arch/arm/boot/dts/rockchip/Makefile           |    1 +
 .../rockchip/rv1103-luckfox-pico-mini-b.dts   |   93 ++
 arch/arm/boot/dts/rockchip/rv1103.dtsi        |   12 +
 .../arm/boot/dts/rockchip/rv1106-pinctrl.dtsi | 1398 +++++++++++++++++
 arch/arm/boot/dts/rockchip/rv1106.dtsi        |  299 ++++
 drivers/clk/rockchip/Kconfig                  |    7 +
 drivers/clk/rockchip/Makefile                 |    1 +
 drivers/clk/rockchip/clk-rv1106.c             | 1107 +++++++++++++
 drivers/pinctrl/pinctrl-rockchip.c            |  208 +++
 drivers/pinctrl/pinctrl-rockchip.h            |    1 +
 .../dt-bindings/clock/rockchip,rv1106-cru.h   |  301 ++++
 19 files changed, 3529 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
 create mode 100644 arch/arm/boot/dts/rockchip/rv1103-luckfox-pico-mini-b.dts
 create mode 100644 arch/arm/boot/dts/rockchip/rv1103.dtsi
 create mode 100644 arch/arm/boot/dts/rockchip/rv1106-pinctrl.dtsi
 create mode 100644 arch/arm/boot/dts/rockchip/rv1106.dtsi
 create mode 100644 drivers/clk/rockchip/clk-rv1106.c
 create mode 100644 include/dt-bindings/clock/rockchip,rv1106-cru.h

---
base-commit: 8cdeaa50eae8dad34885515f62559ee83e7e8dda
branch: rv1106a

-- 
2.43.0

[PATCH 01/12] dt-bindings: clock: rockchip: Add RV1106 CRU support

[Simon Glass]

Add the clock binding header and schema for the Rockchip RV1106 clock
and reset unit. The clock IDs match the numbering used by the vendor
kernel so that existing devicetrees keep working. The header also
covers the GRF clock controller, which provides the MMC drive and
sample phase clocks.

The RV1103 is a package variant of the RV1106 and uses the same CRU.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 .../bindings/clock/rockchip,rv1106-cru.yaml   |  59 ++++
 .../dt-bindings/clock/rockchip,rv1106-cru.h   | 301 ++++++++++++++++++
 2 files changed, 360 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
 create mode 100644 include/dt-bindings/clock/rockchip,rv1106-cru.h

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
new file mode 100644
index 000000000000..884a4a8bb0fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rv1106-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RV1106 Clock and Reset Unit
+
+maintainers:
+  - Simon Glass <sjg@chromium.org>
+  - Heiko Stuebner <heiko@sntech.de>
+
+description:
+  The RV1106 clock controller generates the clock and also implements a
+  reset controller for SoC peripherals.
+
+properties:
+  compatible:
+    const: rockchip,rv1106-cru
+
+  reg:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  "#reset-cells":
+    const: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: xin24m
+
+  rockchip,grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the syscon managing the "general register files" (GRF),
+      if missing pll rates are not changeable, due to the missing pll
+      lock status.
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@ff3b0000 {
+      compatible = "rockchip,rv1106-cru";
+      reg = <0xff3b0000 0x20000>;
+      rockchip,grf = <&grf>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+    };
diff --git a/include/dt-bindings/clock/rockchip,rv1106-cru.h b/include/dt-bindings/clock/rockchip,rv1106-cru.h
new file mode 100644
index 000000000000..acbf9c1ee6af
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rv1106-cru.h
@@ -0,0 +1,301 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
+
+/* pll clocks */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_CPLL		3
+#define PLL_GPLL		4
+#define ARMCLK			5
+
+/* clk (clocks) */
+#define PCLK_DDRPHY		11
+#define PCLK_DDR_ROOT		12
+#define PCLK_DDRMON		13
+#define CLK_TIMER_DDRMON	14
+#define PCLK_DDRC		15
+#define PCLK_DFICTRL		16
+#define ACLK_DDR_ROOT		17
+#define ACLK_SYS_SHRM		18
+#define HCLK_NPU_ROOT		19
+#define ACLK_NPU_ROOT		20
+#define PCLK_NPU_ROOT		21
+#define HCLK_RKNN		22
+#define ACLK_RKNN		23
+#define PCLK_ACODEC		24
+#define MCLK_ACODEC_TX		25
+#define CLK_CORE_CRYPTO		27
+#define CLK_PKA_CRYPTO		28
+#define ACLK_CRYPTO		29
+#define HCLK_CRYPTO		30
+#define ACLK_DECOM		31
+#define PCLK_DECOM		32
+#define DCLK_DECOM		33
+#define ACLK_DMAC		34
+#define PCLK_DSM		35
+#define MCLK_DSM		36
+#define CCLK_SRC_EMMC		37
+#define HCLK_EMMC		38
+#define PCLK_GPIO4		39
+#define DBCLK_GPIO4		40
+#define PCLK_I2C0		41
+#define CLK_I2C0		42
+#define PCLK_I2C2		43
+#define CLK_I2C2		44
+#define PCLK_I2C3		45
+#define CLK_I2C3		46
+#define PCLK_I2C4		47
+#define CLK_I2C4		48
+#define HCLK_I2S0		49
+#define PCLK_DFT2APB		50
+#define HCLK_IVE		51
+#define ACLK_IVE		52
+#define PCLK_PWM0_PERI		53
+#define CLK_PWM0_PERI		54
+#define CLK_CAPTURE_PWM0_PERI	55
+#define PCLK_PERI_ROOT		56
+#define ACLK_PERI_ROOT		57
+#define HCLK_PERI_ROOT		58
+#define CLK_TIMER_ROOT		59
+#define ACLK_BUS_ROOT		60
+#define HCLK_SFC		61
+#define SCLK_SFC		62
+#define PCLK_UART0		63
+#define CLK_PVTM_CORE		64
+#define PCLK_UART1		65
+#define CLK_CORE_MCU_RTC	66
+#define PCLK_PWM1_PERI		67
+#define CLK_PWM1_PERI		68
+#define CLK_CAPTURE_PWM1_PERI	69
+#define PCLK_PWM2_PERI		70
+#define CLK_PWM2_PERI		71
+#define CLK_CAPTURE_PWM2_PERI	72
+#define HCLK_BOOTROM		73
+#define HCLK_SAI		74
+#define MCLK_SAI		75
+#define PCLK_SARADC		76
+#define CLK_SARADC		77
+#define PCLK_SPI1		78
+#define CLK_SPI1		79
+#define PCLK_STIMER		80
+#define CLK_STIMER0		81
+#define CLK_STIMER1		82
+#define PCLK_TIMER		83
+#define CLK_TIMER0		84
+#define CLK_TIMER1		85
+#define CLK_TIMER2		86
+#define CLK_TIMER3		87
+#define CLK_TIMER4		88
+#define CLK_TIMER5		89
+#define HCLK_TRNG_NS		90
+#define HCLK_TRNG_S		91
+#define PCLK_UART2		92
+#define HCLK_CPU		93
+#define PCLK_UART3		94
+#define CLK_CORE_MCU		95
+#define PCLK_UART4		96
+#define PCLK_DDR_HWLP		97
+#define PCLK_UART5		98
+#define ACLK_USBOTG		100
+#define CLK_REF_USBOTG		101
+#define CLK_UTMI_USBOTG		102
+#define PCLK_USBPHY		103
+#define CLK_REF_USBPHY		104
+#define PCLK_WDT_NS		105
+#define TCLK_WDT_NS		106
+#define PCLK_WDT_S		107
+#define TCLK_WDT_S		108
+#define CLK_DDR_FAIL_SAFE	109
+#define XIN_OSC0_DIV		110
+#define CLK_DEEPSLOW		111
+#define PCLK_PMU_GPIO0		112
+#define DBCLK_PMU_GPIO0		113
+#define CLK_PMU			114
+#define PCLK_PMU		115
+#define PCLK_PMU_HP_TIMER	116
+#define CLK_PMU_HP_TIMER	117
+#define CLK_PMU_32K_HP_TIMER	118
+#define PCLK_I2C1		119
+#define CLK_I2C1		120
+#define PCLK_PMU_IOC		121
+#define PCLK_PMU_MAILBOX	122
+#define CLK_PMU_MCU		123
+#define CLK_PMU_MCU_RTC		124
+#define CLK_PMU_MCU_JTAG	125
+#define CLK_PVTM_PMU		126
+#define PCLK_PVTM_PMU		127
+#define CLK_REFOUT		128
+#define CLK_100M_PMU		129
+#define PCLK_PMU_ROOT		130
+#define HCLK_PMU_ROOT		131
+#define HCLK_PMU_SRAM		132
+#define PCLK_PMU_WDT		133
+#define TCLK_PMU_WDT		134
+#define CLK_DFICTRL		135
+#define CLK_DDRMON		136
+#define CLK_DDR_PHY		137
+#define ACLK_DDRC		138
+#define CLK_CORE_DDRC_SRC	139
+#define CLK_CORE_DDRC		140
+#define CLK_50M_SRC		141
+#define CLK_100M_SRC		142
+#define CLK_150M_SRC		143
+#define CLK_200M_SRC		144
+#define CLK_250M_SRC		145
+#define CLK_300M_SRC		146
+#define CLK_339M_SRC		147
+#define CLK_400M_SRC		148
+#define CLK_450M_SRC		149
+#define CLK_500M_SRC		150
+#define CLK_I2S0_8CH_TX_SRC	151
+#define CLK_I2S0_8CH_TX_FRAC	152
+#define CLK_I2S0_8CH_TX		153
+#define CLK_I2S0_8CH_RX_SRC	154
+#define CLK_I2S0_8CH_RX_FRAC	155
+#define CLK_I2S0_8CH_RX		156
+#define I2S0_8CH_MCLKOUT	157
+#define MCLK_I2S0_8CH_RX	158
+#define MCLK_I2S0_8CH_TX	159
+#define CLK_REF_MIPI0_SRC	160
+#define CLK_REF_MIPI0_FRAC	161
+#define CLK_REF_MIPI0_OUT	162
+#define CLK_REF_MIPI1_SRC	163
+#define CLK_REF_MIPI1_FRAC	164
+#define MCLK_REF_MIPI0		165
+#define MCLK_REF_MIPI1		166
+#define CLK_REF_MIPI0		167
+#define CLK_REF_MIPI1		168
+#define CLK_UART0_SRC		169
+#define CLK_UART0_FRAC		170
+#define CLK_UART0		171
+#define SCLK_UART0		172
+#define CLK_UART1_SRC		173
+#define CLK_UART1_FRAC		174
+#define CLK_UART1		175
+#define SCLK_UART1		176
+#define CLK_UART2_SRC		177
+#define CLK_UART2_FRAC		178
+#define CLK_UART2		179
+#define SCLK_UART2		180
+#define CLK_UART3_SRC		181
+#define CLK_UART3_FRAC		182
+#define CLK_UART3		183
+#define SCLK_UART3		184
+#define CLK_UART4_SRC		185
+#define CLK_UART4_FRAC		186
+#define CLK_UART4		187
+#define SCLK_UART4		188
+#define CLK_UART5_SRC		189
+#define CLK_UART5_FRAC		190
+#define CLK_UART5		191
+#define SCLK_UART5		192
+#define CLK_VICAP_M0_SRC	193
+#define CLK_VICAP_M0_FRAC	194
+#define CLK_VICAP_M0		195
+#define SCLK_VICAP_M0		196
+#define CLK_VICAP_M1_SRC	197
+#define CLK_VICAP_M1_FRAC	198
+#define CLK_VICAP_M1		199
+#define SCLK_VICAP_M1		200
+#define DCLK_VOP_SRC		201
+#define PCLK_CRU		202
+#define PCLK_TOP_ROOT		203
+#define PCLK_SPI0		204
+#define CLK_SPI0		205
+#define SCLK_IN_SPI0		206
+#define CLK_UART_DETN_FLT	207
+#define HCLK_VEPU		208
+#define ACLK_VEPU		209
+#define CLK_CORE_VEPU		210
+#define CLK_CORE_VEPU_DVBM	211
+#define PCLK_GPIO1		212
+#define DBCLK_GPIO1		213
+#define HCLK_VEPU_PP		214
+#define ACLK_VEPU_PP		215
+#define HCLK_VEPU_ROOT		216
+#define ACLK_VEPU_COM_ROOT	217
+#define ACLK_VEPU_ROOT		218
+#define PCLK_VEPU_ROOT		219
+#define PCLK_VICAP_VEPU		220
+#define PCLK_CSIHOST0		221
+#define CLK_RXBYTECLKHS_0	222
+#define PCLK_CSIHOST1		223
+#define CLK_RXBYTECLKHS_1	224
+#define PCLK_GPIO3		225
+#define DBCLK_GPIO3		226
+#define HCLK_ISP3P2		227
+#define ACLK_ISP3P2		228
+#define CLK_CORE_ISP3P2		229
+#define PCLK_MIPICSIPHY		230
+#define CCLK_SRC_SDMMC		231
+#define HCLK_SDMMC		232
+#define CLK_SDMMC_DETN_FLT	233
+#define HCLK_VI_ROOT		234
+#define ACLK_VI_ROOT		235
+#define PCLK_VI_ROOT		236
+#define PCLK_VI_RTC_ROOT	237
+#define PCLK_VI_RTC_TEST	238
+#define PCLK_VI_RTC_PHY		239
+#define DCLK_VICAP		240
+#define PCLK_VICAP		241
+#define ACLK_VICAP		242
+#define HCLK_VICAP		243
+#define I0CLK_VICAP		244
+#define I1CLK_VICAP		245
+#define RX0PCLK_VICAP		246
+#define RX1PCLK_VICAP		247
+#define ISP0CLK_VICAP		248
+#define PCLK_GPIO2		249
+#define DBCLK_GPIO2		250
+#define ACLK_MAC		251
+#define PCLK_MAC		252
+#define CLK_GMAC0_50M_O		253
+#define CLK_GMAC0_TX_50M_O	254
+#define CLK_GMAC0_REF_50M	255
+#define CLK_GMAC0_TX_50M	256
+#define CLK_GMAC0_RX_50M	257
+#define ACLK_MAC_ROOT		258
+#define CLK_MACPHY		259
+#define CLK_OTPC_ARB		260
+#define PCLK_OTPC_NS		261
+#define CLK_SBPI_OTPC_NS	262
+#define CLK_USER_OTPC_NS	263
+#define PCLK_OTPC_S		264
+#define CLK_SBPI_OTPC_S		265
+#define CLK_USER_OTPC_S		266
+#define PCLK_OTP_MASK		267
+#define CLK_PMC_OTP		268
+#define HCLK_RGA2E		269
+#define ACLK_RGA2E		270
+#define CLK_CORE_RGA2E		271
+#define CCLK_SRC_SDIO		272
+#define HCLK_SDIO		273
+#define PCLK_TSADC		274
+#define CLK_TSADC		275
+#define CLK_TSADC_TSEN		276
+#define ACLK_VO_ROOT		277
+#define HCLK_VO_ROOT		278
+#define PCLK_VO_ROOT		279
+#define ACLK_VOP_ROOT		280
+#define HCLK_VOP		281
+#define DCLK_VOP		282
+#define ACLK_VOP		283
+#define CLK_RTC_32K		284
+#define PCLK_MAILBOX		291
+
+
+/* mmc phase clocks provided by the grf-cru */
+#define SCLK_EMMC_DRV		1
+#define SCLK_EMMC_SAMPLE	2
+#define SCLK_SDMMC_DRV		3
+#define SCLK_SDMMC_SAMPLE	4
+#define SCLK_SDIO_DRV		5
+#define SCLK_SDIO_SAMPLE	6
+
+#endif
-- 
2.43.0

[PATCH 02/12] clk: rockchip: Add clock controller for the RV1106

[Simon Glass]

Add the clock controller driver for the Rockchip RV1106, based on the
driver from the vendor kernel by Elaine Zhang, following the structure
of the RV1103B driver.

The vendor driver is in the Luckfox Pico SDK [1] at commit 824b817f8
(a Linux 5.10.160 kernel tree).

Compared with the vendor driver, the armclk mux parent is expressed
through the parent-name array required by the mainline armclk helper,
the CRU register offsets are defined locally in the driver, and the
pvtpll is initialised but not calibrated, so the CPU rates which use
it run at the ring oscillator's natural frequency. The MMC drive and
sample phase clocks are registered by a separate provider for the GRF
clock controller child node. No resets are exposed yet, as with the
RV1103B.

The RV1103 is a package variant of the RV1106 and uses the same clock
controller.

[1] https://github.com/LuckfoxTECH/luckfox-pico

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 drivers/clk/rockchip/Kconfig      |    7 +
 drivers/clk/rockchip/Makefile     |    1 +
 drivers/clk/rockchip/clk-rv1106.c | 1107 +++++++++++++++++++++++++++++
 3 files changed, 1115 insertions(+)
 create mode 100644 drivers/clk/rockchip/clk-rv1106.c

diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index 85133498f013..4b55f48d72c2 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -23,6 +23,13 @@ config CLK_RV1103B
 	help
 	  Build the driver for RV1103B Clock Driver.
 
+config CLK_RV1106
+	bool "Rockchip RV1106 clock controller support"
+	depends on ARM || COMPILE_TEST
+	default y
+	help
+	  Build the driver for RV1106 Clock Driver.
+
 config CLK_RV110X
 	bool "Rockchip RV110x clock controller support"
 	depends on ARM || COMPILE_TEST
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 7c984ee006c6..554b7eb83dc9 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -19,6 +19,7 @@ clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
 
 obj-$(CONFIG_CLK_PX30)          += clk-px30.o
 obj-$(CONFIG_CLK_RV1103B)	+= clk-rv1103b.o
+obj-$(CONFIG_CLK_RV1106)	+= clk-rv1106.o
 obj-$(CONFIG_CLK_RV110X)        += clk-rv1108.o
 obj-$(CONFIG_CLK_RV1126)        += clk-rv1126.o
 obj-$(CONFIG_CLK_RV1126B)	+= clk-rv1126b.o rst-rv1126b.o
diff --git a/drivers/clk/rockchip/clk-rv1106.c b/drivers/clk/rockchip/clk-rv1106.c
new file mode 100644
index 000000000000..88f043f34c23
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rv1106.c
@@ -0,0 +1,1107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <dt-bindings/clock/rockchip,rv1106-cru.h>
+#include "clk.h"
+
+/*
+ * Register offsets inside the CRU region. The RV1106 CRU is split into
+ * several sub-blocks, one per power domain, all accessed through a
+ * single register window.
+ */
+#define RV1106_TOPCRU_BASE		0x10000
+#define RV1106_PERICRU_BASE		0x12000
+#define RV1106_VICRU_BASE		0x14000
+#define RV1106_NPUCRU_BASE		0x16000
+#define RV1106_CORECRU_BASE		0x18000
+#define RV1106_VEPUCRU_BASE		0x1a000
+#define RV1106_VOCRU_BASE		0x1c000
+#define RV1106_DDRCRU_BASE		0x1e000
+#define RV1106_SUBDDRCRU_BASE		0x1f000
+
+#define RV1106_PMUCLKSEL_CON(x)		((x) * 0x4 + 0x300)
+#define RV1106_PMUCLKGATE_CON(x)	((x) * 0x4 + 0x800)
+#define RV1106_PLL_CON(x)		((x) * 0x4 + RV1106_TOPCRU_BASE)
+#define RV1106_MODE_CON			(0x280 + RV1106_TOPCRU_BASE)
+#define RV1106_CLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_TOPCRU_BASE)
+#define RV1106_CLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1106_TOPCRU_BASE)
+#define RV1106_GLB_SRST_FST		(0xc08 + RV1106_TOPCRU_BASE)
+#define RV1106_PERICLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_PERICRU_BASE)
+#define RV1106_PERICLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_PERICRU_BASE)
+#define RV1106_VICLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
+#define RV1106_VICLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
+#define RV1106_NPUCLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_NPUCRU_BASE)
+#define RV1106_NPUCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_NPUCRU_BASE)
+#define RV1106_CORECLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_CORECRU_BASE)
+#define RV1106_CORECLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_CORECRU_BASE)
+#define RV1106_VEPUCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_VEPUCRU_BASE)
+#define RV1106_VEPUCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_VEPUCRU_BASE)
+#define RV1106_VOCLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_VOCRU_BASE)
+#define RV1106_VOCLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1106_VOCRU_BASE)
+#define RV1106_DDRCLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_DDRCRU_BASE)
+#define RV1106_DDRCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_DDRCRU_BASE)
+#define RV1106_SUBDDRCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_SUBDDRCRU_BASE)
+#define RV1106_SUBDDRCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_SUBDDRCRU_BASE)
+#define RV1106_SUBDDRMODE_CON		(0x280 + RV1106_SUBDDRCRU_BASE)
+
+/* Register offsets inside the GRF region used by the grf-cru */
+#define RV1106_VI_GRF_BASE		0x50000
+#define RV1106_VO_GRF_BASE		0x60000
+
+#define RV1106_EMMC_CON0		0x20
+#define RV1106_EMMC_CON1		0x24
+#define RV1106_SDMMC_CON0		(0x4 + RV1106_VI_GRF_BASE)
+#define RV1106_SDMMC_CON1		(0x8 + RV1106_VI_GRF_BASE)
+#define RV1106_SDIO_CON0		(0x1c + RV1106_VO_GRF_BASE)
+#define RV1106_SDIO_CON1		(0x20 + RV1106_VO_GRF_BASE)
+
+#define CRU_PVTPLL0_CON0_L		0x11000
+#define CRU_PVTPLL0_CON0_H		0x11004
+#define CRU_PVTPLL0_CON1_L		0x11008
+#define CRU_PVTPLL0_CON2_H		0x11014
+
+#define CRU_PVTPLL1_CON0_L		0x11030
+#define CRU_PVTPLL1_CON0_H		0x11034
+#define CRU_PVTPLL1_CON1_L		0x11038
+#define CRU_PVTPLL1_CON2_H		0x11044
+
+#define RV1106_GRF_SOC_STATUS0		0x10
+#define CPU_PVTPLL_CON0_L		0x40000
+#define CPU_PVTPLL_CON0_H		0x40004
+
+#define PVTPLL_RING_SEL_MASK		0x7
+#define PVTPLL_RING_SEL_SHIFT		8
+#define PVTPLL_EN_MASK			0x3
+#define PVTPLL_EN_SHIFT			0
+#define PVTPLL_LENGTH_SEL_MASK		0x7f
+#define PVTPLL_LENGTH_SEL_SHIFT		0
+
+#define CPU_CLK_PATH_BASE		RV1106_CORECLKSEL_CON(0)
+#define CPU_PVTPLL_PATH_CORE		(BIT(12) | BIT(28))
+
+#define RV1106_FRAC_MAX_PRATE		1200000000
+
+enum rv1106_plls {
+	apll, dpll, cpll, gpll,
+};
+
+static struct rockchip_pll_rate_table rv1106_pll_rates[] = {
+	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+	RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
+	RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
+	RK3036_PLL_RATE(993484800, 1, 124, 3, 1, 0, 3113851),
+	RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
+	RK3036_PLL_RATE(983040000, 1, 81, 2, 1, 0, 15435038),
+	RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
+	RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
+	RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+	RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
+	RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
+	RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
+	RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
+	RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+	RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
+	RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
+	RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
+	RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
+	RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
+	RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
+	RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
+	RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
+	RK3036_PLL_RATE(496742400, 1, 124, 6, 1, 0, 3113851),
+	RK3036_PLL_RATE(491520000, 1, 40, 2, 1, 0, 16106127),
+	RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+	RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
+	RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
+	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
+	{ /* sentinel */ },
+};
+
+#define RV1106_DIV_ACLK_CORE_MASK	0x1f
+#define RV1106_DIV_ACLK_CORE_SHIFT	7
+#define RV1106_DIV_PCLK_DBG_MASK	0x1f
+#define RV1106_DIV_PCLK_DBG_SHIFT	0
+#define RV1106_CORE_SEL_MASK		0x3
+#define RV1106_CORE_SEL_SHIFT		5
+#define RV1106_ALT_DIV_MASK		0x1f
+#define RV1106_ALT_DIV_SHIFT		0
+
+#define RV1106_CLKSEL0(_aclk_core)					\
+{									\
+	.reg = RV1106_CORECLKSEL_CON(0),				\
+	.val = HIWORD_UPDATE(_aclk_core, RV1106_DIV_ACLK_CORE_MASK,	\
+			     RV1106_DIV_ACLK_CORE_SHIFT),		\
+}
+
+#define RV1106_CLKSEL1(_pclk_dbg)					\
+{									\
+	.reg = RV1106_CORECLKSEL_CON(1),				\
+	.val = HIWORD_UPDATE(_pclk_dbg, RV1106_DIV_PCLK_DBG_MASK,	\
+			     RV1106_DIV_PCLK_DBG_SHIFT),		\
+}
+
+#define RV1106_CLKSEL2(_is_pvtpll)					\
+{									\
+	.reg = RV1106_CORECLKSEL_CON(0),				\
+	.val = HIWORD_UPDATE(_is_pvtpll, RV1106_CORE_SEL_MASK,		\
+			     RV1106_CORE_SEL_SHIFT),			\
+}
+
+#define RV1106_CLKSEL3(_alt_div)					\
+{									\
+	.reg = RV1106_CORECLKSEL_CON(0),				\
+	.val = HIWORD_UPDATE(_alt_div, RV1106_ALT_DIV_MASK,		\
+			     RV1106_ALT_DIV_SHIFT),			\
+}
+
+#define RV1106_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg, _is_pvtpll)	\
+{									\
+	.prate = _prate,						\
+	.divs = {							\
+		RV1106_CLKSEL0(_aclk_core),				\
+		RV1106_CLKSEL1(_pclk_dbg),				\
+	},								\
+	.pre_muxs = {							\
+		RV1106_CLKSEL3(1),					\
+		RV1106_CLKSEL2(2),					\
+	},								\
+	.post_muxs = {							\
+		RV1106_CLKSEL2(_is_pvtpll),				\
+		RV1106_CLKSEL3(0),					\
+	},								\
+}
+
+static struct rockchip_cpuclk_rate_table rv1106_cpuclk_rates[] __initdata = {
+	RV1106_CPUCLK_RATE(1608000000, 3, 7, 1),
+	RV1106_CPUCLK_RATE(1584000000, 3, 7, 1),
+	RV1106_CPUCLK_RATE(1560000000, 3, 7, 1),
+	RV1106_CPUCLK_RATE(1536000000, 3, 7, 1),
+	RV1106_CPUCLK_RATE(1512000000, 3, 7, 1),
+	RV1106_CPUCLK_RATE(1488000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1464000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1440000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1416000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1392000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1368000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1344000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1320000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1296000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1272000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1248000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1224000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1200000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1104000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1096000000, 2, 5, 1),
+	RV1106_CPUCLK_RATE(1008000000, 1, 5, 1),
+	RV1106_CPUCLK_RATE(912000000, 1, 5, 1),
+	RV1106_CPUCLK_RATE(816000000, 1, 3, 1),
+	RV1106_CPUCLK_RATE(696000000, 1, 3, 0),
+	RV1106_CPUCLK_RATE(600000000, 1, 3, 0),
+	RV1106_CPUCLK_RATE(408000000, 1, 1, 0),
+	RV1106_CPUCLK_RATE(312000000, 1, 1, 0),
+	RV1106_CPUCLK_RATE(216000000,  1, 1, 0),
+	RV1106_CPUCLK_RATE(96000000, 1, 1, 0),
+};
+
+static const struct rockchip_cpuclk_reg_data rv1106_cpuclk_data = {
+	.core_reg[0] = RV1106_CORECLKSEL_CON(0),
+	.div_core_shift[0] = 0,
+	.div_core_mask[0] = 0x1f,
+	.num_cores = 1,
+	.mux_core_alt = 2,
+	.mux_core_main = 0,
+	.mux_core_shift = 5,
+	.mux_core_mask = 0x3,
+};
+
+PNAME(mux_pll_p)			= { "xin24m" };
+PNAME(mux_armclk_p)			= { "apll", "cpu_pvtpll", "gpll" };
+PNAME(mux_24m_32k_p)			= { "xin24m", "clk_rtc_32k" };
+PNAME(mux_gpll_cpll_p)			= { "gpll", "cpll" };
+PNAME(mux_gpll_24m_p)			= { "gpll", "xin24m" };
+PNAME(mux_100m_50m_24m_p)		= { "clk_100m_src", "clk_50m_src", "xin24m" };
+PNAME(mux_150m_100m_50m_24m_p)		= { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
+PNAME(mux_500m_300m_100m_24m_p)		= { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" };
+PNAME(mux_400m_300m_pvtpll0_pvtpll1_p)	= { "clk_400m_src", "clk_300m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
+PNAME(mux_500m_300m_pvtpll0_pvtpll1_p)	= { "clk_500m_src", "clk_300m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
+PNAME(mux_339m_200m_pvtpll0_pvtpll1_p)	= { "clk_339m_src", "clk_200m_src", "clk_pvtpll_0", "clk_pvtpll_1" };
+PNAME(mux_400m_200m_100m_24m_p)		= { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
+PNAME(mux_200m_100m_50m_24m_p)		= { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
+PNAME(mux_300m_200m_100m_24m_p)		= { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
+PNAME(mux_500m_300m_200m_24m_p)		= { "clk_500m_src", "clk_300m_src", "clk_200m_src", "xin24m" };
+PNAME(mux_50m_24m_p)			= { "clk_50m_src", "xin24m" };
+PNAME(mux_400m_24m_p)			= { "clk_400m_src", "xin24m" };
+PNAME(clk_rtc32k_pmu_p)			= { "clk_rtc32k_frac", "xin32k", "clk_pvtm_32k" };
+PNAME(mux_200m_100m_24m_32k_p)		= { "clk_200m_src", "clk_100m_src", "xin24m", "clk_rtc_32k" };
+PNAME(mux_100m_pmu_24m_p)		= { "clk_100m_pmu", "xin24m" };
+PNAME(mux_200m_100m_24m_p)		= { "clk_200m_src", "clk_100m_pmu", "xin24m" };
+PNAME(mux_339m_200m_100m_24m_p)		= { "clk_339m_src", "clk_200m_src", "clk_100m_pmu", "xin24m" };
+PNAME(mux_dpll_300m_p)			= { "dpll", "clk_300m_src" };
+PNAME(clk_i2s0_8ch_tx_p)		= { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
+PNAME(clk_i2s0_8ch_rx_p)		= { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
+PNAME(i2s0_8ch_mclkout_p)		= { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin_osc0_half" };
+PNAME(clk_ref_mipi0_p)			= { "clk_ref_mipi0_src", "clk_ref_mipi0_frac", "xin24m" };
+PNAME(clk_ref_mipi1_p)			= { "clk_ref_mipi1_src", "clk_ref_mipi1_frac", "xin24m" };
+PNAME(clk_uart0_p)			= { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
+PNAME(clk_uart1_p)			= { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
+PNAME(clk_uart2_p)			= { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
+PNAME(clk_uart3_p)			= { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
+PNAME(clk_uart4_p)			= { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
+PNAME(clk_uart5_p)			= { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
+PNAME(clk_vicap_m0_p)			= { "clk_vicap_m0_src", "clk_vicap_m0_frac", "xin24m" };
+PNAME(clk_vicap_m1_p)			= { "clk_vicap_m1_src", "clk_vicap_m1_frac", "xin24m" };
+
+static struct rockchip_pll_clock rv1106_pll_clks[] __initdata = {
+	[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
+		     CLK_IGNORE_UNUSED, RV1106_PLL_CON(0),
+		     RV1106_MODE_CON, 0, 10, 0, rv1106_pll_rates),
+	[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
+		     0, RV1106_PLL_CON(8),
+		     RV1106_MODE_CON, 2, 10, 0, rv1106_pll_rates),
+	[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
+		     CLK_IGNORE_UNUSED, RV1106_PLL_CON(16),
+		     RV1106_SUBDDRMODE_CON, 0, 10, 0, NULL),
+	[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
+		     0, RV1106_PLL_CON(24),
+		     RV1106_MODE_CON, 4, 10, 0, rv1106_pll_rates),
+};
+
+#define MFLAGS CLK_MUX_HIWORD_MASK
+#define DFLAGS CLK_DIVIDER_HIWORD_MASK
+#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+
+static struct rockchip_clk_branch rv1106_rtc32k_pmu_fracmux __initdata =
+	MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+			RV1106_PMUCLKSEL_CON(0), 6, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_i2s0_8ch_tx_fracmux __initdata =
+	MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(19), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_i2s0_8ch_rx_fracmux __initdata =
+	MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(21), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_ref_mipi0_fracmux __initdata =
+	MUX(CLK_REF_MIPI0, "clk_ref_mipi0", clk_ref_mipi0_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(27), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_ref_mipi1_fracmux __initdata =
+	MUX(CLK_REF_MIPI1, "clk_ref_mipi1", clk_ref_mipi1_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(29), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_uart0_fracmux __initdata =
+	MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(7), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_uart1_fracmux __initdata =
+	MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(9), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_uart2_fracmux __initdata =
+	MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(11), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_uart3_fracmux __initdata =
+	MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(13), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_uart4_fracmux __initdata =
+	MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(15), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_uart5_fracmux __initdata =
+	MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(17), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_vicap_m0_fracmux __initdata =
+	MUX(CLK_VICAP_M0, "clk_vicap_m0", clk_vicap_m0_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(31), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_vicap_m1_fracmux __initdata =
+	MUX(CLK_VICAP_M1, "clk_vicap_m1", clk_vicap_m1_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(33), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1106_clk_branches[] __initdata = {
+
+	FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
+
+	/* PD_CORE */
+	GATE(CLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
+			RV1106_CORECLKGATE_CON(0), 14, GFLAGS),
+	GATE(CLK_CORE_MCU_RTC, "clk_core_mcu_rtc", "xin24m", 0,
+			RV1106_CORECLKGATE_CON(1), 6, GFLAGS),
+	COMPOSITE(HCLK_CPU, "hclk_cpu", mux_gpll_24m_p, CLK_IS_CRITICAL,
+			RV1106_CORECLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_CORECLKGATE_CON(0), 12, GFLAGS),
+	COMPOSITE(CLK_CORE_MCU, "clk_core_mcu", mux_gpll_24m_p, 0,
+			RV1106_CORECLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
+			RV1106_CORECLKGATE_CON(1), 1, GFLAGS),
+	COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IS_CRITICAL,
+			RV1106_CORECLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
+			RV1106_CORECLKGATE_CON(0), 6, GFLAGS),
+	GATE(0, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL,
+			RV1106_CORECLKGATE_CON(0), 10, GFLAGS),
+	GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_cpu_root", 0,
+			RV1106_CORECLKGATE_CON(1), 8, GFLAGS),
+
+	/* PD _TOP */
+	COMPOSITE(CLK_50M_SRC, "clk_50m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE(CLK_100M_SRC, "clk_100m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 2, GFLAGS),
+	COMPOSITE(CLK_150M_SRC, "clk_150m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 3, GFLAGS),
+	COMPOSITE(CLK_200M_SRC, "clk_200m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 4, GFLAGS),
+	COMPOSITE(CLK_250M_SRC, "clk_250m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 5, GFLAGS),
+	COMPOSITE(CLK_300M_SRC, "clk_300m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 6, GFLAGS),
+	COMPOSITE_HALFDIV(CLK_339M_SRC, "clk_339m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 7, GFLAGS),
+	COMPOSITE(CLK_400M_SRC, "clk_400m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 8, GFLAGS),
+	COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 9, GFLAGS),
+	COMPOSITE(CLK_500M_SRC, "clk_500m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 10, GFLAGS),
+
+	COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_CLKSEL_CON(24), 5, 2, MFLAGS,
+			RV1106_CLKGATE_CON(2), 9, GFLAGS),
+
+	COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(17), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(1), 13, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(18), 0,
+			RV1106_CLKGATE_CON(1), 14, GFLAGS,
+			&rv1106_i2s0_8ch_tx_fracmux),
+	GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
+			RV1106_CLKGATE_CON(1), 15, GFLAGS),
+	COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(19), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(2), 0, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(20), 0,
+			RV1106_CLKGATE_CON(2), 1, GFLAGS,
+			&rv1106_i2s0_8ch_rx_fracmux),
+	GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
+			RV1106_CLKGATE_CON(2), 2, GFLAGS),
+	MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(21), 2, 2, MFLAGS),
+	COMPOSITE(CLK_REF_MIPI0_SRC, "clk_ref_mipi0_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(25), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(3), 4, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_REF_MIPI0_FRAC, "clk_ref_mipi0_frac", "clk_ref_mipi0_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(26), 0,
+			RV1106_CLKGATE_CON(3), 5, GFLAGS,
+			&rv1106_clk_ref_mipi0_fracmux),
+	GATE(MCLK_REF_MIPI0, "mclk_ref_mipi0", "clk_ref_mipi0", 0,
+			 RV1106_CLKGATE_CON(3), 6, GFLAGS),
+	COMPOSITE(CLK_REF_MIPI1_SRC, "clk_ref_mipi1_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(27), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(3), 7, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_REF_MIPI1_FRAC, "clk_ref_mipi1_frac", "clk_ref_mipi1_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(28), 0,
+			RV1106_CLKGATE_CON(3), 8, GFLAGS,
+			&rv1106_clk_ref_mipi1_fracmux),
+	GATE(MCLK_REF_MIPI1, "mclk_ref_mipi1", "clk_ref_mipi1", 0,
+			 RV1106_CLKGATE_CON(3), 9, GFLAGS),
+	COMPOSITE(CLK_UART0_SRC, "clk_uart0_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 11, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(6), 0,
+			RV1106_CLKGATE_CON(0), 12, GFLAGS,
+			&rv1106_clk_uart0_fracmux),
+	GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
+			RV1106_CLKGATE_CON(0), 13, GFLAGS),
+	COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(7), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(0), 14, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(8), 0,
+			RV1106_CLKGATE_CON(0), 15, GFLAGS,
+			&rv1106_clk_uart1_fracmux),
+	GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
+			 RV1106_CLKGATE_CON(1), 0, GFLAGS),
+	COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(9), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(1), 1, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(10), 0,
+			RV1106_CLKGATE_CON(1), 2, GFLAGS,
+			&rv1106_clk_uart2_fracmux),
+	GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
+			 RV1106_CLKGATE_CON(1), 3, GFLAGS),
+	COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(11), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(1), 4, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(12), 0,
+			RV1106_CLKGATE_CON(1), 5, GFLAGS,
+			&rv1106_clk_uart3_fracmux),
+	GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
+			 RV1106_CLKGATE_CON(1), 6, GFLAGS),
+	COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(13), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(1), 7, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(14), 0,
+			RV1106_CLKGATE_CON(1), 8, GFLAGS,
+			&rv1106_clk_uart4_fracmux),
+	GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
+			 RV1106_CLKGATE_CON(1), 9, GFLAGS),
+	COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(15), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(1), 10, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(16), 0,
+			RV1106_CLKGATE_CON(1), 11, GFLAGS,
+			&rv1106_clk_uart5_fracmux),
+	GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
+			 RV1106_CLKGATE_CON(1), 12, GFLAGS),
+	COMPOSITE(CLK_VICAP_M0_SRC, "clk_vicap_m0_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(29), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(3), 10, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_VICAP_M0_FRAC, "clk_vicap_m0_frac", "clk_vicap_m0_src", CLK_SET_RATE_PARENT,
+			RV1106_CLKSEL_CON(30), 0,
+			RV1106_CLKGATE_CON(3), 11, GFLAGS,
+			&rv1106_clk_vicap_m0_fracmux),
+	GATE(SCLK_VICAP_M0, "sclk_vicap_m0", "clk_vicap_m0", 0,
+			 RV1106_CLKGATE_CON(3), 12, GFLAGS),
+	COMPOSITE(CLK_VICAP_M1_SRC, "clk_vicap_m1_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(31), 7, 1, MFLAGS, 2, 5, DFLAGS,
+			RV1106_CLKGATE_CON(3), 13, GFLAGS),
+	COMPOSITE_FRACMUX(CLK_VICAP_M1_FRAC, "clk_vicap_m1_frac", "clk_vicap_m1_src", 0,
+			RV1106_CLKSEL_CON(32), 0,
+			RV1106_CLKGATE_CON(3), 14, GFLAGS,
+			&rv1106_clk_vicap_m1_fracmux),
+	GATE(SCLK_VICAP_M1, "sclk_vicap_m1", "clk_vicap_m1", 0,
+			 RV1106_CLKGATE_CON(3), 15, GFLAGS),
+	COMPOSITE(DCLK_VOP_SRC, "dclk_vop_src", mux_gpll_cpll_p, 0,
+			RV1106_CLKSEL_CON(23), 8, 1, MFLAGS, 3, 5, DFLAGS,
+			RV1106_CLKGATE_CON(2), 6, GFLAGS),
+
+	/* PD_DDR */
+	COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_DDRCLKSEL_CON(0), 0, 2, MFLAGS,
+			RV1106_DDRCLKGATE_CON(0), 0, GFLAGS),
+	COMPOSITE_NODIV(ACLK_DDR_ROOT, "aclk_ddr_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_DDRCLKSEL_CON(0), 8, 2, MFLAGS,
+			RV1106_DDRCLKGATE_CON(0), 12, GFLAGS),
+	GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IGNORE_UNUSED,
+			RV1106_DDRCLKGATE_CON(1), 3, GFLAGS),
+	GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED,
+			RV1106_DDRCLKGATE_CON(1), 2, GFLAGS),
+	GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", 0,
+			RV1106_DDRCLKGATE_CON(0), 7, GFLAGS),
+	GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
+			RV1106_DDRCLKGATE_CON(0), 8, GFLAGS),
+	GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IGNORE_UNUSED,
+			RV1106_DDRCLKGATE_CON(0), 5, GFLAGS),
+	GATE(PCLK_DFICTRL, "pclk_dfictrl", "pclk_ddr_root", CLK_IS_CRITICAL,
+			RV1106_DDRCLKGATE_CON(0), 11, GFLAGS),
+	GATE(ACLK_SYS_SHRM, "aclk_sys_shrm", "aclk_ddr_root", CLK_IS_CRITICAL,
+			RV1106_DDRCLKGATE_CON(0), 13, GFLAGS),
+
+	/* PD_NPU */
+	COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_NPUCLKSEL_CON(0), 0, 2, MFLAGS,
+			RV1106_NPUCLKGATE_CON(0), 0, GFLAGS),
+	COMPOSITE_NODIV(ACLK_NPU_ROOT, "aclk_npu_root", mux_500m_300m_pvtpll0_pvtpll1_p, CLK_IS_CRITICAL,
+			RV1106_NPUCLKSEL_CON(0), 2, 2, MFLAGS,
+			RV1106_NPUCLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_NPUCLKSEL_CON(0), 4, 2, MFLAGS,
+			RV1106_NPUCLKGATE_CON(0), 2, GFLAGS),
+	GATE(HCLK_RKNN, "hclk_rknn", "hclk_npu_root", 0,
+			RV1106_NPUCLKGATE_CON(0), 9, GFLAGS),
+	GATE(ACLK_RKNN, "aclk_rknn", "aclk_npu_root", 0,
+			RV1106_NPUCLKGATE_CON(0), 10, GFLAGS),
+
+	/* PD_PERI */
+	COMPOSITE_NODIV(PCLK_PERI_ROOT, "pclk_peri_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_PERICLKSEL_CON(1), 0, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(0), 0, GFLAGS),
+	COMPOSITE_NODIV(ACLK_PERI_ROOT, "aclk_peri_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_PERICLKSEL_CON(1), 2, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE_NODIV(HCLK_PERI_ROOT, "hclk_peri_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_PERICLKSEL_CON(1), 4, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(0), 2, GFLAGS),
+	COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_PERICLKSEL_CON(9), 0, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(6), 8, GFLAGS),
+	GATE(PCLK_ACODEC, "pclk_acodec", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(6), 3, GFLAGS),
+	COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_i2s0_8ch_tx", 0,
+			RV1106_PERICLKSEL_CON(8), 0, 8, DFLAGS,
+			RV1106_PERICLKGATE_CON(6), 4, GFLAGS),
+	COMPOSITE_NODIV(CLK_CORE_CRYPTO, "clk_core_crypto", mux_300m_200m_100m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(6), 5, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(3), 11, GFLAGS),
+	COMPOSITE_NODIV(CLK_PKA_CRYPTO, "clk_pka_crypto", mux_300m_200m_100m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(6), 7, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(3), 12, GFLAGS),
+	GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus_root", 0,
+			RV1106_PERICLKGATE_CON(3), 13, GFLAGS),
+	GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(3), 14, GFLAGS),
+	GATE(ACLK_DECOM, "aclk_decom", "aclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(5), 9, GFLAGS),
+	GATE(PCLK_DECOM, "pclk_decom", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(5), 10, GFLAGS),
+	COMPOSITE_NODIV(DCLK_DECOM, "dclk_decom", mux_400m_200m_100m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(7), 14, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(5), 11, GFLAGS),
+	GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0,
+			RV1106_PERICLKGATE_CON(5), 8, GFLAGS),
+	GATE(PCLK_DSM, "pclk_dsm", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(6), 2, GFLAGS),
+	GATE(MCLK_DSM, "mclk_dsm", "mclk_i2s0_8ch_tx", 0,
+			RV1106_PERICLKGATE_CON(6), 1, GFLAGS),
+	COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_400m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(7), 6, 1, MFLAGS, 0, 6, DFLAGS,
+			RV1106_PERICLKGATE_CON(4), 12, GFLAGS),
+	GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(4), 13, GFLAGS),
+	GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(2), 0, GFLAGS),
+	GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(2), 1, GFLAGS),
+	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(1), 6, GFLAGS),
+	COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(1), 8, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(1), 7, GFLAGS),
+	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(1), 10, GFLAGS),
+	COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(1), 12, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(1), 11, GFLAGS),
+	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(1), 12, GFLAGS),
+	COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(1), 14, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(1), 13, GFLAGS),
+	GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(1), 14, GFLAGS),
+	COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(2), 0, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(1), 15, GFLAGS),
+	GATE(HCLK_I2S0, "hclk_i2s0", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(6), 0, GFLAGS),
+	GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_peri_root", CLK_IGNORE_UNUSED,
+			RV1106_PERICLKGATE_CON(6), 7, GFLAGS),
+	GATE(HCLK_IVE, "hclk_ive", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(6), 9, GFLAGS),
+	GATE(ACLK_IVE, "aclk_ive", "aclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(6), 10, GFLAGS),
+	GATE(PCLK_PWM0_PERI, "pclk_pwm0_peri", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(7), 3, GFLAGS),
+	COMPOSITE_NODIV(CLK_PWM0_PERI, "clk_pwm0_peri", mux_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(11), 0, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(7), 4, GFLAGS),
+	GATE(CLK_CAPTURE_PWM0_PERI, "clk_capture_pwm0_peri", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(7), 5, GFLAGS),
+	GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(0), 3, GFLAGS),
+	GATE(HCLK_SFC, "hclk_sfc", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(4), 14, GFLAGS),
+	COMPOSITE(SCLK_SFC, "sclk_sfc", mux_500m_300m_200m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(7), 12, 2, MFLAGS, 7, 5, DFLAGS,
+			RV1106_PERICLKGATE_CON(5), 0, GFLAGS),
+	GATE(PCLK_UART0, "pclk_uart0", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(6), 11, GFLAGS),
+	GATE(PCLK_UART1, "pclk_uart1", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(6), 15, GFLAGS),
+	GATE(PCLK_PWM1_PERI, "pclk_pwm1_peri", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(3), 15, GFLAGS),
+	COMPOSITE_NODIV(CLK_PWM1_PERI, "clk_pwm1_peri", mux_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(6), 9, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(4), 0, GFLAGS),
+	GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(4), 1, GFLAGS),
+	GATE(PCLK_PWM2_PERI, "pclk_pwm2_peri", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(4), 2, GFLAGS),
+	COMPOSITE_NODIV(CLK_PWM2_PERI, "clk_pwm2_peri", mux_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(6), 11, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(4), 3, GFLAGS),
+	GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(4), 4, GFLAGS),
+	GATE(HCLK_BOOTROM, "hclk_bootrom", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(0), 7, GFLAGS),
+	GATE(HCLK_SAI, "hclk_sai", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(5), 13, GFLAGS),
+	GATE(MCLK_SAI, "mclk_sai", "mclk_i2s0_8ch_tx", 0,
+			RV1106_PERICLKGATE_CON(5), 14, GFLAGS),
+	GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(3), 3, GFLAGS),
+	COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
+			RV1106_PERICLKSEL_CON(6), 0, 3, DFLAGS,
+			RV1106_PERICLKGATE_CON(3), 4, GFLAGS),
+	GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(3), 6, GFLAGS),
+	COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
+			RV1106_PERICLKSEL_CON(6), 3, 2, MFLAGS,
+			RV1106_PERICLKGATE_CON(3), 7, GFLAGS),
+	GATE(PCLK_STIMER, "pclk_stimer", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(0), 15, GFLAGS),
+	GATE(CLK_STIMER0, "clk_stimer0", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(1), 0, GFLAGS),
+	GATE(CLK_STIMER1, "clk_stimer1", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(1), 1, GFLAGS),
+	GATE(PCLK_TIMER, "pclk_timer", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(0), 8, GFLAGS),
+	GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(0), 9, GFLAGS),
+	GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(0), 10, GFLAGS),
+	GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(0), 11, GFLAGS),
+	GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(0), 12, GFLAGS),
+	GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(0), 13, GFLAGS),
+	GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
+			RV1106_PERICLKGATE_CON(0), 14, GFLAGS),
+	GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(3), 9, GFLAGS),
+	GATE(HCLK_TRNG_S, "hclk_trng_s", "hclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(3), 10, GFLAGS),
+	GATE(PCLK_UART2, "pclk_uart2", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(2), 3, GFLAGS),
+	GATE(PCLK_UART3, "pclk_uart3", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(2), 7, GFLAGS),
+	GATE(PCLK_UART4, "pclk_uart4", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(2), 11, GFLAGS),
+	GATE(PCLK_UART5, "pclk_uart5", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(2), 15, GFLAGS),
+	GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_bus_root", 0,
+			RV1106_PERICLKGATE_CON(4), 7, GFLAGS),
+	GATE(CLK_REF_USBOTG, "clk_ref_usbotg", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(4), 8, GFLAGS),
+	GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(5), 1, GFLAGS),
+	GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(5), 2, GFLAGS),
+	GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(1), 2, GFLAGS),
+	GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(1), 3, GFLAGS),
+	GATE(PCLK_WDT_S, "pclk_wdt_s", "pclk_peri_root", 0,
+			RV1106_PERICLKGATE_CON(1), 4, GFLAGS),
+	GATE(TCLK_WDT_S, "tclk_wdt_s", "xin24m", 0,
+			RV1106_PERICLKGATE_CON(1), 5, GFLAGS),
+
+	/* PD_PMU */
+	COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
+			RV1106_PMUCLKSEL_CON(6), 0,
+			RV1106_PMUCLKGATE_CON(1), 14, GFLAGS,
+			&rv1106_rtc32k_pmu_fracmux),
+	DIV(CLK_100M_PMU, "clk_100m_pmu", "clk_200m_src", 0,
+			RV1106_PMUCLKSEL_CON(0), 0, 3, DFLAGS),
+	COMPOSITE_NODIV(PCLK_PMU_ROOT, "pclk_pmu_root", mux_100m_pmu_24m_p, CLK_IS_CRITICAL,
+			RV1106_PMUCLKSEL_CON(0), 3, 1, MFLAGS,
+			RV1106_PMUCLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE_NODIV(HCLK_PMU_ROOT, "hclk_pmu_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_PMUCLKSEL_CON(0), 4, 2, MFLAGS,
+			RV1106_PMUCLKGATE_CON(0), 2, GFLAGS),
+	GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IS_CRITICAL,
+			RV1106_PMUCLKGATE_CON(1), 0, GFLAGS),
+	GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL,
+			RV1106_PMUCLKGATE_CON(1), 1, GFLAGS),
+	GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu", 0,
+			RV1106_PMUCLKGATE_CON(1), 15, GFLAGS),
+	GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "pclk_pmu_root", 0,
+			RV1106_PMUCLKGATE_CON(1), 2, GFLAGS),
+	COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", mux_24m_32k_p, 0,
+			RV1106_PMUCLKSEL_CON(0), 15, 1, MFLAGS,
+			RV1106_PMUCLKGATE_CON(1), 3, GFLAGS),
+	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pmu_root", 0,
+			RV1106_PMUCLKGATE_CON(0), 3, GFLAGS),
+	COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_24m_32k_p, 0,
+			RV1106_PMUCLKSEL_CON(0), 6, 2, MFLAGS,
+			RV1106_PMUCLKGATE_CON(0), 4, GFLAGS),
+	GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0,
+			RV1106_PMUCLKGATE_CON(2), 10, GFLAGS),
+	GATE(CLK_PMU_MCU, "clk_pmu_mcu", "hclk_pmu_root", 0,
+			RV1106_PMUCLKGATE_CON(0), 9, GFLAGS),
+	GATE(CLK_PMU_MCU_RTC, "clk_pmu_mcu_rtc", "xin24m", 0,
+			RV1106_PMUCLKGATE_CON(0), 13, GFLAGS),
+	COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
+			RV1106_PMUCLKSEL_CON(1), 0, 5, DFLAGS,
+			RV1106_PMUCLKGATE_CON(1), 4, GFLAGS),
+	GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0,
+			RV1106_PMUCLKGATE_CON(1), 5, GFLAGS),
+	GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
+			RV1106_PMUCLKGATE_CON(2), 13, GFLAGS),
+	GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IGNORE_UNUSED,
+			RV1106_PMUCLKGATE_CON(0), 8, GFLAGS),
+	GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0,
+			RV1106_PMUCLKGATE_CON(2), 8, GFLAGS),
+	COMPOSITE_NODIV(TCLK_PMU_WDT, "tclk_pmu_wdt", mux_24m_32k_p, 0,
+			RV1106_PMUCLKSEL_CON(7), 2, 1, MFLAGS,
+			RV1106_PMUCLKGATE_CON(2), 9, GFLAGS),
+
+	/* PD_SUBDDR */
+	COMPOSITE(CLK_CORE_DDRC_SRC, "clk_core_ddrc_src", mux_dpll_300m_p, CLK_IGNORE_UNUSED,
+			RV1106_SUBDDRCLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
+			RV1106_SUBDDRCLKGATE_CON(0), 2, GFLAGS),
+	GATE(CLK_DFICTRL, "clk_dfictrl", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
+			RV1106_SUBDDRCLKGATE_CON(0), 5, GFLAGS),
+	GATE(CLK_DDRMON, "clk_ddrmon", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
+			RV1106_SUBDDRCLKGATE_CON(0), 4, GFLAGS),
+	GATE(CLK_DDR_PHY, "clk_ddr_phy", "clk_core_ddrc_src", CLK_IGNORE_UNUSED,
+			RV1106_SUBDDRCLKGATE_CON(0), 6, GFLAGS),
+	GATE(ACLK_DDRC, "aclk_ddrc", "clk_core_ddrc_src", CLK_IS_CRITICAL,
+			RV1106_SUBDDRCLKGATE_CON(0), 1, GFLAGS),
+	GATE(CLK_CORE_DDRC, "clk_core_ddrc", "clk_core_ddrc_src", CLK_IS_CRITICAL,
+			RV1106_SUBDDRCLKGATE_CON(0), 3, GFLAGS),
+
+	/* PD_VEPU */
+	COMPOSITE_NODIV(HCLK_VEPU_ROOT, "hclk_vepu_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VEPUCLKSEL_CON(0), 0, 2, MFLAGS,
+			RV1106_VEPUCLKGATE_CON(0), 0, GFLAGS),
+	COMPOSITE_NODIV(ACLK_VEPU_COM_ROOT, "aclk_vepu_com_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VEPUCLKSEL_CON(0), 2, 2, MFLAGS,
+			RV1106_VEPUCLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE_NODIV(ACLK_VEPU_ROOT, "aclk_vepu_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VEPUCLKSEL_CON(0), 4, 2, MFLAGS,
+			RV1106_VEPUCLKGATE_CON(0), 2, GFLAGS),
+	COMPOSITE_NODIV(PCLK_VEPU_ROOT, "pclk_vepu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VEPUCLKSEL_CON(0), 6, 2, MFLAGS,
+			RV1106_VEPUCLKGATE_CON(0), 3, GFLAGS),
+	GATE(PCLK_SPI0, "pclk_spi0", "pclk_vepu_root", 0,
+			RV1106_VEPUCLKGATE_CON(1), 2, GFLAGS),
+	COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
+			RV1106_VEPUCLKSEL_CON(0), 12, 2, MFLAGS,
+			RV1106_VEPUCLKGATE_CON(1), 3, GFLAGS),
+	GATE(CLK_UART_DETN_FLT, "clk_uart_detn_flt", "xin24m", 0,
+			RV1106_VEPUCLKGATE_CON(1), 8, GFLAGS),
+	GATE(HCLK_VEPU, "hclk_vepu", "hclk_vepu_root", 0,
+			RV1106_VEPUCLKGATE_CON(0), 8, GFLAGS),
+	GATE(ACLK_VEPU, "aclk_vepu", "aclk_vepu_root", 0,
+			RV1106_VEPUCLKGATE_CON(0), 9, GFLAGS),
+	COMPOSITE_NODIV(CLK_CORE_VEPU, "clk_core_vepu", mux_400m_300m_pvtpll0_pvtpll1_p, 0,
+			RV1106_VEPUCLKSEL_CON(0), 8, 2, MFLAGS,
+			RV1106_VEPUCLKGATE_CON(0), 10, GFLAGS),
+	COMPOSITE_NODIV(CLK_CORE_VEPU_DVBM, "clk_core_vepu_dvbm", mux_200m_100m_50m_24m_p, 0,
+			RV1106_VEPUCLKSEL_CON(0), 10, 2, MFLAGS,
+			RV1106_VEPUCLKGATE_CON(0), 13, GFLAGS),
+	GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vepu_root", 0,
+			RV1106_VEPUCLKGATE_CON(0), 15, GFLAGS),
+	GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
+			RV1106_VEPUCLKGATE_CON(1), 0, GFLAGS),
+	GATE(HCLK_VEPU_PP, "hclk_vepu_pp", "hclk_vepu_root", 0,
+			RV1106_VEPUCLKGATE_CON(0), 11, GFLAGS),
+	GATE(ACLK_VEPU_PP, "aclk_vepu_pp", "aclk_vepu_root", 0,
+			RV1106_VEPUCLKGATE_CON(0), 12, GFLAGS),
+
+	/* PD_VI */
+	COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VICLKSEL_CON(0), 0, 2, MFLAGS,
+			RV1106_VICLKGATE_CON(0), 0, GFLAGS),
+	COMPOSITE_NODIV(ACLK_VI_ROOT, "aclk_vi_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VICLKSEL_CON(0), 2, 2, MFLAGS,
+			RV1106_VICLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VICLKSEL_CON(0), 4, 2, MFLAGS,
+			RV1106_VICLKGATE_CON(0), 2, GFLAGS),
+	COMPOSITE_NODIV(PCLK_VI_RTC_ROOT, "pclk_vi_rtc_root", mux_50m_24m_p, 0,
+			RV1106_VICLKSEL_CON(0), 6, 1, MFLAGS,
+			RV1106_VICLKGATE_CON(0), 3, GFLAGS),
+
+	GATE(PCLK_CSIHOST0, "pclk_csihost0", "pclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(1), 3, GFLAGS),
+	GATE(PCLK_CSIHOST1, "pclk_csihost1", "pclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(1), 5, GFLAGS),
+	GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(1), 15, GFLAGS),
+	GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
+			RV1106_VICLKGATE_CON(2), 0, GFLAGS),
+	GATE(HCLK_ISP3P2, "hclk_isp3p2", "hclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(0), 7, GFLAGS),
+	GATE(ACLK_ISP3P2, "aclk_isp3p2", "aclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(0), 8, GFLAGS),
+	COMPOSITE_NODIV(CLK_CORE_ISP3P2, "clk_core_isp3p2", mux_339m_200m_pvtpll0_pvtpll1_p, 0,
+			RV1106_VICLKSEL_CON(0), 7, 2, MFLAGS,
+			RV1106_VICLKGATE_CON(0), 9, GFLAGS),
+	GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(1), 14, GFLAGS),
+	COMPOSITE(CCLK_SRC_SDMMC, "cclk_src_sdmmc", mux_400m_24m_p, 0,
+			RV1106_VICLKSEL_CON(1), 14, 1, MFLAGS, 8, 6, DFLAGS,
+			RV1106_VICLKGATE_CON(1), 11, GFLAGS),
+	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(1), 12, GFLAGS),
+	GATE(CLK_SDMMC_DETN_FLT, "clk_sdmmc_detn_flt", "xin24m", 0,
+			RV1106_VICLKGATE_CON(1), 13, GFLAGS),
+	GATE(PCLK_VI_RTC_TEST, "pclk_vi_rtc_test", "pclk_vi_rtc_root", 0,
+			RV1106_VICLKGATE_CON(2), 5, GFLAGS),
+	GATE(PCLK_VI_RTC_PHY, "pclk_vi_rtc_phy", "pclk_vi_rtc_root", 0,
+			RV1106_VICLKGATE_CON(2), 6, GFLAGS),
+	COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", mux_339m_200m_100m_24m_p, 0,
+			RV1106_VICLKSEL_CON(0), 9, 2, MFLAGS,
+			RV1106_VICLKGATE_CON(0), 10, GFLAGS),
+	GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(0), 12, GFLAGS),
+	GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
+			RV1106_VICLKGATE_CON(0), 13, GFLAGS),
+
+	/* PD_VO */
+	COMPOSITE_NODIV(ACLK_MAC_ROOT, "aclk_mac_root", mux_300m_200m_100m_24m_p, 0,
+			RV1106_VOCLKSEL_CON(1), 12, 2, MFLAGS,
+			RV1106_VOCLKGATE_CON(1), 4, GFLAGS),
+	COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VOCLKSEL_CON(0), 0, 2, MFLAGS,
+			RV1106_VOCLKGATE_CON(0), 0, GFLAGS),
+	COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VOCLKSEL_CON(0), 2, 2, MFLAGS,
+			RV1106_VOCLKGATE_CON(0), 1, GFLAGS),
+	COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
+			RV1106_VOCLKSEL_CON(0), 4, 2, MFLAGS,
+			RV1106_VOCLKGATE_CON(0), 2, GFLAGS),
+	COMPOSITE_NODIV(ACLK_VOP_ROOT, "aclk_vop_root", mux_300m_200m_100m_24m_p, 0,
+			RV1106_VOCLKSEL_CON(1), 10, 2, MFLAGS,
+			RV1106_VOCLKGATE_CON(0), 11, GFLAGS),
+
+	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(3), 0, GFLAGS),
+	GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
+			RV1106_VOCLKGATE_CON(3), 1, GFLAGS),
+	GATE(ACLK_MAC, "aclk_mac", "aclk_mac_root", 0,
+			RV1106_VOCLKGATE_CON(1), 8, GFLAGS),
+	GATE(PCLK_MAC, "pclk_mac", "pclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(1), 9, GFLAGS),
+	FACTOR(CLK_GMAC0_50M_O, "clk_gmac0_50m_o", "clk_50m_src", 0, 1, 1),
+	FACTOR(CLK_GMAC0_REF_50M, "clk_gmac0_ref_50m", "clk_gmac0_50m_o", 0, 1, 1),
+	DIV(CLK_GMAC0_TX_50M_O, "clk_gmac0_tx_50m_o", "clk_gmac0_50m_o", 0,
+			RV1106_VOCLKSEL_CON(2), 1, 6, DFLAGS),
+	GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
+			RV1106_VOCLKGATE_CON(2), 13, GFLAGS),
+	GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
+			RV1106_VOCLKGATE_CON(2), 11, GFLAGS),
+	GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(2), 3, GFLAGS),
+	GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
+			RV1106_VOCLKGATE_CON(2), 5, GFLAGS),
+	COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0,
+			RV1106_VOCLKSEL_CON(3), 10, 3, DFLAGS,
+			RV1106_VOCLKGATE_CON(2), 6, GFLAGS),
+	GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(2), 7, GFLAGS),
+	GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", 0,
+			RV1106_VOCLKGATE_CON(2), 9, GFLAGS),
+	COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", 0,
+			RV1106_VOCLKSEL_CON(3), 13, 3, DFLAGS,
+			RV1106_VOCLKGATE_CON(2), 10, GFLAGS),
+	GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(2), 14, GFLAGS),
+	GATE(CLK_PMC_OTP, "clk_pmc_otp", "clk_sbpi_otpc_s", 0,
+			RV1106_VOCLKGATE_CON(2), 15, GFLAGS),
+	GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(0), 7, GFLAGS),
+	GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(0), 8, GFLAGS),
+	COMPOSITE_NODIV(CLK_CORE_RGA2E, "clk_core_rga2e", mux_400m_200m_100m_24m_p, 0,
+			RV1106_VOCLKSEL_CON(1), 8, 2, MFLAGS,
+			RV1106_VOCLKGATE_CON(0), 9, GFLAGS),
+	COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", mux_400m_24m_p, 0,
+			RV1106_VOCLKSEL_CON(2), 13, 1, MFLAGS, 7, 6, DFLAGS,
+			RV1106_VOCLKGATE_CON(1), 14, GFLAGS),
+	GATE(HCLK_SDIO, "hclk_sdio", "hclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(1), 15, GFLAGS),
+	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(2), 0, GFLAGS),
+	COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
+			RV1106_VOCLKSEL_CON(3), 0, 5, DFLAGS,
+			RV1106_VOCLKGATE_CON(2), 1, GFLAGS),
+	COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
+			RV1106_VOCLKSEL_CON(3), 5, 5, DFLAGS,
+			RV1106_VOCLKGATE_CON(2), 2, GFLAGS),
+	GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0,
+			RV1106_VOCLKGATE_CON(0), 13, GFLAGS),
+	GATE(DCLK_VOP, "dclk_vop", "dclk_vop_src", 0,
+			RV1106_VOCLKGATE_CON(0), 14, GFLAGS),
+	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,
+			RV1106_VOCLKGATE_CON(0), 15, GFLAGS),
+
+	/* IO CLK */
+	GATE(RX0PCLK_VICAP, "rx0pclk_vicap", "rx0pclk_vicap_io", 0,
+			RV1106_VICLKGATE_CON(1), 0, GFLAGS),
+	GATE(RX1PCLK_VICAP, "rx1pclk_vicap", "rx1pclk_vicap_io", 0,
+			RV1106_VICLKGATE_CON(1), 1, GFLAGS),
+	GATE(ISP0CLK_VICAP, "isp0clk_vicap", "isp0clk_vicap_io", 0,
+			RV1106_VICLKGATE_CON(1), 2, GFLAGS),
+	GATE(I0CLK_VICAP, "i0clk_vicap", "i0clk_vicap_io", 0,
+			RV1106_VICLKGATE_CON(0), 14, GFLAGS),
+	GATE(I1CLK_VICAP, "i1clk_vicap", "i1clk_vicap_io", 0,
+			RV1106_VICLKGATE_CON(0), 15, GFLAGS),
+	GATE(PCLK_VICAP, "pclk_vicap", "pclk_vicap_io", 0,
+			RV1106_VICLKGATE_CON(0), 11, GFLAGS),
+	GATE(CLK_RXBYTECLKHS_0, "clk_rxbyteclkhs_0", "clk_rxbyteclkhs_0_io", 0,
+			RV1106_VICLKGATE_CON(1), 4, GFLAGS),
+	GATE(CLK_RXBYTECLKHS_1, "clk_rxbyteclkhs_1", "clk_rxbyteclkhs_1_io", 0,
+			RV1106_VICLKGATE_CON(1), 6, GFLAGS),
+
+	GATE(PCLK_VICAP_VEPU, "pclk_vicap_vepu", "pclk_vicap_vepu_io", 0,
+			RV1106_VEPUCLKGATE_CON(0), 14, GFLAGS),
+	GATE(SCLK_IN_SPI0, "sclk_in_spi0", "sclk_in_spi0_io", 0,
+			RV1106_VEPUCLKGATE_CON(1), 4, GFLAGS),
+
+	GATE(CLK_UTMI_USBOTG, "clk_utmi_usbotg", "clk_utmi_usbotg_io", 0,
+			RV1106_PERICLKGATE_CON(4), 9, GFLAGS),
+};
+
+static struct rockchip_clk_branch rv1106_grf_clk_branches[] __initdata = {
+	MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_src_emmc", RV1106_EMMC_CON0, 1),
+	MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_src_emmc", RV1106_EMMC_CON1, 1),
+	MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "cclk_src_sdmmc", RV1106_SDMMC_CON0, 1),
+	MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "cclk_src_sdmmc", RV1106_SDMMC_CON1, 1),
+	MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RV1106_SDIO_CON0, 1),
+	MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RV1106_SDIO_CON1, 1),
+};
+
+static void __init rv1106_pvtpll_init(struct rockchip_clk_provider *ctx)
+{
+	/* set pvtpll ref clk mux */
+	writel_relaxed(CPU_PVTPLL_PATH_CORE, ctx->reg_base + CPU_CLK_PATH_BASE);
+
+	if (!IS_ERR(ctx->grf)) {
+		regmap_write(ctx->grf, CPU_PVTPLL_CON0_H,
+			     HIWORD_UPDATE(0x7, PVTPLL_LENGTH_SEL_MASK,
+					   PVTPLL_LENGTH_SEL_SHIFT));
+		regmap_write(ctx->grf, CPU_PVTPLL_CON0_L,
+			     HIWORD_UPDATE(0x1, PVTPLL_RING_SEL_MASK,
+					   PVTPLL_RING_SEL_SHIFT));
+		regmap_write(ctx->grf, CPU_PVTPLL_CON0_L,
+			     HIWORD_UPDATE(0x3, PVTPLL_EN_MASK,
+					   PVTPLL_EN_SHIFT));
+	}
+
+	writel_relaxed(0x007f0000, ctx->reg_base + CRU_PVTPLL0_CON0_H);
+	writel_relaxed(0xffff0018, ctx->reg_base + CRU_PVTPLL0_CON1_L);
+	writel_relaxed(0xffff0004, ctx->reg_base + CRU_PVTPLL0_CON2_H);
+	writel_relaxed(0x00030003, ctx->reg_base + CRU_PVTPLL0_CON0_L);
+
+	writel_relaxed(0x007f0000, ctx->reg_base + CRU_PVTPLL1_CON0_H);
+	writel_relaxed(0xffff0018, ctx->reg_base + CRU_PVTPLL1_CON1_L);
+	writel_relaxed(0xffff0004, ctx->reg_base + CRU_PVTPLL1_CON2_H);
+	writel_relaxed(0x00030003, ctx->reg_base + CRU_PVTPLL1_CON0_L);
+}
+
+static void __init rv1106_clk_init(struct device_node *np)
+{
+	struct rockchip_clk_provider *ctx;
+	unsigned long clk_nr;
+	void __iomem *reg_base;
+
+	clk_nr = rockchip_clk_find_max_clk_id(rv1106_clk_branches,
+					      ARRAY_SIZE(rv1106_clk_branches)) + 1;
+	reg_base = of_iomap(np, 0);
+	if (!reg_base) {
+		pr_err("%s: could not map cru region\n", __func__);
+		return;
+	}
+
+	ctx = rockchip_clk_init(np, reg_base, clk_nr);
+	if (IS_ERR(ctx)) {
+		pr_err("%s: rockchip clk init failed\n", __func__);
+		iounmap(reg_base);
+		return;
+	}
+
+	rv1106_pvtpll_init(ctx);
+
+	rockchip_clk_register_plls(ctx, rv1106_pll_clks,
+				   ARRAY_SIZE(rv1106_pll_clks),
+				   RV1106_GRF_SOC_STATUS0);
+
+	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
+				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+				     &rv1106_cpuclk_data, rv1106_cpuclk_rates,
+				     ARRAY_SIZE(rv1106_cpuclk_rates));
+
+	rockchip_clk_register_branches(ctx, rv1106_clk_branches,
+				       ARRAY_SIZE(rv1106_clk_branches));
+
+	rockchip_register_restart_notifier(ctx, RV1106_GLB_SRST_FST, NULL);
+
+	rockchip_clk_of_add_provider(np, ctx);
+}
+
+CLK_OF_DECLARE(rv1106_cru, "rockchip,rv1106-cru", rv1106_clk_init);
+
+static void __init rv1106_grf_clk_init(struct device_node *np)
+{
+	struct rockchip_clk_provider *ctx;
+	struct device_node *parent_np;
+	unsigned long clk_nr;
+	void __iomem *reg_base;
+
+	clk_nr = rockchip_clk_find_max_clk_id(rv1106_grf_clk_branches,
+					      ARRAY_SIZE(rv1106_grf_clk_branches)) + 1;
+	parent_np = of_get_parent(np);
+	reg_base = of_iomap(parent_np, 0);
+	of_node_put(parent_np);
+	if (!reg_base) {
+		pr_err("%s: could not map cru grf region\n", __func__);
+		return;
+	}
+
+	ctx = rockchip_clk_init(np, reg_base, clk_nr);
+	if (IS_ERR(ctx)) {
+		pr_err("%s: rockchip grf clk init failed\n", __func__);
+		iounmap(reg_base);
+		return;
+	}
+
+	rockchip_clk_register_branches(ctx, rv1106_grf_clk_branches,
+				       ARRAY_SIZE(rv1106_grf_clk_branches));
+
+	rockchip_clk_of_add_provider(np, ctx);
+}
+
+CLK_OF_DECLARE(rv1106_grf_cru, "rockchip,rv1106-grf-cru", rv1106_grf_clk_init);
-- 
2.43.0

Re: [PATCH 00/12] Add support for the Rockchip RV1106 and RV1103

[Fabio Estevam]

Hi Simon,

On Monday, July 06, 2026 16:57 -03, Simon Glass <sjg@chromium.org> wrote:

> The series follows the structure of the recently merged RV1103B
> support. The clock driver is ported from the vendor kernel and is the

When I submitted the initial version of the RV1103B series, I received feedback to split it into subsystems. 

You should do the same here and submit it per subsystem:
ARM, clock, pinctrl, serial, mmc, watchdog, and iio.

Re: [PATCH 00/12] Add support for the Rockchip RV1106 and RV1103

[Heiko Stübner]

Am Dienstag, 7. Juli 2026, 00:54:44 Mitteleuropäische Sommerzeit schrieb Fabio Estevam:
> Hi Simon,
> 
> On Monday, July 06, 2026 16:57 -03, Simon Glass <sjg@chromium.org> wrote:
> 
> > The series follows the structure of the recently merged RV1103B
> > support. The clock driver is ported from the vendor kernel and is the
> 
> When I submitted the initial version of the RV1103B series, I received feedback to split it into subsystems. 
> 
> You should do the same here and submit it per subsystem:
> ARM, clock, pinctrl, serial, mmc, watchdog, and iio.

correct ... ARM + clock can stay together, as that is my stuff, but for a
lot of maintainer it is just way easier to not have to pick apart series' .
(or even realize they are meant to do something)

Re: [PATCH 01/12] dt-bindings: clock: rockchip: Add RV1106 CRU support

[Jonas Karlman]

Hi Simon,

On 7/6/2026 9:57 PM, Simon Glass wrote:
> Add the clock binding header and schema for the Rockchip RV1106 clock
> and reset unit. The clock IDs match the numbering used by the vendor
> kernel so that existing devicetrees keep working. The header also
> covers the GRF clock controller, which provides the MMC drive and
> sample phase clocks.
> 
> The RV1103 is a package variant of the RV1106 and uses the same CRU.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> 
>  .../bindings/clock/rockchip,rv1106-cru.yaml   |  59 ++++
>  .../dt-bindings/clock/rockchip,rv1106-cru.h   | 301 ++++++++++++++++++
>  2 files changed, 360 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
>  create mode 100644 include/dt-bindings/clock/rockchip,rv1106-cru.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
> new file mode 100644
> index 000000000000..884a4a8bb0fb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,rv1106-cru.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip RV1106 Clock and Reset Unit
> +
> +maintainers:
> +  - Simon Glass <sjg@chromium.org>
> +  - Heiko Stuebner <heiko@sntech.de>
> +
> +description:
> +  The RV1106 clock controller generates the clock and also implements a
> +  reset controller for SoC peripherals.
> +
> +properties:
> +  compatible:
> +    const: rockchip,rv1106-cru
> +
> +  reg:
> +    maxItems: 1
> +
> +  "#clock-cells":
> +    const: 1
> +
> +  "#reset-cells":
> +    const: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    const: xin24m
> +
> +  rockchip,grf:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      Phandle to the syscon managing the "general register files" (GRF),
> +      if missing pll rates are not changeable, due to the missing pll
> +      lock status.
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#clock-cells"
> +  - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    clock-controller@ff3b0000 {
> +      compatible = "rockchip,rv1106-cru";
> +      reg = <0xff3b0000 0x20000>;
> +      rockchip,grf = <&grf>;
> +      #clock-cells = <1>;
> +      #reset-cells = <1>;
> +    };
> diff --git a/include/dt-bindings/clock/rockchip,rv1106-cru.h b/include/dt-bindings/clock/rockchip,rv1106-cru.h
> new file mode 100644
> index 000000000000..acbf9c1ee6af
> --- /dev/null
> +++ b/include/dt-bindings/clock/rockchip,rv1106-cru.h
> @@ -0,0 +1,301 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
> + * Author: Elaine Zhang <zhangqing@rock-chips.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
> +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
> +
> +/* pll clocks */
> +#define PLL_APLL		1

Clock indices should start at 0 and be a continuous enumeration.

> +#define PLL_DPLL		2
> +#define PLL_CPLL		3
> +#define PLL_GPLL		4
> +#define ARMCLK			5
> +
> +/* clk (clocks) */
> +#define PCLK_DDRPHY		11

As mentioned above, indices should be a continuous enumeration.

> +#define PCLK_DDR_ROOT		12
> +#define PCLK_DDRMON		13
> +#define CLK_TIMER_DDRMON	14
> +#define PCLK_DDRC		15
> +#define PCLK_DFICTRL		16
> +#define ACLK_DDR_ROOT		17
> +#define ACLK_SYS_SHRM		18
> +#define HCLK_NPU_ROOT		19

[snip]

> +/* mmc phase clocks provided by the grf-cru */
> +#define SCLK_EMMC_DRV		1
> +#define SCLK_EMMC_SAMPLE	2
> +#define SCLK_SDMMC_DRV		3
> +#define SCLK_SDMMC_SAMPLE	4
> +#define SCLK_SDIO_DRV		5
> +#define SCLK_SDIO_SAMPLE	6

For other Rockchip SoCs the grf clocks have been exposed from the CRU,
please take a look at e.g. SCLK_SDMMC_DRV and other similar clocks for
RK3528.

Regards,
Jonas

> +
> +#endif