From: Stephen Boyd <sboyd@kernel.org>
To: Jay Buddhabhatti <jay.buddhabhatti@amd.com>,
michal.simek@amd.com, mturquette@baylibre.com,
shubhrajyoti.datta@xilinx.com
Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Subject: Re: [PATCH RESEND v2 2/2] drivers: clk: zynqmp: update divider round rate logic
Date: Sat, 16 Dec 2023 17:21:08 -0800 [thread overview]
Message-ID: <752b98e31a2b9e4cf0aec860f158c53c.sboyd@kernel.org> (raw)
In-Reply-To: <20231129112916.23125-3-jay.buddhabhatti@amd.com>
Quoting Jay Buddhabhatti (2023-11-29 03:29:16)
> Currently zynqmp divider round rate is considering single parent and
> calculating rate and parent rate accordingly. But if divider clock flag
> is set to SET_RATE_PARENT then its not trying to traverse through all
> parent rate and not selecting best parent rate from that. So use common
> divider_round_rate() which is traversing through all clock parents and
> its rate and calculating proper parent rate.
>
> Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver")
> Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
> ---
Applied to clk-next
next prev parent reply other threads:[~2023-12-17 1:21 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-29 11:29 [PATCH RESEND v2 0/2] update for versal net platform Jay Buddhabhatti
2023-11-29 11:29 ` [PATCH RESEND v2 1/2] drivers: clk: zynqmp: calculate closest mux rate Jay Buddhabhatti
2023-12-17 1:21 ` Stephen Boyd
2023-11-29 11:29 ` [PATCH RESEND v2 2/2] drivers: clk: zynqmp: update divider round rate logic Jay Buddhabhatti
2023-12-17 1:21 ` Stephen Boyd [this message]
-- strict thread matches above, loose matches on Subject: below --
2023-11-09 12:05 [PATCH RESEND v2 0/2] update for versal net platform Jay Buddhabhatti
2023-11-09 12:05 ` [PATCH RESEND v2 2/2] drivers: clk: zynqmp: update divider round rate logic Jay Buddhabhatti
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