From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, magnus.damm@gmail.com,
linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH 3/7] clk: renesas: rzg2l-cpg: Add support for MSTOP in clock enable/disable API
Date: Fri, 9 May 2025 13:58:37 +0300 [thread overview]
Message-ID: <8a14cf38-9a7b-462b-80d1-ec5026b5a565@tuxon.dev> (raw)
In-Reply-To: <CAMuHMdU00apiWYCPiwqGr66Ucg9KgWMhhm8FW_KBoeN2ceos+w@mail.gmail.com>
Hi, Geert,
On 07.05.2025 18:47, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Thu, 10 Apr 2025 at 16:06, Claudiu <claudiu.beznea@tuxon.dev> wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> The RZ/{G2L, V2L, G3S} CPG versions support a feature called MSTOP. Each
>> module has one or more MSTOP bits associated with it, and these bits need
>> to be configured along with the module clocks. Setting the MSTOP bits
>> switches the module between normal and standby states.
>>
>> Previously, MSTOP support was abstracted through power domains
>> (struct generic_pm_domain::{power_on, power_off} APIs). With this
>> abstraction, the order of setting the MSTOP and CLKON bits was as follows:
>>
>> Previous Order:
>> A/ Switching to Normal State (e.g., during probe):
>> 1/ Clear module MSTOP bits
>> 2/ Set module CLKON bits
>>
>> B/ Switching to Standby State (e.g., during remove):
>> 1/ Clear CLKON bits
>> 2/ Set MSTOP bits
>>
>> However, in some cases (when the clock is disabled through devres), the
>> order may have been (due to the issue described in link section):
>>
>> 1/ Set MSTOP bits
>> 2/ Clear CLKON bits
>>
>> Recently, the hardware team has suggested that the correct order to set
>> the MSTOP and CLKON bits is:
>>
>> Updated Order:
>> A/ Switching to Normal State (e.g., during probe):
>> 1/ Set CLKON bits
>> 2/ Clear MSTOP bits
>
> What is the recommended order in case multiple clocks map to
> the same module? Clear the MSTOP bit(s) after enabling the first clock,
> or clear the MSTOP bit(s) after enabling all clocks?
I can't find anything about this in the HW manual.
> I believe the code implements the former?
The proposed implementation clears the MSTOP after enabling the first clock
taking into account that there might be cases where 2 clocks sharing the
same MSTOP may not be both enabled for a particular functionality.
Thank you for your review,
Claudiu
next prev parent reply other threads:[~2025-05-09 10:58 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-10 14:06 [PATCH 0/7] clk: renesas: rzg2l-cpg: Drop PM domain abstraction for MSTOP Claudiu
2025-04-10 14:06 ` [PATCH 1/7] clk: renesas: rzg2l-cpg: Skip lookup of clock when searching for a sibling Claudiu
2025-05-05 15:52 ` Geert Uytterhoeven
2025-05-07 12:12 ` Claudiu Beznea
2025-05-08 13:55 ` Geert Uytterhoeven
2025-04-10 14:06 ` [PATCH 2/7] clk: renesas: rzg2l-cpg: Move pointers at the beginning of struct Claudiu
2025-05-05 15:53 ` Geert Uytterhoeven
2025-05-07 12:13 ` Claudiu Beznea
2025-04-10 14:06 ` [PATCH 3/7] clk: renesas: rzg2l-cpg: Add support for MSTOP in clock enable/disable API Claudiu
2025-05-07 15:42 ` Geert Uytterhoeven
2025-05-09 10:54 ` Claudiu Beznea
2025-05-09 12:34 ` Geert Uytterhoeven
2025-05-13 12:34 ` Claudiu Beznea
2025-05-13 14:07 ` Geert Uytterhoeven
2025-05-13 15:36 ` Claudiu Beznea
2025-05-07 15:47 ` Geert Uytterhoeven
2025-05-09 10:58 ` Claudiu Beznea [this message]
2025-05-09 12:12 ` Geert Uytterhoeven
2025-05-09 12:44 ` Claudiu Beznea
2025-04-10 14:06 ` [PATCH 4/7] clk: renesas: r9a08g045: Drop power domain instantiation Claudiu
2025-05-07 17:10 ` Geert Uytterhoeven
2025-05-09 11:03 ` Claudiu Beznea
2025-04-10 14:06 ` [PATCH 5/7] clk: renesas: rzg2l-cpg: Drop MSTOP based power domain support Claudiu
2025-05-07 17:15 ` Geert Uytterhoeven
2025-04-10 14:06 ` [PATCH 6/7] dt-bindings: clock: rzg2l-cpg: Drop power domain IDs Claudiu
2025-04-15 19:16 ` Rob Herring (Arm)
2025-05-07 17:17 ` Geert Uytterhoeven
2025-04-10 14:06 ` [PATCH 7/7] Revert "dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S" Claudiu
2025-04-15 19:16 ` Rob Herring (Arm)
2025-05-07 17:18 ` Geert Uytterhoeven
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