* [PATCH] clk: renesas: r8a779h0: Add watchdog clock
@ 2024-02-01 12:21 Geert Uytterhoeven
2024-02-03 17:36 ` Wolfram Sang
0 siblings, 1 reply; 2+ messages in thread
From: Geert Uytterhoeven @ 2024-02-01 12:21 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-renesas-soc, linux-clk, Cong Dang, Geert Uytterhoeven
From: Cong Dang <cong.dang.xn@renesas.com>
Add the module clock used by the RCLK Watchdog Timer on the Renesas
R-Car V4M (R8A779H0) SoC.
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
To be queued in renesas-clk for v6.9.
drivers/clk/renesas/r8a779h0-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index 219941047291d34d..322db567d5f889d6 100644
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -177,6 +177,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
DEF_MOD("hscif3", 517, R8A779H0_CLK_SASYNCPERD1),
+ DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
DEF_MOD("pfc0", 915, R8A779H0_CLK_CP),
DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
--
2.34.1
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] clk: renesas: r8a779h0: Add watchdog clock
2024-02-01 12:21 [PATCH] clk: renesas: r8a779h0: Add watchdog clock Geert Uytterhoeven
@ 2024-02-03 17:36 ` Wolfram Sang
0 siblings, 0 replies; 2+ messages in thread
From: Wolfram Sang @ 2024-02-03 17:36 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-renesas-soc, linux-clk,
Cong Dang
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On Thu, Feb 01, 2024 at 01:21:55PM +0100, Geert Uytterhoeven wrote:
> From: Cong Dang <cong.dang.xn@renesas.com>
>
> Add the module clock used by the RCLK Watchdog Timer on the Renesas
> R-Car V4M (R8A779H0) SoC.
>
> Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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2024-02-01 12:21 [PATCH] clk: renesas: r8a779h0: Add watchdog clock Geert Uytterhoeven
2024-02-03 17:36 ` Wolfram Sang
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