* [PATCH 2/2] clk: tegra: Micro-optimize Tegra210 clock setup
2016-06-23 10:52 [PATCH 1/2] clk: tegra: Make sor_safe the parent of dpaux and dpaux1 Thierry Reding
@ 2016-06-23 10:52 ` Thierry Reding
2016-06-23 12:26 ` Jon Hunter
2016-06-23 15:28 ` Rhyland Klein
2016-06-23 12:25 ` [PATCH 1/2] clk: tegra: Make sor_safe the parent of dpaux and dpaux1 Jon Hunter
2016-06-23 15:27 ` Rhyland Klein
2 siblings, 2 replies; 6+ messages in thread
From: Thierry Reding @ 2016-06-23 10:52 UTC (permalink / raw)
To: Thierry Reding
Cc: Peter De Schrijver, Rhyland Klein, Jon Hunter, linux-tegra,
linux-clk
From: Thierry Reding <treding@nvidia.com>
sor_safe being the parent of the dpaux and dpaux1 clocks, it's not only
natural, but also slightly more efficient, to initialize it before its
children. This avoids orphaning the dpaux and dpaux1 clocks only to get
them reparented when the sor_safe clock is registered.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/clk/tegra/clk-tegra210.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index fe295b4102ca..b4df5c46642f 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2466,6 +2466,10 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
1, 2);
clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
+ clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
+ 1, 17, 222);
+ clks[TEGRA210_CLK_SOR_SAFE] = clk;
+
clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
1, 17, 181);
clks[TEGRA210_CLK_DPAUX] = clk;
@@ -2474,10 +2478,6 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
1, 17, 207);
clks[TEGRA210_CLK_DPAUX1] = clk;
- clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
- 1, 17, 222);
- clks[TEGRA210_CLK_SOR_SAFE] = clk;
-
/* pll_d_dsi_out */
clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
--
2.8.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] clk: tegra: Micro-optimize Tegra210 clock setup
2016-06-23 10:52 ` [PATCH 2/2] clk: tegra: Micro-optimize Tegra210 clock setup Thierry Reding
@ 2016-06-23 12:26 ` Jon Hunter
2016-06-23 15:28 ` Rhyland Klein
1 sibling, 0 replies; 6+ messages in thread
From: Jon Hunter @ 2016-06-23 12:26 UTC (permalink / raw)
To: Thierry Reding; +Cc: Peter De Schrijver, Rhyland Klein, linux-tegra, linux-clk
On 23/06/16 11:52, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> sor_safe being the parent of the dpaux and dpaux1 clocks, it's not only
> natural, but also slightly more efficient, to initialize it before its
> children. This avoids orphaning the dpaux and dpaux1 clocks only to get
> them reparented when the sor_safe clock is registered.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index fe295b4102ca..b4df5c46642f 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -2466,6 +2466,10 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
> 1, 2);
> clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
>
> + clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
> + 1, 17, 222);
> + clks[TEGRA210_CLK_SOR_SAFE] = clk;
> +
> clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
> 1, 17, 181);
> clks[TEGRA210_CLK_DPAUX] = clk;
> @@ -2474,10 +2478,6 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
> 1, 17, 207);
> clks[TEGRA210_CLK_DPAUX1] = clk;
>
> - clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
> - 1, 17, 222);
> - clks[TEGRA210_CLK_SOR_SAFE] = clk;
> -
> /* pll_d_dsi_out */
> clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
> clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] clk: tegra: Micro-optimize Tegra210 clock setup
2016-06-23 10:52 ` [PATCH 2/2] clk: tegra: Micro-optimize Tegra210 clock setup Thierry Reding
2016-06-23 12:26 ` Jon Hunter
@ 2016-06-23 15:28 ` Rhyland Klein
1 sibling, 0 replies; 6+ messages in thread
From: Rhyland Klein @ 2016-06-23 15:28 UTC (permalink / raw)
To: Thierry Reding; +Cc: Peter De Schrijver, Jon Hunter, linux-tegra, linux-clk
On 6/23/2016 6:52 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> sor_safe being the parent of the dpaux and dpaux1 clocks, it's not only
> natural, but also slightly more efficient, to initialize it before its
> children. This avoids orphaning the dpaux and dpaux1 clocks only to get
> them reparented when the sor_safe clock is registered.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index fe295b4102ca..b4df5c46642f 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -2466,6 +2466,10 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
> 1, 2);
> clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
>
> + clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
> + 1, 17, 222);
> + clks[TEGRA210_CLK_SOR_SAFE] = clk;
> +
> clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
> 1, 17, 181);
> clks[TEGRA210_CLK_DPAUX] = clk;
> @@ -2474,10 +2478,6 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
> 1, 17, 207);
> clks[TEGRA210_CLK_DPAUX1] = clk;
>
> - clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
> - 1, 17, 222);
> - clks[TEGRA210_CLK_SOR_SAFE] = clk;
> -
> /* pll_d_dsi_out */
> clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
> clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
>
Acked-by: Rhyland Klein <rklein@nvidia.com>
--
nvpublic
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] clk: tegra: Make sor_safe the parent of dpaux and dpaux1
2016-06-23 10:52 [PATCH 1/2] clk: tegra: Make sor_safe the parent of dpaux and dpaux1 Thierry Reding
2016-06-23 10:52 ` [PATCH 2/2] clk: tegra: Micro-optimize Tegra210 clock setup Thierry Reding
@ 2016-06-23 12:25 ` Jon Hunter
2016-06-23 15:27 ` Rhyland Klein
2 siblings, 0 replies; 6+ messages in thread
From: Jon Hunter @ 2016-06-23 12:25 UTC (permalink / raw)
To: Thierry Reding; +Cc: Peter De Schrijver, Rhyland Klein, linux-tegra, linux-clk
On 23/06/16 11:52, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> It turns out that sor_safe, rather than pll_p, is the parent of the
> dpaux and dpaux1 clocks.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index aab32af77aa2..fe295b4102ca 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -2466,11 +2466,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
> 1, 2);
> clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
>
> - clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base,
> + clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
> 1, 17, 181);
> clks[TEGRA210_CLK_DPAUX] = clk;
>
> - clk = tegra_clk_register_periph_fixed("dpaux1", "pll_p", 0, clk_base,
> + clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
> 1, 17, 207);
> clks[TEGRA210_CLK_DPAUX1] = clk;
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 1/2] clk: tegra: Make sor_safe the parent of dpaux and dpaux1
2016-06-23 10:52 [PATCH 1/2] clk: tegra: Make sor_safe the parent of dpaux and dpaux1 Thierry Reding
2016-06-23 10:52 ` [PATCH 2/2] clk: tegra: Micro-optimize Tegra210 clock setup Thierry Reding
2016-06-23 12:25 ` [PATCH 1/2] clk: tegra: Make sor_safe the parent of dpaux and dpaux1 Jon Hunter
@ 2016-06-23 15:27 ` Rhyland Klein
2 siblings, 0 replies; 6+ messages in thread
From: Rhyland Klein @ 2016-06-23 15:27 UTC (permalink / raw)
To: Thierry Reding; +Cc: Peter De Schrijver, Jon Hunter, linux-tegra, linux-clk
On 6/23/2016 6:52 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> It turns out that sor_safe, rather than pll_p, is the parent of the
> dpaux and dpaux1 clocks.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index aab32af77aa2..fe295b4102ca 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -2466,11 +2466,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
> 1, 2);
> clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
>
> - clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base,
> + clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
> 1, 17, 181);
> clks[TEGRA210_CLK_DPAUX] = clk;
>
> - clk = tegra_clk_register_periph_fixed("dpaux1", "pll_p", 0, clk_base,
> + clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
> 1, 17, 207);
> clks[TEGRA210_CLK_DPAUX1] = clk;
>
>
Acked-by: Rhyland Klein <rklein@nvidia.com>
--
nvpublic
^ permalink raw reply [flat|nested] 6+ messages in thread