* [PATCH] clk: imx6ull: use OSC clock during AXI rate change
@ 2018-04-18 12:49 Stefan Agner
2018-05-02 7:38 ` Shawn Guo
0 siblings, 1 reply; 9+ messages in thread
From: Stefan Agner @ 2018-04-18 12:49 UTC (permalink / raw)
To: shawnguo, kernel
Cc: fabio.estevam, mturquette, sboyd, linux-arm-kernel, linux-clk,
linux-kernel, Stefan Agner
On i.MX6 ULL using PLL3 seems to cause a freeze when setting
the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear
since commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag
for busy divider and busy mux"), probably because the clock is
now forced to be on.
Fixes: 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux")
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
This addresses a regression ssen on v4.17-rc1 where the kernel
boots during clock initialization, see also:
https://patchwork.kernel.org/patch/10295927/
drivers/clk/imx/clk-imx6ul.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 114ecbb94ec5..12320118f8de 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -464,7 +464,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);
/* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
- clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
+ clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_OSC]);
clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]);
clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]);
clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]);
--
2.17.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
2018-04-18 12:49 [PATCH] clk: imx6ull: use OSC clock during AXI rate change Stefan Agner
@ 2018-05-02 7:38 ` Shawn Guo
2018-05-07 12:56 ` Stefan Agner
0 siblings, 1 reply; 9+ messages in thread
From: Shawn Guo @ 2018-05-02 7:38 UTC (permalink / raw)
To: Stefan Agner, Jacky Bai
Cc: kernel, fabio.estevam, mturquette, sboyd, linux-arm-kernel,
linux-clk, linux-kernel
Hi Jacky,
Do you see this problem on i.MX6 ULL? What's your take on Stefan's fix?
Shawn
On Wed, Apr 18, 2018 at 02:49:08PM +0200, Stefan Agner wrote:
> On i.MX6 ULL using PLL3 seems to cause a freeze when setting
> the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear
> since commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag
> for busy divider and busy mux"), probably because the clock is
> now forced to be on.
>
> Fixes: 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux")
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
> This addresses a regression ssen on v4.17-rc1 where the kernel
> boots during clock initialization, see also:
> https://patchwork.kernel.org/patch/10295927/
>
> drivers/clk/imx/clk-imx6ul.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
> index 114ecbb94ec5..12320118f8de 100644
> --- a/drivers/clk/imx/clk-imx6ul.c
> +++ b/drivers/clk/imx/clk-imx6ul.c
> @@ -464,7 +464,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
> clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);
>
> /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
> - clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
> + clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_OSC]);
> clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]);
> clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]);
> clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]);
> --
> 2.17.0
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
2018-05-02 7:38 ` Shawn Guo
@ 2018-05-07 12:56 ` Stefan Agner
2018-05-08 7:32 ` Jacky Bai
0 siblings, 1 reply; 9+ messages in thread
From: Stefan Agner @ 2018-05-07 12:56 UTC (permalink / raw)
To: Jacky Bai, Shawn Guo
Cc: kernel, fabio.estevam, mturquette, sboyd, linux-arm-kernel,
linux-clk, linux-kernel
Hi Jacky,
On 02.05.2018 09:38, Shawn Guo wrote:
> Hi Jacky,
>
> Do you see this problem on i.MX6 ULL? What's your take on Stefan's fix?
Any comment to this?
It is 4.17.0-rc4 is out and i.MX 6ULL is still broken :-(
--
Stefan
>
> Shawn
>
> On Wed, Apr 18, 2018 at 02:49:08PM +0200, Stefan Agner wrote:
>> On i.MX6 ULL using PLL3 seems to cause a freeze when setting
>> the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear
>> since commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag
>> for busy divider and busy mux"), probably because the clock is
>> now forced to be on.
>>
>> Fixes: 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux")
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>> ---
>> This addresses a regression ssen on v4.17-rc1 where the kernel
>> boots during clock initialization, see also:
>> https://patchwork.kernel.org/patch/10295927/
>>
>> drivers/clk/imx/clk-imx6ul.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
>> index 114ecbb94ec5..12320118f8de 100644
>> --- a/drivers/clk/imx/clk-imx6ul.c
>> +++ b/drivers/clk/imx/clk-imx6ul.c
>> @@ -464,7 +464,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
>> clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);
>>
>> /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
>> - clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
>> + clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_OSC]);
>> clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]);
>> clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]);
>> clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]);
>> --
>> 2.17.0
>>
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
2018-05-07 12:56 ` Stefan Agner
@ 2018-05-08 7:32 ` Jacky Bai
2018-05-08 13:20 ` Stefan Agner
0 siblings, 1 reply; 9+ messages in thread
From: Jacky Bai @ 2018-05-08 7:32 UTC (permalink / raw)
To: Stefan Agner, Shawn Guo
Cc: kernel@pengutronix.de, Fabio Estevam, mturquette@baylibre.com,
sboyd@kernel.org, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
>=20
> Hi Jacky,
>=20
> On 02.05.2018 09:38, Shawn Guo wrote:
> > Hi Jacky,
> >
> > Do you see this problem on i.MX6 ULL? What's your take on Stefan's fix=
?
>=20
> Any comment to this?
>=20
> It is 4.17.0-rc4 is out and i.MX 6ULL is still broken :-(
>=20
Hi Stefan,
I have tried two 6ULL board, I don't meet such issue. System can boot up su=
ccessfully with commit 6f9575e55632 included.
Anyway, the change in this patch is ok for me. it is no harm to the BUS clo=
ck change flow.
Jacky
> --
> Stefan
>=20
> >
> > Shawn
> >
> > On Wed, Apr 18, 2018 at 02:49:08PM +0200, Stefan Agner wrote:
> >> On i.MX6 ULL using PLL3 seems to cause a freeze when setting the
> >> parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear since
> >> commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag for busy
> >> divider and busy mux"), probably because the clock is now forced to
> >> be on.
> >>
> >> Fixes: 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy
> >> divider and busy mux")
> >> Signed-off-by: Stefan Agner <stefan@agner.ch>
> >> ---
> >> This addresses a regression ssen on v4.17-rc1 where the kernel boots
> >> during clock initialization, see also:
> >>
> https://emea01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fpa
> >>
> tchwork.kernel.org%2Fpatch%2F10295927%2F&data=3D02%7C01%7Cping.bai%
> 40nx
> >>
> p.com%7C023287ec65034c4db45f08d5b419effb%7C686ea1d3bc2b4c6fa92cd9
> 9c5c
> >>
> 301635%7C0%7C0%7C636612945852594725&sdata=3DU0ZGid9ZBey0FXfId2dhZb
> hVl8p
> >> CcjTiexG3JHYwCA4%3D&reserved=3D0
> >>
> >> drivers/clk/imx/clk-imx6ul.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/clk/imx/clk-imx6ul.c
> >> b/drivers/clk/imx/clk-imx6ul.c index 114ecbb94ec5..12320118f8de
> >> 100644
> >> --- a/drivers/clk/imx/clk-imx6ul.c
> >> +++ b/drivers/clk/imx/clk-imx6ul.c
> >> @@ -464,7 +464,7 @@ static void __init imx6ul_clocks_init(struct
> device_node *ccm_node)
> >> clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);
> >>
> >> /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz
> */
> >> - clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL],
> clks[IMX6UL_CLK_PLL3_USB_OTG]);
> >> + clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL],
> >> +clks[IMX6UL_CLK_OSC]);
> >> clk_set_parent(clks[IMX6UL_CLK_PERIPH],
> clks[IMX6UL_CLK_PERIPH_CLK2]);
> >> clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE],
> clks[IMX6UL_CLK_PLL2_BUS]);
> >> clk_set_parent(clks[IMX6UL_CLK_PERIPH],
> >> clks[IMX6UL_CLK_PERIPH_PRE]);
> >> --
> >> 2.17.0
> >>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
2018-05-08 7:32 ` Jacky Bai
@ 2018-05-08 13:20 ` Stefan Agner
2018-05-08 18:19 ` Stephen Boyd
0 siblings, 1 reply; 9+ messages in thread
From: Stefan Agner @ 2018-05-08 13:20 UTC (permalink / raw)
To: Jacky Bai
Cc: Shawn Guo, kernel, Fabio Estevam, mturquette, sboyd,
linux-arm-kernel, linux-clk, linux-kernel
On 08.05.2018 09:32, Jacky Bai wrote:
>> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
>>
>> Hi Jacky,
>>
>> On 02.05.2018 09:38, Shawn Guo wrote:
>> > Hi Jacky,
>> >
>> > Do you see this problem on i.MX6 ULL? What's your take on Stefan's fix?
>>
>> Any comment to this?
>>
>> It is 4.17.0-rc4 is out and i.MX 6ULL is still broken :-(
>>
> Hi Stefan,
>
> I have tried two 6ULL board, I don't meet such issue. System can boot
> up successfully with commit 6f9575e55632 included.
> Anyway, the change in this patch is ok for me. it is no harm to the
> BUS clock change flow.
Hm, that is interesting, maybe it is because we use a different SKU? Or
maybe bootloader?
I tested here with a 800 MHz clocked variant on a Colibri iMX6ULL using
U-Boot 2016.11.
--
Stefan
>
> Jacky
>> --
>> Stefan
>>
>> >
>> > Shawn
>> >
>> > On Wed, Apr 18, 2018 at 02:49:08PM +0200, Stefan Agner wrote:
>> >> On i.MX6 ULL using PLL3 seems to cause a freeze when setting the
>> >> parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear since
>> >> commit 6f9575e55632 ("clk: imx: Add CLK_IS_CRITICAL flag for busy
>> >> divider and busy mux"), probably because the clock is now forced to
>> >> be on.
>> >>
>> >> Fixes: 6f9575e55632("clk: imx: Add CLK_IS_CRITICAL flag for busy
>> >> divider and busy mux")
>> >> Signed-off-by: Stefan Agner <stefan@agner.ch>
>> >> ---
>> >> This addresses a regression ssen on v4.17-rc1 where the kernel boots
>> >> during clock initialization, see also:
>> >>
>> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpa
>> >>
>> tchwork.kernel.org%2Fpatch%2F10295927%2F&data=02%7C01%7Cping.bai%
>> 40nx
>> >>
>> p.com%7C023287ec65034c4db45f08d5b419effb%7C686ea1d3bc2b4c6fa92cd9
>> 9c5c
>> >>
>> 301635%7C0%7C0%7C636612945852594725&sdata=U0ZGid9ZBey0FXfId2dhZb
>> hVl8p
>> >> CcjTiexG3JHYwCA4%3D&reserved=0
>> >>
>> >> drivers/clk/imx/clk-imx6ul.c | 2 +-
>> >> 1 file changed, 1 insertion(+), 1 deletion(-)
>> >>
>> >> diff --git a/drivers/clk/imx/clk-imx6ul.c
>> >> b/drivers/clk/imx/clk-imx6ul.c index 114ecbb94ec5..12320118f8de
>> >> 100644
>> >> --- a/drivers/clk/imx/clk-imx6ul.c
>> >> +++ b/drivers/clk/imx/clk-imx6ul.c
>> >> @@ -464,7 +464,7 @@ static void __init imx6ul_clocks_init(struct
>> device_node *ccm_node)
>> >> clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);
>> >>
>> >> /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz
>> */
>> >> - clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL],
>> clks[IMX6UL_CLK_PLL3_USB_OTG]);
>> >> + clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL],
>> >> +clks[IMX6UL_CLK_OSC]);
>> >> clk_set_parent(clks[IMX6UL_CLK_PERIPH],
>> clks[IMX6UL_CLK_PERIPH_CLK2]);
>> >> clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE],
>> clks[IMX6UL_CLK_PLL2_BUS]);
>> >> clk_set_parent(clks[IMX6UL_CLK_PERIPH],
>> >> clks[IMX6UL_CLK_PERIPH_PRE]);
>> >> --
>> >> 2.17.0
>> >>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
2018-05-08 13:20 ` Stefan Agner
@ 2018-05-08 18:19 ` Stephen Boyd
2018-05-09 1:26 ` Jacky Bai
0 siblings, 1 reply; 9+ messages in thread
From: Stephen Boyd @ 2018-05-08 18:19 UTC (permalink / raw)
To: Jacky Bai, Stefan Agner
Cc: Shawn Guo, kernel, Fabio Estevam, mturquette, linux-arm-kernel,
linux-clk, linux-kernel
Quoting Stefan Agner (2018-05-08 06:20:03)
> On 08.05.2018 09:32, Jacky Bai wrote:
> > =
> > I have tried two 6ULL board, I don't meet such issue. System can boot
> > up successfully with commit 6f9575e55632 included.
> > Anyway, the change in this patch is ok for me. it is no harm to the
> > BUS clock change flow.
> =
> Hm, that is interesting, maybe it is because we use a different SKU? Or
> maybe bootloader?
> =
> I tested here with a 800 MHz clocked variant on a Colibri iMX6ULL using
> U-Boot 2016.11.
> =
I'll throw this into fixes today because it fixes something to be
useful. It's still interesting to see what's different between the two
setups though.
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
2018-05-08 18:19 ` Stephen Boyd
@ 2018-05-09 1:26 ` Jacky Bai
2018-05-09 14:12 ` Stefan Agner
0 siblings, 1 reply; 9+ messages in thread
From: Jacky Bai @ 2018-05-09 1:26 UTC (permalink / raw)
To: Stephen Boyd, Stefan Agner
Cc: Shawn Guo, kernel@pengutronix.de, Fabio Estevam,
mturquette@baylibre.com, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
PiBTdWJqZWN0OiBSZTogW1BBVENIXSBjbGs6IGlteDZ1bGw6IHVzZSBPU0MgY2xvY2sgZHVyaW5n
IEFYSSByYXRlIGNoYW5nZQ0KPiANCj4gUXVvdGluZyBTdGVmYW4gQWduZXIgKDIwMTgtMDUtMDgg
MDY6MjA6MDMpDQo+ID4gT24gMDguMDUuMjAxOCAwOTozMiwgSmFja3kgQmFpIHdyb3RlOg0KPiA+
ID4NCj4gPiA+IEkgaGF2ZSB0cmllZCB0d28gNlVMTCBib2FyZCwgSSBkb24ndCBtZWV0IHN1Y2gg
aXNzdWUuIFN5c3RlbSBjYW4NCj4gPiA+IGJvb3QgdXAgc3VjY2Vzc2Z1bGx5IHdpdGggY29tbWl0
IDZmOTU3NWU1NTYzMiBpbmNsdWRlZC4NCj4gPiA+IEFueXdheSwgdGhlIGNoYW5nZSBpbiB0aGlz
IHBhdGNoIGlzIG9rIGZvciBtZS4gaXQgaXMgbm8gaGFybSB0byB0aGUNCj4gPiA+IEJVUyBjbG9j
ayBjaGFuZ2UgZmxvdy4NCj4gPg0KPiA+IEhtLCB0aGF0IGlzIGludGVyZXN0aW5nLCBtYXliZSBp
dCBpcyBiZWNhdXNlIHdlIHVzZSBhIGRpZmZlcmVudCBTS1U/DQo+ID4gT3IgbWF5YmUgYm9vdGxv
YWRlcj8NCj4gPg0KPiA+IEkgdGVzdGVkIGhlcmUgd2l0aCBhIDgwMCBNSHogY2xvY2tlZCB2YXJp
YW50IG9uIGEgQ29saWJyaSBpTVg2VUxMDQo+ID4gdXNpbmcgVS1Cb290IDIwMTYuMTEuDQo+ID4N
Cj4gDQo+IEknbGwgdGhyb3cgdGhpcyBpbnRvIGZpeGVzIHRvZGF5IGJlY2F1c2UgaXQgZml4ZXMg
c29tZXRoaW5nIHRvIGJlIHVzZWZ1bC4gSXQncyBzdGlsbA0KPiBpbnRlcmVzdGluZyB0byBzZWUg
d2hhdCdzIGRpZmZlcmVudCBiZXR3ZWVuIHRoZSB0d28gc2V0dXBzIHRob3VnaC4NCg0KVGhhbmtz
LiANCg0KSSB3aWxsIGZpbmQgc29tZSA4MDBNSHogcGFydHMgYW5kIGhhdmUgYSB0cnkgd2l0aCBk
aWZmZXJlbnQgYm9vdGxvYWRlciBsYXRlci4NCldpbGwgbGV0IHlvdSBrbm93LCB3aGVuIEkgaGF2
ZSBzb21lIHJlc3VsdHMuDQoNCkphY2t5DQo=
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
2018-05-09 1:26 ` Jacky Bai
@ 2018-05-09 14:12 ` Stefan Agner
2018-05-10 1:53 ` Jacky Bai
0 siblings, 1 reply; 9+ messages in thread
From: Stefan Agner @ 2018-05-09 14:12 UTC (permalink / raw)
To: Jacky Bai
Cc: Stephen Boyd, Shawn Guo, kernel, Fabio Estevam, mturquette,
linux-arm-kernel, linux-clk, linux-kernel
On 09.05.2018 03:26, Jacky Bai wrote:
>> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
>>
>> Quoting Stefan Agner (2018-05-08 06:20:03)
>> > On 08.05.2018 09:32, Jacky Bai wrote:
>> > >
>> > > I have tried two 6ULL board, I don't meet such issue. System can
>> > > boot up successfully with commit 6f9575e55632 included.
>> > > Anyway, the change in this patch is ok for me. it is no harm to the
>> > > BUS clock change flow.
>> >
>> > Hm, that is interesting, maybe it is because we use a different SKU?
>> > Or maybe bootloader?
>> >
>> > I tested here with a 800 MHz clocked variant on a Colibri iMX6ULL
>> > using U-Boot 2016.11.
>> >
>>
>> I'll throw this into fixes today because it fixes something to be useful. It's still
>> interesting to see what's different between the two setups though.
>
> Thanks.
>
> I will find some 800MHz parts and have a try with different bootloader later.
> Will let you know, when I have some results.
>
FWIW, I tried two SKUs here:
MCIMX6Z2DVM05AA (528Mhz)
MCIMX6Z2CVM08AA (800MHz)
Both run at 396MHz in U-Boot, and both freeze and the same location.
--
Stefan
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
2018-05-09 14:12 ` Stefan Agner
@ 2018-05-10 1:53 ` Jacky Bai
0 siblings, 0 replies; 9+ messages in thread
From: Jacky Bai @ 2018-05-10 1:53 UTC (permalink / raw)
To: Stefan Agner
Cc: Stephen Boyd, Shawn Guo, kernel@pengutronix.de, Fabio Estevam,
mturquette@baylibre.com, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate change
>=20
> On 09.05.2018 03:26, Jacky Bai wrote:
> >> Subject: Re: [PATCH] clk: imx6ull: use OSC clock during AXI rate
> >> change
> >>
> >> Quoting Stefan Agner (2018-05-08 06:20:03)
> >> > On 08.05.2018 09:32, Jacky Bai wrote:
> >> > >
> >> > > I have tried two 6ULL board, I don't meet such issue. System can
> >> > > boot up successfully with commit 6f9575e55632 included.
> >> > > Anyway, the change in this patch is ok for me. it is no harm to
> >> > > the BUS clock change flow.
> >> >
> >> > Hm, that is interesting, maybe it is because we use a different SKU?
> >> > Or maybe bootloader?
> >> >
> >> > I tested here with a 800 MHz clocked variant on a Colibri iMX6ULL
> >> > using U-Boot 2016.11.
> >> >
> >>
> >> I'll throw this into fixes today because it fixes something to be
> >> useful. It's still interesting to see what's different between the two=
setups
> though.
> >
> > Thanks.
> >
> > I will find some 800MHz parts and have a try with different bootloader =
later.
> > Will let you know, when I have some results.
> >
>=20
> FWIW, I tried two SKUs here:
> MCIMX6Z2DVM05AA (528Mhz)
> MCIMX6Z2CVM08AA (800MHz)
>=20
MCIMX6Z or MCIMX6Y ? I think i.MX6ULL should be 6Y.
Jacky
> Both run at 396MHz in U-Boot, and both freeze and the same location.
>=20
> --
> Stefan
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-05-10 1:53 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-04-18 12:49 [PATCH] clk: imx6ull: use OSC clock during AXI rate change Stefan Agner
2018-05-02 7:38 ` Shawn Guo
2018-05-07 12:56 ` Stefan Agner
2018-05-08 7:32 ` Jacky Bai
2018-05-08 13:20 ` Stefan Agner
2018-05-08 18:19 ` Stephen Boyd
2018-05-09 1:26 ` Jacky Bai
2018-05-09 14:12 ` Stefan Agner
2018-05-10 1:53 ` Jacky Bai
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