[PATCH] clk: renesas: r8a78000: Add SGASYNCD8_PERW_BUS

[PATCH] clk: renesas: r8a78000: Add SGASYNCD8_PERW_BUS

[Geert Uytterhoeven]

From: Wolfram Sang <wsa+renesas@sang-engineering.com>

Add support for the SGASYNCD8_PERW_BUS clock, which is a fixed 133 MHz
clock serving as the functional clock parent for I2C cores 1 to 8.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
To be queued in renesas-clk for v7.4.

 drivers/clk/renesas/r8a78000-cpg.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/renesas/r8a78000-cpg.c b/drivers/clk/renesas/r8a78000-cpg.c
index 7946f9d0b423def1..b8024e76743ea53d 100644
--- a/drivers/clk/renesas/r8a78000-cpg.c
+++ b/drivers/clk/renesas/r8a78000-cpg.c
@@ -23,12 +23,14 @@ struct clk_map {
 
 enum fixed_clk {
 	FIXED_CLK_66M,
+	FIXED_CLK_133M,
 	FIXED_CLK_266M,
 	NUM_FIXED_CLKS
 };
 
 static const unsigned long fixed_clk_rates[NUM_FIXED_CLKS] = {
 	[FIXED_CLK_66M] = 66666000,
+	[FIXED_CLK_133M] = 133330000,
 	[FIXED_CLK_266M] = 266660000,
 };
 
@@ -140,6 +142,7 @@ static int r8a78000_cpg_probe(struct platform_device *pdev)
 
 static const struct clk_map r8a78000_cpg_default[] = {
 	{ R8A78000_CPG_SGASYNCD4_PERW_BUS,	FIXED_CLK(266M) },
+	{ R8A78000_CPG_SGASYNCD8_PERW_BUS,	FIXED_CLK(133M) },
 	{ R8A78000_CPG_SGASYNCD16_PERW_BUS,	FIXED_CLK(66M) },
 	{ -1 }
 };
-- 
2.43.0

Re: [PATCH] clk: renesas: r8a78000: Add SGASYNCD8_PERW_BUS

[Wolfram Sang]

On Fri, Sep 25, 2026 at 10:56:14AM +0200, Geert Uytterhoeven wrote:
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
> 
> Add support for the SGASYNCD8_PERW_BUS clock, which is a fixed 133 MHz
> clock serving as the functional clock parent for I2C cores 1 to 8.
> 
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thank you for constant forward-porting this patch to your latest base
work!