Re: [PATCH v2 1/3] clk: divider: Fix the divisor for rates above 4.29 GHz

[Sebastian Reichel <sebastian.reichel@collabora.com>]

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Hi,

On Thu, Nov 12, 2026 at 04:29:55PM +0100, Carlo Caione wrote:
> On Thu, Nov 12, 2026 at 10:09:46 +0100, Brian Masney wrote:
> > Hi Carlo,
> 
> Hi Brian,
> 
> > >  static int _div_round_up(const struct clk_div_table *table,
> > >  			 unsigned long parent_rate, unsigned long rate,
> > >  			 unsigned long flags)
> > >  {
> > > -	int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
> > > +	int div = _get_div_round_up(parent_rate, rate);
> > 
> > _get_div_round_up() returns an unsigned long however it's downsized to
> > an int here.
> 
> Right, but wasn't also DIV_ROUND_UP_ULL() previously returning a u64
> that was stored in the same int?

I would also argue, that this is a separate fix. Looking at the code
involved it goes all the way down to this incorrectly using int for
a clock rate:

/*
 * ...
 * @determine_rate: Given a target rate as input, returns the closest rate
 *		actually supported by the clock, and optionally the parent clock
 *		that should be used to provide the clock rate.
 * ...
 */
struct clk_ops {
    ...
    int (*determine_rate)(struct clk_hw *hw,
                          struct clk_rate_request *req);
    ...
}

Fixing that will be a bigger task.

Greetings,

-- Sebastian

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