From: sashiko-bot@kernel.org
To: "Carlo Caione" <ccaione@baylibre.com>
Cc: linux-clk@vger.kernel.org
Subject: Re: [PATCH v2 3/3] clk: divider: test: Add tests for rates above 4.29 GHz
Date: Thu, 12 Nov 2026 09:50:39 +0000 [thread overview]
Message-ID: <sashiko-outbox-210906@kernel.org> (raw)
In-Reply-To: <20261112-upstream-clk-divider-large-rates-v2-3-18f3bb888b0c@baylibre.com>
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] clk: divider: test: unlocked clk_hw_round_rate() calls trigger
lockdep warning
--
commit 25eaef0a68df414370fdc908fa118bc3dbfa005e
Author: Carlo Caione <ccaione@baylibre.com>
clk: divider: test: Add tests for rates above 4.29 GHz
This commit adds KUnit test suites for clk dividers covering rates above
4.29 GHz on 64-bit platforms and round-closest dividers requested above
their parent rate.
> diff --git a/drivers/clk/clk-divider_test.c b/drivers/clk/clk-divider_test.c
> index 8ee1614128d09..734cbdad55ddf 100644
> --- a/drivers/clk/clk-divider_test.c
> +++ b/drivers/clk/clk-divider_test.c
[ ... ]
> +static void clk_divider_large_rate_round_up(struct kunit *test)
> +{
> + struct clk_hw *div_hw;
> + u32 *fake_reg;
> +
> + fake_reg = kunit_kzalloc(test, sizeof(*fake_reg), GFP_KERNEL);
> + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, fake_reg);
> +
> + div_hw = clk_divider_large_rate_init(test, fake_reg, PARENT_RATE_6GHZ,
> + 0, 0);
> +
> + KUNIT_EXPECT_EQ(test, clk_hw_round_rate(div_hw, PARENT_RATE_6GHZ),
> + PARENT_RATE_6GHZ);
> +}
[Severity: Low]
Does calling clk_hw_round_rate() here (and in the other rounding test
cases below) trigger a lockdep warning when CONFIG_LOCKDEP is enabled?
clk_hw_round_rate() is a provider helper that expects prepare_lock to be
held and calls clk_core_init_rate_req() and clk_core_round_rate_nolock(),
which assert lockdep_assert_held(&prepare_lock). Obtaining a struct clk
via clk_hw_get_clk_kunit() and calling clk_round_rate() instead would
acquire prepare_lock properly.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261112-upstream-clk-divider-large-rates-v2-0-18f3bb888b0c@baylibre.com?part=3
prev parent reply other threads:[~2026-11-12 9:50 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-12 9:36 [PATCH v2 0/3] Fix clk-divider rates above 4.29 GHz on 64-bit Carlo Caione
2026-11-12 9:36 ` [PATCH v2 1/3] clk: divider: Fix the divisor for rates above 4.29 GHz Carlo Caione
2026-11-12 15:09 ` Brian Masney
2026-11-12 15:29 ` Carlo Caione
2026-11-12 15:38 ` Sebastian Reichel
2026-11-12 15:34 ` Sebastian Reichel
2026-11-12 9:37 ` [PATCH v2 2/3] clk: divider: Fix round-closest for rates above the parent rate Carlo Caione
2026-11-12 15:41 ` Sebastian Reichel
2026-11-12 9:37 ` [PATCH v2 3/3] clk: divider: test: Add tests for rates above 4.29 GHz Carlo Caione
2026-11-12 9:50 ` sashiko-bot [this message]
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