[PATCH 0/3] clk: qcom: Add dfs support for QUPv3 RCGs on SM8150

Linux clock framework development
 help / color / mirror / Atom feed

* [PATCH 0/3] clk: qcom: Add dfs support for QUPv3 RCGs on SM8150
@ 2024-01-04 14:23 Satya Priya Kakitapalli
  2024-01-04 14:23 ` [PATCH 1/3] clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS " Satya Priya Kakitapalli
                   ` (2 more replies)
  0 siblings, 3 replies; 11+ messages in thread
From: Satya Priya Kakitapalli @ 2024-01-04 14:23 UTC (permalink / raw)
  To: Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd,
	Deepak Katragadda, Vinod Koul, Taniya Das, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley
  Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, Ajit Pandey,
	Imran Shaik, Jagadeesh Kona, Satya Priya Kakitapalli

Add dfs support and missing resets for SM8150 global clock
controller.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
Satya Priya Kakitapalli (3):
      clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS on SM8150
      dt-bindings: clock: Update the gcc resets for sm8150
      clk: qcom: gcc-sm8150: Update the gcc resets

 drivers/clk/qcom/gcc-sm8150.c               | 354 +++++++++++++++++-----------
 include/dt-bindings/clock/qcom,gcc-sm8150.h |   3 +
 2 files changed, 217 insertions(+), 140 deletions(-)
---
base-commit: ab0b3e6ef50d305278b1971891cf1d82ab050b35
change-id: 20240104-sm8150-dfs-support-087ce1773183

Best regards,
-- 
Satya Priya Kakitapalli <quic_skakitap@quicinc.com>


^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH 1/3] clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS on SM8150
  2024-01-04 14:23 [PATCH 0/3] clk: qcom: Add dfs support for QUPv3 RCGs on SM8150 Satya Priya Kakitapalli
@ 2024-01-04 14:23 ` Satya Priya Kakitapalli
  2024-01-04 15:44   ` Krzysztof Kozlowski
  2024-01-04 21:36   ` Stephen Boyd
  2024-01-04 14:23 ` [PATCH 2/3] dt-bindings: clock: Update the gcc resets for sm8150 Satya Priya Kakitapalli
  2024-01-04 14:23 ` [PATCH 3/3] clk: qcom: gcc-sm8150: Update the gcc resets Satya Priya Kakitapalli
  2 siblings, 2 replies; 11+ messages in thread
From: Satya Priya Kakitapalli @ 2024-01-04 14:23 UTC (permalink / raw)
  To: Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd,
	Deepak Katragadda, Vinod Koul, Taniya Das, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley
  Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, Ajit Pandey,
	Imran Shaik, Jagadeesh Kona, Satya Priya Kakitapalli

QUPv3 clocks support DFS and thus register the RCGs which require
support for the same.

Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150")
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
 drivers/clk/qcom/gcc-sm8150.c | 351 +++++++++++++++++++++++++-----------------
 1 file changed, 211 insertions(+), 140 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index 05d115c52dfe..6d76fd344ddf 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -453,19 +453,29 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 	{ }
 };
 
+static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
+	.name = "gcc_qupv3_wrap0_s0_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
+};
+
 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 	.cmd_rcgr = 0x17148,
 	.mnd_width = 16,
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap0_s0_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
+	.name = "gcc_qupv3_wrap0_s1_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
@@ -474,13 +484,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap0_s1_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
+	.name = "gcc_qupv3_wrap0_s2_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
@@ -489,13 +501,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap0_s2_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
+	.name = "gcc_qupv3_wrap0_s3_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
@@ -504,13 +518,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap0_s3_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
+	.name = "gcc_qupv3_wrap0_s4_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
@@ -519,13 +535,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap0_s4_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
+	.name = "gcc_qupv3_wrap0_s5_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
@@ -534,13 +552,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap0_s5_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
+	.name = "gcc_qupv3_wrap0_s6_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
@@ -549,13 +569,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap0_s6_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
+	.name = "gcc_qupv3_wrap0_s7_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
@@ -564,13 +586,15 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap0_s7_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
+	.name = "gcc_qupv3_wrap1_s0_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@@ -579,13 +603,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap1_s0_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
+	.name = "gcc_qupv3_wrap1_s1_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@@ -594,13 +620,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap1_s1_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
+	.name = "gcc_qupv3_wrap1_s2_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@@ -609,13 +637,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap1_s2_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
+	.name = "gcc_qupv3_wrap1_s3_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@@ -624,13 +654,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap1_s3_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
+	.name = "gcc_qupv3_wrap1_s4_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@@ -639,13 +671,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap1_s4_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
+	.name = "gcc_qupv3_wrap1_s5_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@@ -654,13 +688,15 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap1_s5_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
+	.name = "gcc_qupv3_wrap2_s0_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
@@ -669,13 +705,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap2_s0_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
+	.name = "gcc_qupv3_wrap2_s1_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
@@ -684,13 +722,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap2_s1_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
+	.name = "gcc_qupv3_wrap2_s2_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
@@ -699,13 +739,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap2_s2_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
+	.name = "gcc_qupv3_wrap2_s3_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
@@ -714,13 +756,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap2_s3_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
+	.name = "gcc_qupv3_wrap2_s4_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
@@ -729,13 +773,15 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap2_s4_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
+	.name = "gcc_qupv3_wrap2_s5_clk_src",
+	.parent_data = gcc_parents_0,
+	.num_parents = ARRAY_SIZE(gcc_parents_0),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
@@ -744,13 +790,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
 	.hid_width = 5,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-	.clkr.hw.init = &(struct clk_init_data){
-		.name = "gcc_qupv3_wrap2_s5_clk_src",
-		.parent_data = gcc_parents_0,
-		.num_parents = ARRAY_SIZE(gcc_parents_0),
-		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
-	},
+	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
 };
 
 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
@@ -3750,6 +3790,29 @@ static struct gdsc *gcc_sm8150_gdscs[] = {
 	[USB30_SEC_GDSC] = &usb30_sec_gdsc,
 };
 
+static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
+	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
+};
+
 static const struct regmap_config gcc_sm8150_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
@@ -3777,6 +3840,7 @@ MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
 static int gcc_sm8150_probe(struct platform_device *pdev)
 {
 	struct regmap *regmap;
+	int ret;
 
 	regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
 	if (IS_ERR(regmap))
@@ -3786,6 +3850,13 @@ static int gcc_sm8150_probe(struct platform_device *pdev)
 	regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
 	regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
 
+	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
+				       ARRAY_SIZE(gcc_dfs_clocks));
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to register with DFS!\n");
+		return ret;
+	}
+
 	return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
 }
 

-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread

* Re: [PATCH 1/3] clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS on SM8150
  2024-01-04 14:23 ` [PATCH 1/3] clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS " Satya Priya Kakitapalli
@ 2024-01-04 15:44   ` Krzysztof Kozlowski
  2024-01-04 21:36   ` Stephen Boyd
  1 sibling, 0 replies; 11+ messages in thread
From: Krzysztof Kozlowski @ 2024-01-04 15:44 UTC (permalink / raw)
  To: Satya Priya Kakitapalli, Bjorn Andersson, Konrad Dybcio,
	Michael Turquette, Stephen Boyd, Deepak Katragadda, Vinod Koul,
	Taniya Das, Rob Herring, Krzysztof Kozlowski, Conor Dooley
  Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, Ajit Pandey,
	Imran Shaik, Jagadeesh Kona

On 04/01/2024 15:23, Satya Priya Kakitapalli wrote:
> QUPv3 clocks support DFS and thus register the RCGs which require
> support for the same.
> 
> Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150")

Please describe user-observable issues you are fixing here. It's not
obvious to me.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH 1/3] clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS on SM8150
  2024-01-04 14:23 ` [PATCH 1/3] clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS " Satya Priya Kakitapalli
  2024-01-04 15:44   ` Krzysztof Kozlowski
@ 2024-01-04 21:36   ` Stephen Boyd
  2024-01-10 10:31     ` Satya Priya Kakitapalli (Temp)
  1 sibling, 1 reply; 11+ messages in thread
From: Stephen Boyd @ 2024-01-04 21:36 UTC (permalink / raw)
  To: Bjorn Andersson, Conor Dooley, Deepak Katragadda, Konrad Dybcio,
	Krzysztof Kozlowski, Michael Turquette, Rob Herring,
	Satya Priya Kakitapalli, Taniya Das, Vinod Koul
  Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, Ajit Pandey,
	Imran Shaik, Jagadeesh Kona, Satya Priya Kakitapalli

Quoting Satya Priya Kakitapalli (2024-01-04 06:23:04)
> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> index 05d115c52dfe..6d76fd344ddf 100644
> --- a/drivers/clk/qcom/gcc-sm8150.c
> +++ b/drivers/clk/qcom/gcc-sm8150.c
> @@ -453,19 +453,29 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
>         { }
>  };
>  
> +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {

Can these be const?

> +       .name = "gcc_qupv3_wrap0_s0_clk_src",
> +       .parent_data = gcc_parents_0,
> +       .num_parents = ARRAY_SIZE(gcc_parents_0),
> +       .flags = CLK_SET_RATE_PARENT,
> +       .ops = &clk_rcg2_ops,
> +};
> +
>  static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
>         .cmd_rcgr = 0x17148,
>         .mnd_width = 16,
>         .hid_width = 5,
>         .parent_map = gcc_parent_map_0,
>         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
> -       .clkr.hw.init = &(struct clk_init_data){
> -               .name = "gcc_qupv3_wrap0_s0_clk_src",
[...]
> @@ -3786,6 +3850,13 @@ static int gcc_sm8150_probe(struct platform_device *pdev)
>         regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
>         regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
>  
> +       ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
> +                                      ARRAY_SIZE(gcc_dfs_clocks));
> +       if (ret) {
> +               dev_err(&pdev->dev, "Failed to register with DFS!\n");

Use 

		return dev_err_probe(...);

^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH 1/3] clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS on SM8150
  2024-01-04 21:36   ` Stephen Boyd
@ 2024-01-10 10:31     ` Satya Priya Kakitapalli (Temp)
  0 siblings, 0 replies; 11+ messages in thread
From: Satya Priya Kakitapalli (Temp) @ 2024-01-10 10:31 UTC (permalink / raw)
  To: Stephen Boyd, Bjorn Andersson, Conor Dooley, Deepak Katragadda,
	Konrad Dybcio, Krzysztof Kozlowski, Michael Turquette,
	Rob Herring, Taniya Das, Vinod Koul
  Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, Ajit Pandey,
	Imran Shaik, Jagadeesh Kona


On 1/5/2024 3:06 AM, Stephen Boyd wrote:
> Quoting Satya Priya Kakitapalli (2024-01-04 06:23:04)
>> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
>> index 05d115c52dfe..6d76fd344ddf 100644
>> --- a/drivers/clk/qcom/gcc-sm8150.c
>> +++ b/drivers/clk/qcom/gcc-sm8150.c
>> @@ -453,19 +453,29 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
>>          { }
>>   };
>>   
>> +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
> Can these be const?


We update the ops inside the qcom_cc_register_rcg_dfs. Hence cannot make 
this as const.


>> +       .name = "gcc_qupv3_wrap0_s0_clk_src",
>> +       .parent_data = gcc_parents_0,
>> +       .num_parents = ARRAY_SIZE(gcc_parents_0),
>> +       .flags = CLK_SET_RATE_PARENT,
>> +       .ops = &clk_rcg2_ops,
>> +};
>> +
>>   static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
>>          .cmd_rcgr = 0x17148,
>>          .mnd_width = 16,
>>          .hid_width = 5,
>>          .parent_map = gcc_parent_map_0,
>>          .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
>> -       .clkr.hw.init = &(struct clk_init_data){
>> -               .name = "gcc_qupv3_wrap0_s0_clk_src",
> [...]
>> @@ -3786,6 +3850,13 @@ static int gcc_sm8150_probe(struct platform_device *pdev)
>>          regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
>>          regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
>>   
>> +       ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
>> +                                      ARRAY_SIZE(gcc_dfs_clocks));
>> +       if (ret) {
>> +               dev_err(&pdev->dev, "Failed to register with DFS!\n");
> Use
>
> 		return dev_err_probe(...);


Okay.


^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH 2/3] dt-bindings: clock: Update the gcc resets for sm8150
  2024-01-04 14:23 [PATCH 0/3] clk: qcom: Add dfs support for QUPv3 RCGs on SM8150 Satya Priya Kakitapalli
  2024-01-04 14:23 ` [PATCH 1/3] clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS " Satya Priya Kakitapalli
@ 2024-01-04 14:23 ` Satya Priya Kakitapalli
  2024-01-04 15:43   ` Krzysztof Kozlowski
  2024-01-04 14:23 ` [PATCH 3/3] clk: qcom: gcc-sm8150: Update the gcc resets Satya Priya Kakitapalli
  2 siblings, 1 reply; 11+ messages in thread
From: Satya Priya Kakitapalli @ 2024-01-04 14:23 UTC (permalink / raw)
  To: Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd,
	Deepak Katragadda, Vinod Koul, Taniya Das, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley
  Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, Ajit Pandey,
	Imran Shaik, Jagadeesh Kona, Satya Priya Kakitapalli

Add all the available resets for the global clock controller
on sm8150.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
 include/dt-bindings/clock/qcom,gcc-sm8150.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
index dfefd5e8bf6e..921a33f24d33 100644
--- a/include/dt-bindings/clock/qcom,gcc-sm8150.h
+++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
@@ -239,6 +239,9 @@
 #define GCC_USB30_PRIM_BCR					26
 #define GCC_USB30_SEC_BCR					27
 #define GCC_USB_PHY_CFG_AHB2PHY_BCR				28
+#define GCC_VIDEO_AXIC_CLK_BCR					29
+#define GCC_VIDEO_AXI0_CLK_BCR					30
+#define GCC_VIDEO_AXI1_CLK_BCR					31
 
 /* GCC GDSCRs */
 #define PCIE_0_GDSC						0

-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread

* Re: [PATCH 2/3] dt-bindings: clock: Update the gcc resets for sm8150
  2024-01-04 14:23 ` [PATCH 2/3] dt-bindings: clock: Update the gcc resets for sm8150 Satya Priya Kakitapalli
@ 2024-01-04 15:43   ` Krzysztof Kozlowski
  2024-01-10  9:45     ` Satya Priya Kakitapalli (Temp)
  0 siblings, 1 reply; 11+ messages in thread
From: Krzysztof Kozlowski @ 2024-01-04 15:43 UTC (permalink / raw)
  To: Satya Priya Kakitapalli, Bjorn Andersson, Konrad Dybcio,
	Michael Turquette, Stephen Boyd, Deepak Katragadda, Vinod Koul,
	Taniya Das, Rob Herring, Krzysztof Kozlowski, Conor Dooley
  Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, Ajit Pandey,
	Imran Shaik, Jagadeesh Kona

On 04/01/2024 15:23, Satya Priya Kakitapalli wrote:
> Add all the available resets for the global clock controller
> on sm8150.
> 
> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
> ---

Subject:
Everything can be an update. You also miss prefix. Instead:
dt-bindings: clock: qcom,gcc-sm8150: Add Video camcc whatever foobar
reset IDs

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH 2/3] dt-bindings: clock: Update the gcc resets for sm8150
  2024-01-04 15:43   ` Krzysztof Kozlowski
@ 2024-01-10  9:45     ` Satya Priya Kakitapalli (Temp)
  0 siblings, 0 replies; 11+ messages in thread
From: Satya Priya Kakitapalli (Temp) @ 2024-01-10  9:45 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio,
	Michael Turquette, Stephen Boyd, Deepak Katragadda, Vinod Koul,
	Taniya Das, Rob Herring, Krzysztof Kozlowski, Conor Dooley
  Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, Ajit Pandey,
	Imran Shaik, Jagadeesh Kona


On 1/4/2024 9:13 PM, Krzysztof Kozlowski wrote:
> On 04/01/2024 15:23, Satya Priya Kakitapalli wrote:
>> Add all the available resets for the global clock controller
>> on sm8150.
>>
>> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
>> ---
> Subject:
> Everything can be an update. You also miss prefix. Instead:
> dt-bindings: clock: qcom,gcc-sm8150: Add Video camcc whatever foobar
> reset IDs


Okay, will update the subject.


> Best regards,
> Krzysztof
>

^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH 3/3] clk: qcom: gcc-sm8150: Update the gcc resets
  2024-01-04 14:23 [PATCH 0/3] clk: qcom: Add dfs support for QUPv3 RCGs on SM8150 Satya Priya Kakitapalli
  2024-01-04 14:23 ` [PATCH 1/3] clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS " Satya Priya Kakitapalli
  2024-01-04 14:23 ` [PATCH 2/3] dt-bindings: clock: Update the gcc resets for sm8150 Satya Priya Kakitapalli
@ 2024-01-04 14:23 ` Satya Priya Kakitapalli
  2024-01-04 15:44   ` Krzysztof Kozlowski
  2 siblings, 1 reply; 11+ messages in thread
From: Satya Priya Kakitapalli @ 2024-01-04 14:23 UTC (permalink / raw)
  To: Bjorn Andersson, Konrad Dybcio, Michael Turquette, Stephen Boyd,
	Deepak Katragadda, Vinod Koul, Taniya Das, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley
  Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, Ajit Pandey,
	Imran Shaik, Jagadeesh Kona, Satya Priya Kakitapalli

Add all the available resets for the global clock controller
on sm8150.

Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150")
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
---
 drivers/clk/qcom/gcc-sm8150.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index 6d76fd344ddf..833e64b61e6b 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -3778,6 +3778,9 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = {
 	[GCC_USB30_PRIM_BCR] = { 0xf000 },
 	[GCC_USB30_SEC_BCR] = { 0x10000 },
 	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+	[GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },
+	[GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 },
+	[GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 },
 };
 
 static struct gdsc *gcc_sm8150_gdscs[] = {

-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread

* Re: [PATCH 3/3] clk: qcom: gcc-sm8150: Update the gcc resets
  2024-01-04 14:23 ` [PATCH 3/3] clk: qcom: gcc-sm8150: Update the gcc resets Satya Priya Kakitapalli
@ 2024-01-04 15:44   ` Krzysztof Kozlowski
  2024-01-10 10:28     ` Satya Priya Kakitapalli (Temp)
  0 siblings, 1 reply; 11+ messages in thread
From: Krzysztof Kozlowski @ 2024-01-04 15:44 UTC (permalink / raw)
  To: Satya Priya Kakitapalli, Bjorn Andersson, Konrad Dybcio,
	Michael Turquette, Stephen Boyd, Deepak Katragadda, Vinod Koul,
	Taniya Das, Rob Herring, Krzysztof Kozlowski, Conor Dooley
  Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, Ajit Pandey,
	Imran Shaik, Jagadeesh Kona

On 04/01/2024 15:23, Satya Priya Kakitapalli wrote:
> Add all the available resets for the global clock controller
> on sm8150.
> 
> Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150")

If this is a fix, then please describe observable issue and how users
are affected. See stable kernel rules document.

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH 3/3] clk: qcom: gcc-sm8150: Update the gcc resets
  2024-01-04 15:44   ` Krzysztof Kozlowski
@ 2024-01-10 10:28     ` Satya Priya Kakitapalli (Temp)
  0 siblings, 0 replies; 11+ messages in thread
From: Satya Priya Kakitapalli (Temp) @ 2024-01-10 10:28 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio,
	Michael Turquette, Stephen Boyd, Deepak Katragadda, Vinod Koul,
	Taniya Das, Rob Herring, Krzysztof Kozlowski, Conor Dooley
  Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, Ajit Pandey,
	Imran Shaik, Jagadeesh Kona


On 1/4/2024 9:14 PM, Krzysztof Kozlowski wrote:
> On 04/01/2024 15:23, Satya Priya Kakitapalli wrote:
>> Add all the available resets for the global clock controller
>> on sm8150.
>>
>> Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150")
> If this is a fix, then please describe observable issue and how users
> are affected. See stable kernel rules document.


No issues are observed as of now, just wanted to make sure all the 
available resets are added. I'll remove the fixes tag.


> Best regards,
> Krzysztof
>

^ permalink raw reply	[flat|nested] 11+ messages in thread

end of thread, other threads:[~2024-01-10 10:31 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-01-04 14:23 [PATCH 0/3] clk: qcom: Add dfs support for QUPv3 RCGs on SM8150 Satya Priya Kakitapalli
2024-01-04 14:23 ` [PATCH 1/3] clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS " Satya Priya Kakitapalli
2024-01-04 15:44   ` Krzysztof Kozlowski
2024-01-04 21:36   ` Stephen Boyd
2024-01-10 10:31     ` Satya Priya Kakitapalli (Temp)
2024-01-04 14:23 ` [PATCH 2/3] dt-bindings: clock: Update the gcc resets for sm8150 Satya Priya Kakitapalli
2024-01-04 15:43   ` Krzysztof Kozlowski
2024-01-10  9:45     ` Satya Priya Kakitapalli (Temp)
2024-01-04 14:23 ` [PATCH 3/3] clk: qcom: gcc-sm8150: Update the gcc resets Satya Priya Kakitapalli
2024-01-04 15:44   ` Krzysztof Kozlowski
2024-01-10 10:28     ` Satya Priya Kakitapalli (Temp)

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox