[GIT PULL] clk: renesas: Updates for v6.19 (take two)

[GIT PULL] clk: renesas: Updates for v6.19 (take two)

[Geert Uytterhoeven]

	Hi Mike, Stephen,

The following changes since commit 07525a693a5ff6592668a0fd647153e4b4933cae:

  clk: renesas: r9a09g056: Add clock and reset entries for ISP (2025-10-27 12:15:00 +0100)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v6.19-tag2

for you to fetch changes up to 5fb2f67341bd4b7c482f2bbda6b78244a51c3923:

  clk: renesas: r9a09g077: Add SPI module clocks (2025-11-13 21:18:25 +0100)

----------------------------------------------------------------
clk: renesas: Updates for v6.19 (take two)

  - Add GPU clocks on R-Car V3U,
  - Add USB3.0 clocks and resets on RZ/V2H and RZ/V2N,
  - Add more serial (RSCI) clocks and resets on RZ/G3E,
  - Add SPI clocks on RZ/T2H and RZ/N2H,
  - Miscellaneous fixes and improvements.

Note that this includes DT binding definition updates for the R-Car V3U,
RZ/V2H, and RZ/V2N SoCs, which are shared by clock driver and DT source
files.

Thanks for pulling!

----------------------------------------------------------------
Biju Das (1):
      clk: renesas: r9a09g047: Add RSCI clocks/resets

Cosmin Tanislav (1):
      clk: renesas: r9a09g077: Add SPI module clocks

Geert Uytterhoeven (2):
      Merge tag 'renesas-r8a779a0-dt-binding-defs-tag2' into renesas-clk-for-v6.19
      Merge tag 'renesas-r9a09g057-dt-binding-defs-tag5' into renesas-clk-for-v6.19

Haotian Zhang (1):
      clk: renesas: r9a06g032: Fix memory leak in error path

Lad Prabhakar (7):
      clk: renesas: r9a09g077: Propagate rate changes to parent clocks
      clk: renesas: r9a09g077: Remove stray blank line
      clk: renesas: r9a09g077: Use devm_ helpers for divider clock registration
      dt-bindings: clock: renesas,r9a09g057-cpg: Add USB3.0 core clocks
      dt-bindings: clock: renesas,r9a09g056-cpg: Add USB3.0 core clocks
      clk: renesas: r9a09g057: Add USB3.0 clocks/resets
      clk: renesas: r9a09g056: Add USB3.0 clocks/resets

Niklas Söderlund (4):
      dt-bindings: clock: r8a779a0: Add ZG core clock
      clk: renesas: rcar-gen4: Add support for clock dividers in FRQCRB
      clk: renesas: r8a779a0: Add ZG Core clock
      clk: renesas: r8a779a0: Add 3DGE module clock

 drivers/clk/renesas/r8a779a0-cpg-mssr.c           |   7 +-
 drivers/clk/renesas/r9a06g032-clocks.c            |   6 +-
 drivers/clk/renesas/r9a09g047-cpg.c               | 126 ++++++++++++++++++++++
 drivers/clk/renesas/r9a09g056-cpg.c               |   9 +-
 drivers/clk/renesas/r9a09g057-cpg.c               |  16 ++-
 drivers/clk/renesas/r9a09g077-cpg.c               |  53 ++++++---
 drivers/clk/renesas/rcar-gen4-cpg.c               |   9 +-
 include/dt-bindings/clock/r8a779a0-cpg-mssr.h     |   1 +
 include/dt-bindings/clock/renesas,r9a09g056-cpg.h |   2 +
 include/dt-bindings/clock/renesas,r9a09g057-cpg.h |   4 +
 10 files changed, 209 insertions(+), 24 deletions(-)

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

Re: [GIT PULL] clk: renesas: Updates for v6.19 (take two)

[Stephen Boyd]

Quoting Geert Uytterhoeven (2025-11-14 02:30:41)
>         Hi Mike, Stephen,
> 
> The following changes since commit 07525a693a5ff6592668a0fd647153e4b4933cae:
> 
>   clk: renesas: r9a09g056: Add clock and reset entries for ISP (2025-10-27 12:15:00 +0100)
> 
> are available in the Git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v6.19-tag2
> 
> for you to fetch changes up to 5fb2f67341bd4b7c482f2bbda6b78244a51c3923:
> 
>   clk: renesas: r9a09g077: Add SPI module clocks (2025-11-13 21:18:25 +0100)
> 
> ----------------------------------------------------------------

Thanks. Pulled into clk-next