[PATCH 0/3] clk: renesas: Miscellaneous fixes and cleanups

[PATCH 0/3] clk: renesas: Miscellaneous fixes and cleanups

[Geert Uytterhoeven]

	Hi all,

This boring patch series contains a few fixes and cleanups for Renesas
clock drivers.

I intend to queue these in renesas-clk for v7.2.
Thanks for your comments!

Geert Uytterhoeven (3):
  clk: renesas: cpg-mssr: Add number of clock cells check
  clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS()
  clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable()

 drivers/clk/renesas/renesas-cpg-mssr.c |  3 +++
 drivers/clk/renesas/rzg2l-cpg.c        | 16 +++++++---------
 drivers/clk/renesas/rzg2l-cpg.h        | 13 +++++--------
 3 files changed, 15 insertions(+), 17 deletions(-)

-- 
2.43.0

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds
Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH 3/3] clk: renesas: cpg-mssr: Add number of clock cells check

[Geert Uytterhoeven]

The number of clock cells is not validated in the clock provider's
clk_src_get() callback.  Add the missing check.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/clk/renesas/renesas-cpg-mssr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 26ea85cfaa02714f..5b84cbee030b8a1e 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -370,6 +370,9 @@ struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
 	struct clk *clk;
 	int range_check;
 
+	if (clkspec->args_count != 2)
+		return ERR_PTR(-EINVAL);
+
 	switch (clkspec->args[0]) {
 	case CPG_CORE:
 		type = "core";
-- 
2.43.0

RE: [PATCH 3/3] clk: renesas: cpg-mssr: Add number of clock cells check

[Biju Das]

Hi Geert,

Thanks for the patch.

> -----Original Message-----
> From: Geert Uytterhoeven <geert+renesas@glider.be>
> Sent: 30 April 2026 16:20
> Subject: [PATCH 3/3] clk: renesas: cpg-mssr: Add number of clock cells check
> 
> The number of clock cells is not validated in the clock provider's
> clk_src_get() callback.  Add the missing check.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Cheers,
Biju

> ---
>  drivers/clk/renesas/renesas-cpg-mssr.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
> index 26ea85cfaa02714f..5b84cbee030b8a1e 100644
> --- a/drivers/clk/renesas/renesas-cpg-mssr.c
> +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
> @@ -370,6 +370,9 @@ struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
>  	struct clk *clk;
>  	int range_check;
> 
> +	if (clkspec->args_count != 2)
> +		return ERR_PTR(-EINVAL);
> +
>  	switch (clkspec->args[0]) {
>  	case CPG_CORE:
>  		type = "core";
> --
> 2.43.0

[PATCH 1/3] clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS()

[Geert Uytterhoeven]

Define DEF_MUX() using DEF_MUX_FLAGS(), to reduce duplication.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
No change in generated code.
---
 drivers/clk/renesas/rzg2l-cpg.h | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 0e63b62e84350358..33f54ba0e64ee628 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -178,22 +178,19 @@ enum clk_types {
 		 .invalid_rate = _invalid_rate, \
 		 .max_rate = _max_rate, .flag = (_clk_flags), \
 		 .notifier = _notif)
-#define DEF_MUX(_name, _id, _conf, _parent_names) \
+#define DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, _flag) \
 	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
 		 .parent_names = _parent_names, \
 		 .num_parents = ARRAY_SIZE(_parent_names), \
-		 .mux_flags = CLK_MUX_HIWORD_MASK)
+		 .mux_flags = CLK_MUX_HIWORD_MASK, \
+		 .flag = _flag)
+#define DEF_MUX(_name, _id, _conf, _parent_names) \
+	DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, 0)
 #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \
 	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
 		 .parent_names = _parent_names, \
 		 .num_parents = ARRAY_SIZE(_parent_names), \
 		 .mux_flags = CLK_MUX_READ_ONLY)
-#define DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, _flag) \
-	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
-		 .parent_names = _parent_names, \
-		 .num_parents = ARRAY_SIZE(_parent_names), \
-		 .mux_flags = CLK_MUX_HIWORD_MASK, \
-		 .flag = _flag)
 #define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk_flags, _notifier) \
 	DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, .sconf = _sconf, \
 		 .parent_names = _parent_names, \
-- 
2.43.0

RE: [PATCH 1/3] clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS()

[Biju Das]

Hi Geert,

Thanks for the patch.

> -----Original Message-----
> From: Geert Uytterhoeven <geert+renesas@glider.be>
> Sent: 30 April 2026 16:20
> Subject: [PATCH 1/3] clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS()
> 
> Define DEF_MUX() using DEF_MUX_FLAGS(), to reduce duplication.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Cheers,
Biju

> ---
> No change in generated code.
> ---
>  drivers/clk/renesas/rzg2l-cpg.h | 13 +++++--------
>  1 file changed, 5 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index
> 0e63b62e84350358..33f54ba0e64ee628 100644
> --- a/drivers/clk/renesas/rzg2l-cpg.h
> +++ b/drivers/clk/renesas/rzg2l-cpg.h
> @@ -178,22 +178,19 @@ enum clk_types {
>  		 .invalid_rate = _invalid_rate, \
>  		 .max_rate = _max_rate, .flag = (_clk_flags), \
>  		 .notifier = _notif)
> -#define DEF_MUX(_name, _id, _conf, _parent_names) \
> +#define DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, _flag) \
>  	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
>  		 .parent_names = _parent_names, \
>  		 .num_parents = ARRAY_SIZE(_parent_names), \
> -		 .mux_flags = CLK_MUX_HIWORD_MASK)
> +		 .mux_flags = CLK_MUX_HIWORD_MASK, \
> +		 .flag = _flag)
> +#define DEF_MUX(_name, _id, _conf, _parent_names) \
> +	DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, 0)
>  #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \
>  	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
>  		 .parent_names = _parent_names, \
>  		 .num_parents = ARRAY_SIZE(_parent_names), \
>  		 .mux_flags = CLK_MUX_READ_ONLY)
> -#define DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, _flag) \
> -	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
> -		 .parent_names = _parent_names, \
> -		 .num_parents = ARRAY_SIZE(_parent_names), \
> -		 .mux_flags = CLK_MUX_HIWORD_MASK, \
> -		 .flag = _flag)
>  #define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk_flags, _notifier) \
>  	DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, .sconf = _sconf, \
>  		 .parent_names = _parent_names, \
> --
> 2.43.0

[PATCH 2/3] clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable()

[Geert Uytterhoeven]

Reduce duplication by introducing mon_mask.
Eliminate an else branch by moving common parts into variable
pre-initializations.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
No change in generated code.
---
 drivers/clk/renesas/rzg2l-cpg.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index f98b6eb4f501c676..426e93dc7a9891bf 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1197,27 +1197,25 @@ static int rzg3l_cpg_pll_clk_endisable(struct clk_hw *hw, bool enable)
 {
 	struct pll_clk *pll_clk = to_pll(hw);
 	struct rzg2l_cpg_priv *priv = pll_clk->priv;
+	u32 mon_mask = RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK;
+	u32 val = RZG3L_PLL_STBY_RESETB_WEN;
 	u32 stby_offset, mon_offset;
-	u32 val, mon_val;
+	u32 mon_val = 0;
 	int ret;
 
 	stby_offset = RZG3L_PLL_STBY_OFFSET(pll_clk->conf);
 	mon_offset = RZG3L_PLL_MON_OFFSET(pll_clk->conf);
 
 	if (enable) {
-		val = RZG3L_PLL_STBY_RESETB_WEN | RZG3L_PLL_STBY_RESETB;
-		mon_val = RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK;
-	} else {
-		val = RZG3L_PLL_STBY_RESETB_WEN;
-		mon_val = 0;
+		val |= RZG3L_PLL_STBY_RESETB;
+		mon_val = mon_mask;
 	}
 
 	writel(val, priv->base + stby_offset);
 
 	/* ensure PLL is in normal/standby mode */
-	ret = readl_poll_timeout_atomic(priv->base + mon_offset, val, mon_val ==
-					(val & (RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK)),
-					10, 100);
+	ret = readl_poll_timeout_atomic(priv->base + mon_offset, val,
+					mon_val == (val & mon_mask), 10, 100);
 	if (ret)
 		dev_err(priv->dev, "Failed to %s PLL 0x%x/%pC\n", enable ?
 			"enable" : "disable", stby_offset, hw->clk);
-- 
2.43.0

RE: [PATCH 2/3] clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable()

[Biju Das]

Hi Geert,

Thanks for the patch.

> -----Original Message-----
> From: Geert Uytterhoeven <geert+renesas@glider.be>
> Sent: 30 April 2026 16:20
> Subject: [PATCH 2/3] clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable()
> 
> Reduce duplication by introducing mon_mask.
> Eliminate an else branch by moving common parts into variable pre-initializations.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Cheers,
Biju

> ---
> No change in generated code.
> ---
>  drivers/clk/renesas/rzg2l-cpg.c | 16 +++++++---------
>  1 file changed, 7 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index
> f98b6eb4f501c676..426e93dc7a9891bf 100644
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -1197,27 +1197,25 @@ static int rzg3l_cpg_pll_clk_endisable(struct clk_hw *hw, bool enable)  {
>  	struct pll_clk *pll_clk = to_pll(hw);
>  	struct rzg2l_cpg_priv *priv = pll_clk->priv;
> +	u32 mon_mask = RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK;
> +	u32 val = RZG3L_PLL_STBY_RESETB_WEN;
>  	u32 stby_offset, mon_offset;
> -	u32 val, mon_val;
> +	u32 mon_val = 0;
>  	int ret;
> 
>  	stby_offset = RZG3L_PLL_STBY_OFFSET(pll_clk->conf);
>  	mon_offset = RZG3L_PLL_MON_OFFSET(pll_clk->conf);
> 
>  	if (enable) {
> -		val = RZG3L_PLL_STBY_RESETB_WEN | RZG3L_PLL_STBY_RESETB;
> -		mon_val = RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK;
> -	} else {
> -		val = RZG3L_PLL_STBY_RESETB_WEN;
> -		mon_val = 0;
> +		val |= RZG3L_PLL_STBY_RESETB;
> +		mon_val = mon_mask;
>  	}
> 
>  	writel(val, priv->base + stby_offset);
> 
>  	/* ensure PLL is in normal/standby mode */
> -	ret = readl_poll_timeout_atomic(priv->base + mon_offset, val, mon_val ==
> -					(val & (RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK)),
> -					10, 100);
> +	ret = readl_poll_timeout_atomic(priv->base + mon_offset, val,
> +					mon_val == (val & mon_mask), 10, 100);
>  	if (ret)
>  		dev_err(priv->dev, "Failed to %s PLL 0x%x/%pC\n", enable ?
>  			"enable" : "disable", stby_offset, hw->clk);
> --
> 2.43.0