* [PATCH v3 2/5] dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern
2026-06-03 15:12 [PATCH v3 0/5] clock: versal-clk: Fix Versal NET clock binding and switch to CCF Michal Simek
@ 2026-06-03 15:12 ` Michal Simek
2026-06-03 15:33 ` Conor Dooley
2026-06-03 15:12 ` [PATCH v3 3/5] dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema Michal Simek
2026-06-03 15:12 ` [PATCH v3 4/5] dt-bindings: clock: versal-clk: Fix Versal NET clock validation Michal Simek
2 siblings, 1 reply; 8+ messages in thread
From: Michal Simek @ 2026-06-03 15:12 UTC (permalink / raw)
To: linux-kernel, monstr, michal.simek, git
Cc: Conor Dooley, Krzysztof Kozlowski, Michael Turquette, Rob Herring,
Shubhrajyoti Datta, Stephen Boyd,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:COMMON CLK FRAMEWORK
The clock-names pattern "^mio_clk[00-77]+.*$" was intended to constrain
the MIO index to the valid range 00..77 (ZynqMP has 78 MIO pins),
but a regex character class cannot express a multi-digit decimal range.
Replace the bogus character class with an explicit alternation that
enumerates the two-digit decimal values 00..77.
Fixes: 03d4a1004053 ("dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml")
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
Changes in v3:
- New patch in series
Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
index bef109d163a8..d843d95801b5 100644
--- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
@@ -116,7 +116,7 @@ allOf:
- const: pss_alt_ref_clk
- const: aux_ref_clk
- const: gt_crx_ref_clk
- - pattern: "^mio_clk[00-77]+.*$"
+ - pattern: "^mio_clk(0[0-9]|[1-6][0-9]|7[0-7])+.*$"
- pattern: "gem[0-3]+_emio_clk.*$"
- pattern: "swdt[0-1]+_ext_clk.*$"
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v3 3/5] dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema
2026-06-03 15:12 [PATCH v3 0/5] clock: versal-clk: Fix Versal NET clock binding and switch to CCF Michal Simek
2026-06-03 15:12 ` [PATCH v3 2/5] dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern Michal Simek
@ 2026-06-03 15:12 ` Michal Simek
2026-06-03 15:34 ` Conor Dooley
2026-06-03 15:12 ` [PATCH v3 4/5] dt-bindings: clock: versal-clk: Fix Versal NET clock validation Michal Simek
2 siblings, 1 reply; 8+ messages in thread
From: Michal Simek @ 2026-06-03 15:12 UTC (permalink / raw)
To: linux-kernel, monstr, michal.simek, git
Cc: Rob Herring, Conor Dooley, Krzysztof Kozlowski, Michael Turquette,
Stephen Boyd,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
kishore Manne, moderated list:ARM/ZYNQ ARCHITECTURE,
open list:COMMON CLK FRAMEWORK
The ZynqMP clock controller binding shares only #clock-cells with the
Versal bindings. Move it to a dedicated xlnx,zynqmp-clk.yaml schema.
Also remove "(Optional clock)" from clock description because it is visible
from schema itself.
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
Changes in v3:
- Cover change in zynqmp-firmware.yaml
- Move clock-cells to be the last in the example
- Remove comment around (Optional clock) which is obvious from schema
itself
Changes in v2:
- New patch in series
- Split zynqmp-clk from versal-clk
.../bindings/clock/xlnx,versal-clk.yaml | 50 +-------------
.../bindings/clock/xlnx,zynqmp-clk.yaml | 68 +++++++++++++++++++
.../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 7 +-
3 files changed, 76 insertions(+), 49 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml
diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
index d843d95801b5..12d060c39bfc 100644
--- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
@@ -17,9 +17,7 @@ description: |
properties:
compatible:
oneOf:
- - enum:
- - xlnx,versal-clk
- - xlnx,zynqmp-clk
+ - const: xlnx,versal-clk
- items:
- enum:
- xlnx,versal-net-clk
@@ -32,11 +30,11 @@ properties:
description: List of clock specifiers which are external input
clocks to the given clock controller.
minItems: 2
- maxItems: 8
+ maxItems: 3
clock-names:
minItems: 2
- maxItems: 8
+ maxItems: 3
required:
- compatible
@@ -87,39 +85,6 @@ allOf:
- const: pl_alt_ref
- const: alt_ref
- - if:
- properties:
- compatible:
- contains:
- enum:
- - xlnx,zynqmp-clk
-
- then:
- properties:
- clocks:
- minItems: 5
- items:
- - description: PS reference clock
- - description: reference clock for video system
- - description: alternative PS reference clock
- - description: auxiliary reference clock
- - description: transceiver reference clock
- - description: (E)MIO clock source (Optional clock)
- - description: GEM emio clock (Optional clock)
- - description: Watchdog external clock (Optional clock)
-
- clock-names:
- minItems: 5
- items:
- - const: pss_ref_clk
- - const: video_clk
- - const: pss_alt_ref_clk
- - const: aux_ref_clk
- - const: gt_crx_ref_clk
- - pattern: "^mio_clk(0[0-9]|[1-6][0-9]|7[0-7])+.*$"
- - pattern: "gem[0-3]+_emio_clk.*$"
- - pattern: "swdt[0-1]+_ext_clk.*$"
-
examples:
- |
firmware {
@@ -134,13 +99,4 @@ examples:
};
};
};
-
- clock-controller {
- #clock-cells = <1>;
- compatible = "xlnx,zynqmp-clk";
- clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
- <&aux_ref_clk>, <>_crx_ref_clk>;
- clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
- "aux_ref_clk", "gt_crx_ref_clk";
- };
...
diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml
new file mode 100644
index 000000000000..ccea3184b041
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/xlnx,zynqmp-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx ZynqMP clock controller
+
+maintainers:
+ - Michal Simek <michal.simek@amd.com>
+
+description:
+ The clock controller is a hardware block of Xilinx ZynqMP clock tree. It
+ reads required input clock frequencies from the devicetree and acts as clock
+ provider for all clock consumers of PS clocks.
+
+properties:
+ compatible:
+ const: xlnx,zynqmp-clk
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ description: List of clock specifiers which are external input
+ clocks to the given clock controller.
+ minItems: 5
+ items:
+ - description: PS reference clock
+ - description: reference clock for video system
+ - description: alternative PS reference clock
+ - description: auxiliary reference clock
+ - description: transceiver reference clock
+ - description: (E)MIO clock source
+ - description: GEM emio clock
+ - description: Watchdog external clock
+
+ clock-names:
+ minItems: 5
+ items:
+ - const: pss_ref_clk
+ - const: video_clk
+ - const: pss_alt_ref_clk
+ - const: aux_ref_clk
+ - const: gt_crx_ref_clk
+ - pattern: "^mio_clk(0[0-9]|[1-6][0-9]|7[0-7])+.*$"
+ - pattern: "gem[0-3]+_emio_clk.*$"
+ - pattern: "swdt[0-1]+_ext_clk.*$"
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller {
+ compatible = "xlnx,zynqmp-clk";
+ clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
+ <&aux_ref_clk>, <>_crx_ref_clk>;
+ clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
+ "aux_ref_clk", "gt_crx_ref_clk";
+ #clock-cells = <1>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
index 680082c29f01..72af37cdb103 100644
--- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
@@ -48,8 +48,7 @@ properties:
const: 1
clock-controller:
- $ref: /schemas/clock/xlnx,versal-clk.yaml#
- description: The clock controller is a hardware block of Xilinx versal
+ description: The clock controller is a hardware block of Xilinx SoC
clock tree. It reads required input clock frequencies from the devicetree
and acts as clock provider for all clock consumers of PS clocks.list of
clock specifiers which are external input clocks to the given clock
@@ -113,10 +112,14 @@ allOf:
const: xlnx,zynqmp-firmware
then:
properties:
+ clock-controller:
+ $ref: /schemas/clock/xlnx,zynqmp-clk.yaml#
pinctrl:
$ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
else:
properties:
+ clock-controller:
+ $ref: /schemas/clock/xlnx,versal-clk.yaml#
pinctrl:
$ref: /schemas/pinctrl/xlnx,versal-pinctrl.yaml#
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v3 4/5] dt-bindings: clock: versal-clk: Fix Versal NET clock validation
2026-06-03 15:12 [PATCH v3 0/5] clock: versal-clk: Fix Versal NET clock binding and switch to CCF Michal Simek
2026-06-03 15:12 ` [PATCH v3 2/5] dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern Michal Simek
2026-06-03 15:12 ` [PATCH v3 3/5] dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema Michal Simek
@ 2026-06-03 15:12 ` Michal Simek
2 siblings, 0 replies; 8+ messages in thread
From: Michal Simek @ 2026-06-03 15:12 UTC (permalink / raw)
To: linux-kernel, monstr, michal.simek, git
Cc: Conor Dooley, Conor Dooley, Krzysztof Kozlowski,
Michael Turquette, Rob Herring, Shubhrajyoti Datta, Stephen Boyd,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:COMMON CLK FRAMEWORK
The Versal NET clock controller compatible is specified as:
compatible = "xlnx,versal-net-clk", "xlnx,versal-clk";
with xlnx,versal-clk listed as fallback. The original binding had
two separate if/then blocks - one matching xlnx,versal-clk (2 clocks)
and another matching xlnx,versal-net-clk (3 clocks). Since both
compatible strings are present, both conditions matched simultaneously
and JSON Schema applied the more restrictive 2-clock constraint,
causing false "too long" validation errors for Versal NET.
Define clock-names at the top-level and use if/then only to constrain
the clock count (2 for Versal, 3 for Versal NET). Add a dedicated
example for the Versal NET 3-clock configuration.
Fixes: 39118392d19a ("dt-bindings: Remove alt_ref from versal")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes in v3:
- Move clock-cells to be the last property in the example
- use 2 spaces for indentation in example to follow the same style which is
already used
- Add fixed tag
Changes in v2:
- Update logic without ZynqMP part in this file and have if/else only
around min/maxItems
.../bindings/clock/xlnx,versal-clk.yaml | 51 ++++++++-----------
1 file changed, 22 insertions(+), 29 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
index 12d060c39bfc..b533ffd082fd 100644
--- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
@@ -30,11 +30,17 @@ properties:
description: List of clock specifiers which are external input
clocks to the given clock controller.
minItems: 2
- maxItems: 3
+ items:
+ - description: reference clock
+ - description: alternate reference clock for programmable logic
+ - description: alternate reference clock
clock-names:
minItems: 2
- maxItems: 3
+ items:
+ - const: ref
+ - const: pl_alt_ref
+ - const: alt_ref
required:
- compatible
@@ -50,40 +56,19 @@ allOf:
compatible:
contains:
enum:
- - xlnx,versal-clk
-
+ - xlnx,versal-net-clk
then:
properties:
clocks:
- items:
- - description: reference clock
- - description: alternate reference clock for programmable logic
-
+ minItems: 3
clock-names:
- items:
- - const: ref
- - const: pl_alt_ref
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - xlnx,versal-net-clk
-
- then:
+ minItems: 3
+ else:
properties:
clocks:
- items:
- - description: reference clock
- - description: alternate reference clock for programmable logic
- - description: alternate reference clock
-
+ maxItems: 2
clock-names:
- items:
- - const: ref
- - const: pl_alt_ref
- - const: alt_ref
+ maxItems: 2
examples:
- |
@@ -99,4 +84,12 @@ examples:
};
};
};
+
+ - |
+ clock-controller {
+ compatible = "xlnx,versal-net-clk", "xlnx,versal-clk";
+ clocks = <&ref>, <&pl_alt_ref>, <&alt_ref>;
+ clock-names = "ref", "pl_alt_ref", "alt_ref";
+ #clock-cells = <1>;
+ };
...
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread