Re: [PATCH v3 0/6] Add SPI4 support for IPQ5424

[Manikanta Mylavarapu <quic_mmanikan@quicinc.com>]

On 12/30/2024 9:06 PM, Konrad Dybcio wrote:
> On 30.12.2024 4:34 PM, Kathiravan Thirumoorthy wrote:
>>
>>
>> On 12/30/2024 7:28 PM, Konrad Dybcio wrote:
>>> On 30.12.2024 2:54 PM, Konrad Dybcio wrote:
>>>> On 30.12.2024 7:51 AM, Kathiravan Thirumoorthy wrote:
>>>>>
>>>>>
>>>>> On 12/27/2024 12:54 PM, Manikanta Mylavarapu wrote:
>>>>>> Add SPI4 node to the IPQ5424 device tree and update the relevant
>>>>>> bindings, GPIO pin mappings accordingly.
>>>>>>
>>>>>> Changes in V3:
>>>>>>      - Rename SPI0 to SPI4 because SPI protocol runs on serial engine 4
>>>>>
>>>>> Do we really need to do this? If so, it will not align with the HW documentation and will lead to the confusion down the line. IMHO, we should stick with the convention followed in the HW documentation.
>>>>
>>>> +1, the clocks are called SPI0/SPI1 internally
>>>
>>> Ok, I looked at a bit more documentation and it looks like
>>> somebody just had fun naming things..
>>>
>>> SPI0 is on SE4 and SPI1 is on something else, with no more
>>> clock provisions for that protocol.. Which is not usually the
>>> case.
>>
>>
>> IPQ5424 has one QUPV3 instance with 6 SEs. SE0-SE4 are Mini core and SE5 is FW core.
>>
>> SE0 and SE1 are for 4-wire UART and 2-wire UART respectively. SE2 and SE3 are for I2C protocol. SE4 is for SPI.
>>
>> Since SE5 is FW based (some RDPs use this SE for I2C). In GCC block, clocks for this instance is named after SPI as SPI1.
> 
> Thanks for the explanation.
> 
> Manikanta, please refer to this in the commit message as well
> 


Thank you, Konrad and Kathiravan, for your valuable insights.
I will incorporate the aforementioned information into the commit message, revert the 'renaming spi0 to spi4',
and include both spi0 and spi1 in the next version.

Thanks & Regards,
Manikanta.