* [PATCH v9 01/23] dt-bindings: clock: imx8mm: add VIDEO_PLL clocks
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
@ 2025-01-18 12:39 ` Dario Binacchi
2025-01-18 12:39 ` [PATCH v9 02/23] clk: imx8mm: rename video_pll1 to video_pll Dario Binacchi
` (15 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:39 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Krzysztof Kozlowski, Abel Vesa,
Conor Dooley, Fabio Estevam, Krzysztof Kozlowski,
Michael Turquette, Peng Fan, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree, imx,
linux-arm-kernel, linux-clk
Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's add the IMX8MM_VIDEO_PLL[_*]
definitions to be consistent with the RM and avoid misunderstandings.
The IMX8MM_VIDEO_PLL1* constants have not been removed to ensure
backward compatibility of the patch.
No functional changes intended.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
(no changes since v6)
Changes in v6:
- Add 'Acked-by' tag of Krzysztof Kozlowski
Changes in v5:
- New
include/dt-bindings/clock/imx8mm-clock.h | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
index 1f768b2eeb1a..102d8a6cdb55 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -16,7 +16,8 @@
#define IMX8MM_CLK_EXT4 7
#define IMX8MM_AUDIO_PLL1_REF_SEL 8
#define IMX8MM_AUDIO_PLL2_REF_SEL 9
-#define IMX8MM_VIDEO_PLL1_REF_SEL 10
+#define IMX8MM_VIDEO_PLL_REF_SEL 10
+#define IMX8MM_VIDEO_PLL1_REF_SEL IMX8MM_VIDEO_PLL_REF_SEL
#define IMX8MM_DRAM_PLL_REF_SEL 11
#define IMX8MM_GPU_PLL_REF_SEL 12
#define IMX8MM_VPU_PLL_REF_SEL 13
@@ -26,7 +27,8 @@
#define IMX8MM_SYS_PLL3_REF_SEL 17
#define IMX8MM_AUDIO_PLL1 18
#define IMX8MM_AUDIO_PLL2 19
-#define IMX8MM_VIDEO_PLL1 20
+#define IMX8MM_VIDEO_PLL 20
+#define IMX8MM_VIDEO_PLL1 IMX8MM_VIDEO_PLL
#define IMX8MM_DRAM_PLL 21
#define IMX8MM_GPU_PLL 22
#define IMX8MM_VPU_PLL 23
@@ -36,7 +38,8 @@
#define IMX8MM_SYS_PLL3 27
#define IMX8MM_AUDIO_PLL1_BYPASS 28
#define IMX8MM_AUDIO_PLL2_BYPASS 29
-#define IMX8MM_VIDEO_PLL1_BYPASS 30
+#define IMX8MM_VIDEO_PLL_BYPASS 30
+#define IMX8MM_VIDEO_PLL1_BYPASS IMX8MM_VIDEO_PLL_BYPASS
#define IMX8MM_DRAM_PLL_BYPASS 31
#define IMX8MM_GPU_PLL_BYPASS 32
#define IMX8MM_VPU_PLL_BYPASS 33
@@ -46,7 +49,8 @@
#define IMX8MM_SYS_PLL3_BYPASS 37
#define IMX8MM_AUDIO_PLL1_OUT 38
#define IMX8MM_AUDIO_PLL2_OUT 39
-#define IMX8MM_VIDEO_PLL1_OUT 40
+#define IMX8MM_VIDEO_PLL_OUT 40
+#define IMX8MM_VIDEO_PLL1_OUT IMX8MM_VIDEO_PLL_OUT
#define IMX8MM_DRAM_PLL_OUT 41
#define IMX8MM_GPU_PLL_OUT 42
#define IMX8MM_VPU_PLL_OUT 43
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 02/23] clk: imx8mm: rename video_pll1 to video_pll
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
2025-01-18 12:39 ` [PATCH v9 01/23] dt-bindings: clock: imx8mm: add VIDEO_PLL clocks Dario Binacchi
@ 2025-01-18 12:39 ` Dario Binacchi
2025-01-18 12:39 ` [PATCH v9 03/23] dt-bindings: clock: imx8mp: add VIDEO_PLL clocks Dario Binacchi
` (14 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:39 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Peng Fan, Abel Vesa, Fabio Estevam,
Michael Turquette, Pengutronix Kernel Team, Sascha Hauer,
Shawn Guo, Stephen Boyd, imx, linux-arm-kernel, linux-clk
Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's rename "video_pll1" to
"video_pll" to be consistent with the RM and avoid misunderstandings.
No functional changes intended.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
The patch, which simply replaces video_pll1 with video_pll, highlights
many warnings raised by checkpatch.pl. These are not generated by the
changes made but are inherited from how the module was originally
written. Fixing them would have meant "obscuring" the actual changes
introduced.
(no changes since v7)
Changes in v7:
- Add 'Reviewed-by' tag of Peng Fan
Changes in v5:
- Split the patch dropping the dt-bindings changes.
Changes in v4:
- New
drivers/clk/imx/clk-imx8mm.c | 102 +++++++++++++++++------------------
1 file changed, 51 insertions(+), 51 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 342049b847b9..8a1fc7e17ba2 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -28,7 +28,7 @@ static u32 share_count_nand;
static const char *pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
-static const char *video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
+static const char *video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
@@ -42,22 +42,22 @@ static const char *imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m
static const char * const imx8mm_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
static const char *imx8mm_m4_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "sys_pll1_266m",
- "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
+ "sys_pll1_800m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", };
static const char *imx8mm_vpu_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
"sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "vpu_pll_out", };
static const char *imx8mm_gpu3d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out",
- "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+ "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
static const char *imx8mm_gpu2d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out",
- "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+ "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
static const char *imx8mm_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", "sys_pll2_250m",
- "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "sys_pll1_100m",};
+ "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "sys_pll1_100m",};
static const char *imx8mm_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
- "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
+ "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", };
static const char *imx8mm_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
"sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
@@ -72,28 +72,28 @@ static const char *imx8mm_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pl
"sys_pll1_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", };
static const char *imx8mm_disp_rtrm_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll2_1000m",
- "audio_pll1_out", "video_pll1_out", "clk_ext2", "clk_ext3", };
+ "audio_pll1_out", "video_pll_out", "clk_ext2", "clk_ext3", };
static const char *imx8mm_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m",
"sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
static const char *imx8mm_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m",
- "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+ "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
static const char *imx8mm_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m",
- "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+ "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
static const char *imx8mm_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m",
- "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+ "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
static const char *imx8mm_noc_apb_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll3_out", "sys_pll2_333m", "sys_pll2_200m",
- "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", };
+ "sys_pll1_800m", "audio_pll1_out", "video_pll_out", };
static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
- "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
+ "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", };
static const char *imx8mm_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_1000m",
- "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
+ "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", };
static const char *imx8mm_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m", "sys_pll2_500m",
"sys_pll2_1000m", "sys_pll3_out", "audio_pll1_out", "sys_pll1_266m", };
@@ -108,10 +108,10 @@ static const char *imx8mm_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_8
"sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", };
static const char *imx8mm_disp_dtrc_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m",
- "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", };
+ "sys_pll1_160m", "video_pll_out", "sys_pll3_out", "audio_pll2_out", };
static const char *imx8mm_disp_dc8000_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m",
- "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", };
+ "sys_pll1_160m", "video_pll_out", "sys_pll3_out", "audio_pll2_out", };
static const char *imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
"sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", };
@@ -122,47 +122,47 @@ static const char *imx8mm_pcie1_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_p
static const char *imx8mm_pcie1_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out",
"sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", };
-static const char *imx8mm_dc_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out",
+static const char *imx8mm_dc_pixel_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out", "audio_pll1_out",
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
-static const char *imx8mm_lcdif_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out",
+static const char *imx8mm_lcdif_pixel_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out", "audio_pll1_out",
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
-static const char *imx8mm_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", };
-static const char *imx8mm_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", };
-static const char *imx8mm_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", };
-static const char *imx8mm_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", };
-static const char *imx8mm_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", };
-static const char *imx8mm_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", };
-static const char *imx8mm_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", };
-static const char *imx8mm_spdif2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_spdif2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", };
static const char *imx8mm_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
- "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
+ "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", };
static const char *imx8mm_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4", "video_pll1_out", };
+ "clk_ext3", "clk_ext4", "video_pll_out", };
static const char *imx8mm_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
- "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
+ "sys_pll2_500m", "video_pll_out", "audio_pll2_out", };
static const char *imx8mm_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m",
- "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll1_out", };
+ "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll_out", };
static const char *imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
"audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
@@ -174,16 +174,16 @@ static const char *imx8mm_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1
"sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
static const char *imx8mm_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+ "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
static const char *imx8mm_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+ "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
static const char *imx8mm_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+ "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
static const char *imx8mm_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+ "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
static const char *imx8mm_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m",
"sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
@@ -213,19 +213,19 @@ static const char *imx8mm_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1
"sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
static const char *imx8mm_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
- "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", };
static const char *imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
- "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", };
static const char *imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
- "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", };
static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
- "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", };
static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m",
- "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" };
+ "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" };
static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
"sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
@@ -234,31 +234,31 @@ static const char *imx8mm_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_ou
"sys_pll1_266m", "sys_pll2_500m", "sys_pll1_100m", };
static const char *imx8mm_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m",
- "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", };
+ "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_out", };
static const char *imx8mm_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m", "sys_pll1_800m",
- "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
+ "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out", };
static const char *imx8mm_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m", "sys_pll1_800m",
- "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", };
+ "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_out", };
static const char *imx8mm_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
"sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
static const char *imx8mm_csi1_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m",
- "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", };
+ "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_out", };
static const char *imx8mm_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m",
- "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
+ "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out", };
static const char *imx8mm_csi1_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m",
"sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", };
static const char *imx8mm_csi2_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m",
- "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", };
+ "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_out", };
static const char *imx8mm_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m",
- "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
+ "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out", };
static const char *imx8mm_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m",
"sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", };
@@ -286,9 +286,9 @@ static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }
static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "sys_pll1_200m",
"audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", };
static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", };
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", };
-static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
"dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
@@ -327,7 +327,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MM_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
@@ -336,7 +336,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
hws[IMX8MM_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
hws[IMX8MM_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);
- hws[IMX8MM_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll);
+ hws[IMX8MM_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", base + 0x28, &imx_1443x_pll);
hws[IMX8MM_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll);
hws[IMX8MM_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
hws[IMX8MM_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll);
@@ -348,7 +348,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
/* PLL bypass out */
hws[IMX8MM_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MM_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MM_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
+ hws[IMX8MM_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MM_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MM_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MM_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
@@ -358,7 +358,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
/* PLL out gate */
hws[IMX8MM_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
hws[IMX8MM_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
- hws[IMX8MM_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
+ hws[IMX8MM_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", base + 0x28, 13);
hws[IMX8MM_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
hws[IMX8MM_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
hws[IMX8MM_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 03/23] dt-bindings: clock: imx8mp: add VIDEO_PLL clocks
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
2025-01-18 12:39 ` [PATCH v9 01/23] dt-bindings: clock: imx8mm: add VIDEO_PLL clocks Dario Binacchi
2025-01-18 12:39 ` [PATCH v9 02/23] clk: imx8mm: rename video_pll1 to video_pll Dario Binacchi
@ 2025-01-18 12:39 ` Dario Binacchi
2025-01-18 12:39 ` [PATCH v9 04/23] clk: imx8mp: rename video_pll1 to video_pll Dario Binacchi
` (13 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:39 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Krzysztof Kozlowski, Abel Vesa,
Conor Dooley, Fabio Estevam, Krzysztof Kozlowski,
Michael Turquette, Peng Fan, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree, imx,
linux-arm-kernel, linux-clk
Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's add the IMX8MP_VIDEO_PLL[_*]
definitions to be consistent with the RM and avoid misunderstandings.
The IMX8MP_VIDEO_PLL1* constants have not been removed to ensure
backward compatibility of the patch.
No functional changes intended.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
(no changes since v6)
Changes in v6:
- Add 'Acked-by' tag of Krzysztof Kozlowski
Changes in v5:
- New
include/dt-bindings/clock/imx8mp-clock.h | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index 7da4243984b2..3235d7de3b62 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -16,7 +16,8 @@
#define IMX8MP_CLK_EXT4 7
#define IMX8MP_AUDIO_PLL1_REF_SEL 8
#define IMX8MP_AUDIO_PLL2_REF_SEL 9
-#define IMX8MP_VIDEO_PLL1_REF_SEL 10
+#define IMX8MP_VIDEO_PLL_REF_SEL 10
+#define IMX8MP_VIDEO_PLL1_REF_SEL IMX8MP_VIDEO_PLL_REF_SEL
#define IMX8MP_DRAM_PLL_REF_SEL 11
#define IMX8MP_GPU_PLL_REF_SEL 12
#define IMX8MP_VPU_PLL_REF_SEL 13
@@ -26,7 +27,8 @@
#define IMX8MP_SYS_PLL3_REF_SEL 17
#define IMX8MP_AUDIO_PLL1 18
#define IMX8MP_AUDIO_PLL2 19
-#define IMX8MP_VIDEO_PLL1 20
+#define IMX8MP_VIDEO_PLL 20
+#define IMX8MP_VIDEO_PLL1 IMX8MP_VIDEO_PLL
#define IMX8MP_DRAM_PLL 21
#define IMX8MP_GPU_PLL 22
#define IMX8MP_VPU_PLL 23
@@ -36,7 +38,8 @@
#define IMX8MP_SYS_PLL3 27
#define IMX8MP_AUDIO_PLL1_BYPASS 28
#define IMX8MP_AUDIO_PLL2_BYPASS 29
-#define IMX8MP_VIDEO_PLL1_BYPASS 30
+#define IMX8MP_VIDEO_PLL_BYPASS 30
+#define IMX8MP_VIDEO_PLL1_BYPASS IMX8MP_VIDEO_PLL_BYPASS
#define IMX8MP_DRAM_PLL_BYPASS 31
#define IMX8MP_GPU_PLL_BYPASS 32
#define IMX8MP_VPU_PLL_BYPASS 33
@@ -46,7 +49,8 @@
#define IMX8MP_SYS_PLL3_BYPASS 37
#define IMX8MP_AUDIO_PLL1_OUT 38
#define IMX8MP_AUDIO_PLL2_OUT 39
-#define IMX8MP_VIDEO_PLL1_OUT 40
+#define IMX8MP_VIDEO_PLL_OUT 40
+#define IMX8MP_VIDEO_PLL1_OUT IMX8MP_VIDEO_PLL_OUT
#define IMX8MP_DRAM_PLL_OUT 41
#define IMX8MP_GPU_PLL_OUT 42
#define IMX8MP_VPU_PLL_OUT 43
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 04/23] clk: imx8mp: rename video_pll1 to video_pll
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
` (2 preceding siblings ...)
2025-01-18 12:39 ` [PATCH v9 03/23] dt-bindings: clock: imx8mp: add VIDEO_PLL clocks Dario Binacchi
@ 2025-01-18 12:39 ` Dario Binacchi
2025-01-18 12:39 ` [PATCH v9 05/23] dt-bindings: clock: imx8m-anatop: add oscillators and PLLs Dario Binacchi
` (12 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:39 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Peng Fan, Abel Vesa, Fabio Estevam,
Michael Turquette, Pengutronix Kernel Team, Sascha Hauer,
Shawn Guo, Stephen Boyd, imx, linux-arm-kernel, linux-clk
Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's rename "video_pll1" to
"video_pll" to be consistent with the RM and avoid misunderstandings.
No functional changes intended.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
The patch, which simply replaces video_pll1 with video_pll, highlights
many warnings raised by checkpatch.pl. These are not generated by the
changes made but are inherited from how the module was originally
written. Fixing them would have meant "obscuring" the actual changes
introduced.
(no changes since v7)
Changes in v7:
- Add 'Reviewed-by' tag of Peng Fan
Changes in v5:
- Split the patch dropping the dt-bindings changes.
Changes in v4:
- New
drivers/clk/imx/clk-imx8mp.c | 118 +++++++++++++++++------------------
1 file changed, 59 insertions(+), 59 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 516dbd170c8a..e96460534e7d 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -23,7 +23,7 @@ static u32 share_count_audio;
static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
-static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
+static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
@@ -40,27 +40,27 @@ static const char * const imx8mp_a53_core_sels[] = {"arm_a53_div", "arm_pll_out"
static const char * const imx8mp_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m",
"vpu_pll_out", "sys_pll1_800m", "audio_pll1_out",
- "video_pll1_out", "sys_pll3_out", };
+ "video_pll_out", "sys_pll3_out", };
static const char * const imx8mp_ml_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_gpu3d_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_gpu3d_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_gpu2d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_audio_axi_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_hsio_axi_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
@@ -72,11 +72,11 @@ static const char * const imx8mp_media_isp_sels[] = {"osc_24m", "sys_pll2_1000m"
static const char * const imx8mp_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "sys_pll1_100m",};
+ "video_pll_out", "sys_pll1_100m",};
static const char * const imx8mp_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
- "video_pll1_out", "sys_pll3_out", };
+ "video_pll_out", "sys_pll3_out", };
static const char * const imx8mp_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
@@ -96,35 +96,35 @@ static const char * const imx8mp_media_apb_sels[] = {"osc_24m", "sys_pll2_125m",
static const char * const imx8mp_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_noc_io_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_ml_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_ml_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
"sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
- "audio_pll1_out", "video_pll1_out", };
+ "audio_pll1_out", "video_pll_out", };
static const char * const imx8mp_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
"sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out",
- "audio_pll1_out", "video_pll1_out", };
+ "audio_pll1_out", "video_pll_out", };
static const char * const imx8mp_mipi_dsi_esc_rx_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
"sys_pll1_800m", "sys_pll2_1000m",
@@ -159,56 +159,56 @@ static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m",
"sys_pll1_160m", "sys_pll1_200m", };
static const char * const imx8mp_i2c5_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char * const imx8mp_i2c6_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char * const imx8mp_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
+ "video_pll_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext1", "clk_ext2", };
static const char * const imx8mp_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
+ "video_pll_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext2", "clk_ext3", };
static const char * const imx8mp_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
+ "video_pll_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext3", "clk_ext4", };
static const char * const imx8mp_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
+ "video_pll_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext2", "clk_ext3", };
static const char * const imx8mp_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
+ "video_pll_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext3", "clk_ext4", };
static const char * const imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
- "video_pll1_out", "clk_ext4", };
+ "video_pll_out", "clk_ext4", };
static const char * const imx8mp_enet_qos_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
"clk_ext1", "clk_ext2", "clk_ext3",
- "clk_ext4", "video_pll1_out", };
+ "clk_ext4", "video_pll_out", };
static const char * const imx8mp_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
- "video_pll1_out", "clk_ext4", };
+ "video_pll_out", "clk_ext4", };
static const char * const imx8mp_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
"clk_ext1", "clk_ext2", "clk_ext3",
- "clk_ext4", "video_pll1_out", };
+ "clk_ext4", "video_pll_out", };
static const char * const imx8mp_enet_phy_ref_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
"sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
- "sys_pll2_250m", "video_pll1_out", };
+ "sys_pll2_250m", "video_pll_out", };
static const char * const imx8mp_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
@@ -223,19 +223,19 @@ static const char * const imx8mp_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "s
"audio_pll2_out", "sys_pll1_100m", };
static const char * const imx8mp_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char * const imx8mp_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char * const imx8mp_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char * const imx8mp_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char * const imx8mp_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
@@ -276,42 +276,42 @@ static const char * const imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "s
static const char * const imx8mp_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
- "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll1_80m", "video_pll_out", };
static const char * const imx8mp_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
- "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll1_80m", "video_pll_out", };
static const char * const imx8mp_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
- "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll1_80m", "video_pll_out", };
static const char * const imx8mp_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
- "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll1_80m", "video_pll_out", };
static const char * const imx8mp_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext1" };
static const char * const imx8mp_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext2" };
static const char * const imx8mp_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext3" };
static const char * const imx8mp_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext1" };
static const char * const imx8mp_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext2" };
static const char * const imx8mp_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext3" };
static const char * const imx8mp_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
@@ -328,19 +328,19 @@ static const char * const imx8mp_ipp_do_clko1_sels[] = {"osc_24m", "sys_pll1_800
static const char * const imx8mp_ipp_do_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
"sys_pll1_166m", "sys_pll3_out", "audio_pll1_out",
- "video_pll1_out", "osc_32k" };
+ "video_pll_out", "osc_32k" };
static const char * const imx8mp_hdmi_fdcc_tst_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
- "audio_pll2_out", "video_pll1_out", };
+ "audio_pll2_out", "video_pll_out", };
static const char * const imx8mp_hdmi_24m_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char * const imx8mp_hdmi_ref_266m_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll3_out",
"sys_pll2_333m", "sys_pll1_266m", "sys_pll2_200m",
- "audio_pll1_out", "video_pll1_out", };
+ "audio_pll1_out", "video_pll_out", };
static const char * const imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
@@ -349,26 +349,26 @@ static const char * const imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "s
static const char * const imx8mp_media_cam1_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
"sys_pll1_800m", "sys_pll2_1000m",
"sys_pll3_out", "audio_pll2_out",
- "video_pll1_out", };
+ "video_pll_out", };
static const char * const imx8mp_media_mipi_phy1_ref_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
"sys_pll1_800m", "sys_pll2_1000m",
"clk_ext2", "audio_pll2_out",
- "video_pll1_out", };
+ "video_pll_out", };
-static const char * const imx8mp_media_disp_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
+static const char * const imx8mp_media_disp_pix_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out",
"audio_pll1_out", "sys_pll1_800m",
"sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
static const char * const imx8mp_media_cam2_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
"sys_pll1_800m", "sys_pll2_1000m",
"sys_pll3_out", "audio_pll2_out",
- "video_pll1_out", };
+ "video_pll_out", };
static const char * const imx8mp_media_ldb_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
"sys_pll1_800m", "sys_pll2_1000m",
"clk_ext2", "audio_pll2_out",
- "video_pll1_out", };
+ "video_pll_out", };
static const char * const imx8mp_memrepair_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
@@ -392,12 +392,12 @@ static const char * const imx8mp_vpu_vc8000e_sels[] = {"osc_24m", "vpu_pll_out",
"sys_pll3_out", "audio_pll1_out", };
static const char * const imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
+ "video_pll_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext3", "clk_ext4", };
static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
-static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
"dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
@@ -440,7 +440,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MP_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", anatop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
@@ -451,7 +451,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", anatop_base, &imx_1443x_pll);
hws[IMX8MP_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", anatop_base + 0x14, &imx_1443x_pll);
- hws[IMX8MP_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", anatop_base + 0x28, &imx_1443x_pll);
+ hws[IMX8MP_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", anatop_base + 0x28, &imx_1443x_pll);
hws[IMX8MP_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", anatop_base + 0x50, &imx_1443x_dram_pll);
hws[IMX8MP_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", anatop_base + 0x64, &imx_1416x_pll);
hws[IMX8MP_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", anatop_base + 0x74, &imx_1416x_pll);
@@ -462,7 +462,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MP_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MP_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", anatop_base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
+ hws[IMX8MP_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", anatop_base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MP_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", anatop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MP_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", anatop_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MP_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", anatop_base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
@@ -473,7 +473,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", anatop_base, 13);
hws[IMX8MP_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", anatop_base + 0x14, 13);
- hws[IMX8MP_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", anatop_base + 0x28, 13);
+ hws[IMX8MP_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", anatop_base + 0x28, 13);
hws[IMX8MP_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", anatop_base + 0x50, 13);
hws[IMX8MP_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", anatop_base + 0x64, 11);
hws[IMX8MP_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", anatop_base + 0x74, 11);
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 05/23] dt-bindings: clock: imx8m-anatop: add oscillators and PLLs
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
` (3 preceding siblings ...)
2025-01-18 12:39 ` [PATCH v9 04/23] clk: imx8mp: rename video_pll1 to video_pll Dario Binacchi
@ 2025-01-18 12:39 ` Dario Binacchi
2025-01-18 12:39 ` [PATCH v9 10/23] clk: imx: add hw API imx_anatop_get_clk_hw Dario Binacchi
` (11 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:39 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Krzysztof Kozlowski, Abel Vesa,
Conor Dooley, Fabio Estevam, Krzysztof Kozlowski,
Michael Turquette, Peng Fan, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree, imx,
linux-arm-kernel, linux-clk
Though adding clocks and clock-names properties will break the ABI,
it is required to accurately describe the hardware. Indeed, the anatop
module uses the input oscillators to generate various PLLs. In turn,
the Clock Control Module (CCM) receives clocks from the PLLs and
oscillators and generates clocks for on-chip peripherals.
Furthermore, as agreed in [1], this change represents the first step
toward the implementation of the anatop driver. Currently, in fact,
there is no dedicated anatop driver, but the CCM driver parses the
anatop node and registers the PLLs it produces.
[1] https://lore.kernel.org/imx/20241106090549.3684963-1-dario.binacchi@amarulasolutions.com/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
(no changes since v7)
Changes in v7:
- Add 'Reviewed-by' tag of Krzysztof Kozlowski
Changes in v6:
- Improve commit message
- Merge it with patch 10, 11, and 12:
- 10/20 dt-bindings: clock: imx8mm: add binding definitions for anatop
- 11/20 dt-bindings: clock: imx8mn: add binding definitions for anatop
- 12/20 dt-bindings: clock: imx8mp: add binding definitions for anatop
Changes in v4:
- New
.../bindings/clock/fsl,imx8m-anatop.yaml | 53 ++++++++++++++-
include/dt-bindings/clock/imx8mm-clock.h | 64 +++++++++++++++++
include/dt-bindings/clock/imx8mn-clock.h | 64 +++++++++++++++++
include/dt-bindings/clock/imx8mp-clock.h | 68 +++++++++++++++++++
4 files changed, 248 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml
index bbd22e95b319..f439b0a94ce2 100644
--- a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml
+++ b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml
@@ -30,22 +30,73 @@ properties:
interrupts:
maxItems: 1
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ minItems: 2
+ maxItems: 3
+
'#clock-cells':
const: 1
required:
- compatible
- reg
+ - clocks
+ - clock-names
- '#clock-cells'
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8mq-anatop
+ then:
+ properties:
+ clocks:
+ items:
+ - description: 32k osc
+ - description: 25m osc
+ - description: 27m osc
+ clock-names:
+ items:
+ - const: ckil
+ - const: osc_25m
+ - const: osc_27m
+ else:
+ properties:
+ clocks:
+ items:
+ - description: 32k osc
+ - description: 24m osc
+
+ clock-names:
+ items:
+ - const: osc_32k
+ - const: osc_24m
+
additionalProperties: false
examples:
- |
- anatop: clock-controller@30360000 {
+ clock-controller@30360000 {
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
#clock-cells = <1>;
+ clocks = <&osc_32k>, <&osc_24m>;
+ clock-names = "osc_32k", "osc_24m";
+ };
+
+ - |
+ clock-controller@30360000 {
+ compatible = "fsl,imx8mq-anatop";
+ reg = <0x30360000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc_25m>, <&osc_27m>;
+ clock-names = "ckil", "osc_25m", "osc_27m";
};
...
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
index 102d8a6cdb55..017c06e48430 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -287,4 +287,68 @@
#define IMX8MM_CLK_END 258
+#define IMX8MM_ANATOP_CLK_DUMMY 0
+#define IMX8MM_ANATOP_CLK_32K 1
+#define IMX8MM_ANATOP_CLK_24M 2
+#define IMX8MM_ANATOP_AUDIO_PLL1_REF_SEL 3
+#define IMX8MM_ANATOP_AUDIO_PLL2_REF_SEL 4
+#define IMX8MM_ANATOP_VIDEO_PLL_REF_SEL 5
+#define IMX8MM_ANATOP_DRAM_PLL_REF_SEL 6
+#define IMX8MM_ANATOP_GPU_PLL_REF_SEL 7
+#define IMX8MM_ANATOP_VPU_PLL_REF_SEL 8
+#define IMX8MM_ANATOP_ARM_PLL_REF_SEL 9
+#define IMX8MM_ANATOP_SYS_PLL3_REF_SEL 10
+#define IMX8MM_ANATOP_AUDIO_PLL1 11
+#define IMX8MM_ANATOP_AUDIO_PLL2 12
+#define IMX8MM_ANATOP_VIDEO_PLL 13
+#define IMX8MM_ANATOP_DRAM_PLL 14
+#define IMX8MM_ANATOP_GPU_PLL 15
+#define IMX8MM_ANATOP_VPU_PLL 16
+#define IMX8MM_ANATOP_ARM_PLL 17
+#define IMX8MM_ANATOP_SYS_PLL1 18
+#define IMX8MM_ANATOP_SYS_PLL2 19
+#define IMX8MM_ANATOP_SYS_PLL3 20
+#define IMX8MM_ANATOP_AUDIO_PLL1_BYPASS 21
+#define IMX8MM_ANATOP_AUDIO_PLL2_BYPASS 22
+#define IMX8MM_ANATOP_VIDEO_PLL_BYPASS 23
+#define IMX8MM_ANATOP_DRAM_PLL_BYPASS 24
+#define IMX8MM_ANATOP_GPU_PLL_BYPASS 25
+#define IMX8MM_ANATOP_VPU_PLL_BYPASS 26
+#define IMX8MM_ANATOP_ARM_PLL_BYPASS 27
+#define IMX8MM_ANATOP_SYS_PLL3_BYPASS 28
+#define IMX8MM_ANATOP_AUDIO_PLL1_OUT 29
+#define IMX8MM_ANATOP_AUDIO_PLL2_OUT 30
+#define IMX8MM_ANATOP_VIDEO_PLL_OUT 31
+#define IMX8MM_ANATOP_DRAM_PLL_OUT 32
+#define IMX8MM_ANATOP_GPU_PLL_OUT 33
+#define IMX8MM_ANATOP_VPU_PLL_OUT 34
+#define IMX8MM_ANATOP_ARM_PLL_OUT 35
+#define IMX8MM_ANATOP_SYS_PLL3_OUT 36
+#define IMX8MM_ANATOP_SYS_PLL1_OUT 37
+#define IMX8MM_ANATOP_SYS_PLL1_40M 38
+#define IMX8MM_ANATOP_SYS_PLL1_80M 39
+#define IMX8MM_ANATOP_SYS_PLL1_100M 40
+#define IMX8MM_ANATOP_SYS_PLL1_133M 41
+#define IMX8MM_ANATOP_SYS_PLL1_160M 42
+#define IMX8MM_ANATOP_SYS_PLL1_200M 43
+#define IMX8MM_ANATOP_SYS_PLL1_266M 44
+#define IMX8MM_ANATOP_SYS_PLL1_400M 45
+#define IMX8MM_ANATOP_SYS_PLL1_800M 46
+#define IMX8MM_ANATOP_SYS_PLL2_OUT 47
+#define IMX8MM_ANATOP_SYS_PLL2_50M 48
+#define IMX8MM_ANATOP_SYS_PLL2_100M 49
+#define IMX8MM_ANATOP_SYS_PLL2_125M 50
+#define IMX8MM_ANATOP_SYS_PLL2_166M 51
+#define IMX8MM_ANATOP_SYS_PLL2_200M 52
+#define IMX8MM_ANATOP_SYS_PLL2_250M 53
+#define IMX8MM_ANATOP_SYS_PLL2_333M 54
+#define IMX8MM_ANATOP_SYS_PLL2_500M 55
+#define IMX8MM_ANATOP_SYS_PLL2_1000M 56
+#define IMX8MM_ANATOP_CLK_CLKOUT1_SEL 57
+#define IMX8MM_ANATOP_CLK_CLKOUT1_DIV 58
+#define IMX8MM_ANATOP_CLK_CLKOUT1 59
+#define IMX8MM_ANATOP_CLK_CLKOUT2_SEL 60
+#define IMX8MM_ANATOP_CLK_CLKOUT2_DIV 61
+#define IMX8MM_ANATOP_CLK_CLKOUT2 62
+
#endif
diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
index 04809edab33c..b2fa73803d45 100644
--- a/include/dt-bindings/clock/imx8mn-clock.h
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -267,4 +267,68 @@
#define IMX8MN_CLK_END 235
+#define IMX8MN_ANATOP_CLK_DUMMY 0
+#define IMX8MN_ANATOP_CLK_32K 1
+#define IMX8MN_ANATOP_CLK_24M 2
+#define IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL 3
+#define IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL 4
+#define IMX8MN_ANATOP_VIDEO_PLL_REF_SEL 5
+#define IMX8MN_ANATOP_DRAM_PLL_REF_SEL 6
+#define IMX8MN_ANATOP_GPU_PLL_REF_SEL 7
+#define IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL 8
+#define IMX8MN_ANATOP_ARM_PLL_REF_SEL 9
+#define IMX8MN_ANATOP_SYS_PLL3_REF_SEL 10
+#define IMX8MN_ANATOP_AUDIO_PLL1 11
+#define IMX8MN_ANATOP_AUDIO_PLL2 12
+#define IMX8MN_ANATOP_VIDEO_PLL 13
+#define IMX8MN_ANATOP_DRAM_PLL 14
+#define IMX8MN_ANATOP_GPU_PLL 15
+#define IMX8MN_ANATOP_M7_ALT_PLL 16
+#define IMX8MN_ANATOP_ARM_PLL 17
+#define IMX8MN_ANATOP_SYS_PLL1 18
+#define IMX8MN_ANATOP_SYS_PLL2 19
+#define IMX8MN_ANATOP_SYS_PLL3 20
+#define IMX8MN_ANATOP_AUDIO_PLL1_BYPASS 21
+#define IMX8MN_ANATOP_AUDIO_PLL2_BYPASS 22
+#define IMX8MN_ANATOP_VIDEO_PLL_BYPASS 23
+#define IMX8MN_ANATOP_DRAM_PLL_BYPASS 24
+#define IMX8MN_ANATOP_GPU_PLL_BYPASS 25
+#define IMX8MN_ANATOP_M7_ALT_PLL_BYPASS 26
+#define IMX8MN_ANATOP_ARM_PLL_BYPASS 27
+#define IMX8MN_ANATOP_SYS_PLL3_BYPASS 28
+#define IMX8MN_ANATOP_AUDIO_PLL1_OUT 29
+#define IMX8MN_ANATOP_AUDIO_PLL2_OUT 30
+#define IMX8MN_ANATOP_VIDEO_PLL_OUT 31
+#define IMX8MN_ANATOP_DRAM_PLL_OUT 32
+#define IMX8MN_ANATOP_GPU_PLL_OUT 33
+#define IMX8MN_ANATOP_M7_ALT_PLL_OUT 34
+#define IMX8MN_ANATOP_ARM_PLL_OUT 35
+#define IMX8MN_ANATOP_SYS_PLL3_OUT 36
+#define IMX8MN_ANATOP_SYS_PLL1_OUT 37
+#define IMX8MN_ANATOP_SYS_PLL1_40M 38
+#define IMX8MN_ANATOP_SYS_PLL1_80M 39
+#define IMX8MN_ANATOP_SYS_PLL1_100M 40
+#define IMX8MN_ANATOP_SYS_PLL1_133M 41
+#define IMX8MN_ANATOP_SYS_PLL1_160M 42
+#define IMX8MN_ANATOP_SYS_PLL1_200M 43
+#define IMX8MN_ANATOP_SYS_PLL1_266M 44
+#define IMX8MN_ANATOP_SYS_PLL1_400M 45
+#define IMX8MN_ANATOP_SYS_PLL1_800M 46
+#define IMX8MN_ANATOP_SYS_PLL2_OUT 47
+#define IMX8MN_ANATOP_SYS_PLL2_50M 48
+#define IMX8MN_ANATOP_SYS_PLL2_100M 49
+#define IMX8MN_ANATOP_SYS_PLL2_125M 50
+#define IMX8MN_ANATOP_SYS_PLL2_166M 51
+#define IMX8MN_ANATOP_SYS_PLL2_200M 52
+#define IMX8MN_ANATOP_SYS_PLL2_250M 53
+#define IMX8MN_ANATOP_SYS_PLL2_333M 54
+#define IMX8MN_ANATOP_SYS_PLL2_500M 55
+#define IMX8MN_ANATOP_SYS_PLL2_1000M 56
+#define IMX8MN_ANATOP_CLK_CLKOUT1_SEL 57
+#define IMX8MN_ANATOP_CLK_CLKOUT1_DIV 58
+#define IMX8MN_ANATOP_CLK_CLKOUT1 59
+#define IMX8MN_ANATOP_CLK_CLKOUT2_SEL 60
+#define IMX8MN_ANATOP_CLK_CLKOUT2_DIV 61
+#define IMX8MN_ANATOP_CLK_CLKOUT2 62
+
#endif
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index 3235d7de3b62..8c076225fd9e 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -402,4 +402,72 @@
#define IMX8MP_CLK_AUDIOMIX_END 59
+#define IMX8MP_ANATOP_CLK_DUMMY 0
+#define IMX8MP_ANATOP_CLK_24M 1
+#define IMX8MP_ANATOP_CLK_32K 2
+#define IMX8MP_ANATOP_AUDIO_PLL1_REF_SEL 3
+#define IMX8MP_ANATOP_AUDIO_PLL2_REF_SEL 4
+#define IMX8MP_ANATOP_VIDEO_PLL_REF_SEL 5
+#define IMX8MP_ANATOP_DRAM_PLL_REF_SEL 6
+#define IMX8MP_ANATOP_GPU_PLL_REF_SEL 7
+#define IMX8MP_ANATOP_VPU_PLL_REF_SEL 8
+#define IMX8MP_ANATOP_ARM_PLL_REF_SEL 9
+#define IMX8MP_ANATOP_SYS_PLL1_REF_SEL 10
+#define IMX8MP_ANATOP_SYS_PLL2_REF_SEL 11
+#define IMX8MP_ANATOP_SYS_PLL3_REF_SEL 12
+#define IMX8MP_ANATOP_AUDIO_PLL1 13
+#define IMX8MP_ANATOP_AUDIO_PLL2 14
+#define IMX8MP_ANATOP_VIDEO_PLL 15
+#define IMX8MP_ANATOP_DRAM_PLL 16
+#define IMX8MP_ANATOP_GPU_PLL 17
+#define IMX8MP_ANATOP_VPU_PLL 18
+#define IMX8MP_ANATOP_ARM_PLL 19
+#define IMX8MP_ANATOP_SYS_PLL1 20
+#define IMX8MP_ANATOP_SYS_PLL2 21
+#define IMX8MP_ANATOP_SYS_PLL3 22
+#define IMX8MP_ANATOP_AUDIO_PLL1_BYPASS 23
+#define IMX8MP_ANATOP_AUDIO_PLL2_BYPASS 24
+#define IMX8MP_ANATOP_VIDEO_PLL_BYPASS 25
+#define IMX8MP_ANATOP_DRAM_PLL_BYPASS 26
+#define IMX8MP_ANATOP_GPU_PLL_BYPASS 27
+#define IMX8MP_ANATOP_VPU_PLL_BYPASS 28
+#define IMX8MP_ANATOP_ARM_PLL_BYPASS 29
+#define IMX8MP_ANATOP_SYS_PLL1_BYPASS 30
+#define IMX8MP_ANATOP_SYS_PLL2_BYPASS 31
+#define IMX8MP_ANATOP_SYS_PLL3_BYPASS 32
+#define IMX8MP_ANATOP_AUDIO_PLL1_OUT 33
+#define IMX8MP_ANATOP_AUDIO_PLL2_OUT 34
+#define IMX8MP_ANATOP_VIDEO_PLL_OUT 35
+#define IMX8MP_ANATOP_DRAM_PLL_OUT 36
+#define IMX8MP_ANATOP_GPU_PLL_OUT 37
+#define IMX8MP_ANATOP_VPU_PLL_OUT 38
+#define IMX8MP_ANATOP_ARM_PLL_OUT 39
+#define IMX8MP_ANATOP_SYS_PLL3_OUT 40
+#define IMX8MP_ANATOP_SYS_PLL1_OUT 41
+#define IMX8MP_ANATOP_SYS_PLL1_40M 42
+#define IMX8MP_ANATOP_SYS_PLL1_80M 43
+#define IMX8MP_ANATOP_SYS_PLL1_100M 44
+#define IMX8MP_ANATOP_SYS_PLL1_133M 45
+#define IMX8MP_ANATOP_SYS_PLL1_160M 46
+#define IMX8MP_ANATOP_SYS_PLL1_200M 47
+#define IMX8MP_ANATOP_SYS_PLL1_266M 48
+#define IMX8MP_ANATOP_SYS_PLL1_400M 49
+#define IMX8MP_ANATOP_SYS_PLL1_800M 50
+#define IMX8MP_ANATOP_SYS_PLL2_OUT 51
+#define IMX8MP_ANATOP_SYS_PLL2_50M 52
+#define IMX8MP_ANATOP_SYS_PLL2_100M 53
+#define IMX8MP_ANATOP_SYS_PLL2_125M 54
+#define IMX8MP_ANATOP_SYS_PLL2_166M 55
+#define IMX8MP_ANATOP_SYS_PLL2_200M 56
+#define IMX8MP_ANATOP_SYS_PLL2_250M 57
+#define IMX8MP_ANATOP_SYS_PLL2_333M 58
+#define IMX8MP_ANATOP_SYS_PLL2_500M 59
+#define IMX8MP_ANATOP_SYS_PLL2_1000M 60
+#define IMX8MP_ANATOP_CLK_CLKOUT1_SEL 61
+#define IMX8MP_ANATOP_CLK_CLKOUT1_DIV 62
+#define IMX8MP_ANATOP_CLK_CLKOUT1 63
+#define IMX8MP_ANATOP_CLK_CLKOUT2_SEL 64
+#define IMX8MP_ANATOP_CLK_CLKOUT2_DIV 65
+#define IMX8MP_ANATOP_CLK_CLKOUT2 66
+
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 10/23] clk: imx: add hw API imx_anatop_get_clk_hw
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
` (4 preceding siblings ...)
2025-01-18 12:39 ` [PATCH v9 05/23] dt-bindings: clock: imx8m-anatop: add oscillators and PLLs Dario Binacchi
@ 2025-01-18 12:39 ` Dario Binacchi
2025-01-18 12:39 ` [PATCH v9 11/23] clk: imx: add support for i.MX8MN anatop clock driver Dario Binacchi
` (10 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:39 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Peng Fan, Abel Vesa, Fabio Estevam,
Michael Turquette, Pengutronix Kernel Team, Sascha Hauer,
Shawn Guo, Stephen Boyd, imx, linux-arm-kernel, linux-clk
Get the hw of a clock registered by the anatop module. This function is
preparatory for future developments.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
Changes in v9:
- Add 'Reviewed-by' tag of Peng Fan
Changes in v7:
- Add device_node type parameter to imx8m_anatop_get_clk_hw()
- Rename imx8m_anatop_get_clk_hw() to imx_anatop_get_clk_hw()
- Drop the gaurding macros so the code can be used also by i.MX9
Changes in v5:
- Consider CONFIG_CLK_IMX8M{M,N,P,Q}_MODULE to fix compilation errors
Changes in v4:
- New
drivers/clk/imx/clk.c | 15 +++++++++++++++
drivers/clk/imx/clk.h | 2 ++
2 files changed, 17 insertions(+)
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index df83bd939492..a906d3cd960b 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -128,6 +128,21 @@ struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name)
}
EXPORT_SYMBOL_GPL(imx_get_clk_hw_by_name);
+struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id)
+{
+ struct of_phandle_args args;
+ struct clk_hw *hw;
+
+ args.np = np;
+ args.args_count = 1;
+ args.args[0] = id;
+
+ hw = __clk_get_hw(of_clk_get_from_provider(&args));
+ pr_debug("%s: got clk: %s\n", __func__, clk_hw_get_name(hw));
+ return hw;
+}
+EXPORT_SYMBOL_GPL(imx_anatop_get_clk_hw);
+
/*
* This fixups the register CCM_CSCMR1 write value.
* The write/read/divider values of the aclk_podf field
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index aa5202f284f3..50e407cf48d9 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -487,4 +487,6 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,
u32 reg, const char **parent_names,
u8 num_parents, const u32 *mux_table, u32 mask);
+struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id);
+
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 11/23] clk: imx: add support for i.MX8MN anatop clock driver
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
` (5 preceding siblings ...)
2025-01-18 12:39 ` [PATCH v9 10/23] clk: imx: add hw API imx_anatop_get_clk_hw Dario Binacchi
@ 2025-01-18 12:39 ` Dario Binacchi
2025-01-18 12:39 ` [PATCH v9 12/23] dt-bindings: clock: imx8m-clock: add PLLs Dario Binacchi
` (9 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:39 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Peng Fan, Abel Vesa, Dan Carpenter,
Fabio Estevam, Michael Turquette, Pengutronix Kernel Team,
Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel,
linux-clk
Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root.
By doing so, we also simplify the CCM driver code. The changes are
backward compatible.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
Changes in v9:
- Fix a build warning raised by the kernel test robot
- Add 'Reviewed-by' tag of Peng Fan
Changes in v8:
- Drop call of of_parse_phandle() to get the anatop's device node.
Changes in v7:
- Update the code based on the changes made to the
imx8m_anatop_get_clk_hw():
- Rename imx8m_anatop_get_clk_hw to imx_anatop_get_clk_hw
- Add device_node type parameter
- Call of_parse_phandle() to get the anatop's device node.
Changes in v6:
- Define IMX8MN_ANATOP_CLK_END inside the driver after it has ben
removed from include/dt-bindings/clock/imx8mn-clock.h.
Changes in v4:
- New
drivers/clk/imx/Makefile | 2 +-
drivers/clk/imx/clk-imx8mn-anatop.c | 283 ++++++++++++++++++++++++++++
drivers/clk/imx/clk-imx8mn.c | 183 ++++++++----------
3 files changed, 364 insertions(+), 104 deletions(-)
create mode 100644 drivers/clk/imx/clk-imx8mn-anatop.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 03f2b2a1ab63..f0f1d01c68f8 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -26,7 +26,7 @@ mxc-clk-objs += clk-gpr-mux.o
obj-$(CONFIG_MXC_CLK) += mxc-clk.o
obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
-obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
+obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn-anatop.o clk-imx8mn.o
obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
diff --git a/drivers/clk/imx/clk-imx8mn-anatop.c b/drivers/clk/imx/clk-imx8mn-anatop.c
new file mode 100644
index 000000000000..5091794948eb
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mn-anatop.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * clk-imx8mn-anatop.c - NXP i.MX8MN anatop clock driver
+ *
+ * Copyright (c) 2024 Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ */
+
+#include <dt-bindings/clock/imx8mn-clock.h>
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/of_platform.h>
+
+#include "clk.h"
+
+#define IMX8MN_ANATOP_CLK_END (IMX8MN_ANATOP_CLK_CLKOUT2 + 1)
+
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
+static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
+static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
+static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
+static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
+static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
+static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll", "m7_alt_pll_ref_sel", };
+static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
+static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
+ "dummy", "dummy", "gpu_pll_out", "dummy",
+ "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
+ "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
+
+static struct clk_hw_onecell_data *clk_hw_data;
+static struct clk_hw **hws;
+
+static int imx8mn_anatop_clocks_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ void __iomem *base;
+ int ret;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base)) {
+ dev_err(dev, "failed to get base address\n");
+ return PTR_ERR(base);
+ }
+
+ clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
+ IMX8MN_ANATOP_CLK_END),
+ GFP_KERNEL);
+ if (WARN_ON(!clk_hw_data))
+ return -ENOMEM;
+
+ clk_hw_data->num = IMX8MN_ANATOP_CLK_END;
+ hws = clk_hw_data->hws;
+
+ hws[IMX8MN_ANATOP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
+ hws[IMX8MN_ANATOP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
+ hws[IMX8MN_ANATOP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
+
+ hws[IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL] =
+ imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL] =
+ imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_ANATOP_VIDEO_PLL_REF_SEL] =
+ imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_ANATOP_DRAM_PLL_REF_SEL] =
+ imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_ANATOP_GPU_PLL_REF_SEL] =
+ imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL] =
+ imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_ANATOP_ARM_PLL_REF_SEL] =
+ imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_ANATOP_SYS_PLL3_REF_SEL] =
+ imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+
+ hws[IMX8MN_ANATOP_AUDIO_PLL1] =
+ imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel",
+ base, &imx_1443x_pll);
+ hws[IMX8MN_ANATOP_AUDIO_PLL2] =
+ imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel",
+ base + 0x14, &imx_1443x_pll);
+ hws[IMX8MN_ANATOP_VIDEO_PLL] =
+ imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel",
+ base + 0x28, &imx_1443x_pll);
+ hws[IMX8MN_ANATOP_DRAM_PLL] =
+ imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50,
+ &imx_1443x_dram_pll);
+ hws[IMX8MN_ANATOP_GPU_PLL] =
+ imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64,
+ &imx_1416x_pll);
+ hws[IMX8MN_ANATOP_M7_ALT_PLL] =
+ imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel",
+ base + 0x74, &imx_1416x_pll);
+ hws[IMX8MN_ANATOP_ARM_PLL] =
+ imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84,
+ &imx_1416x_pll);
+ hws[IMX8MN_ANATOP_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000);
+ hws[IMX8MN_ANATOP_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000);
+ hws[IMX8MN_ANATOP_SYS_PLL3] =
+ imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114,
+ &imx_1416x_pll);
+
+ /* PLL bypass out */
+ hws[IMX8MN_ANATOP_AUDIO_PLL1_BYPASS] =
+ imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1,
+ audio_pll1_bypass_sels,
+ ARRAY_SIZE(audio_pll1_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MN_ANATOP_AUDIO_PLL2_BYPASS] =
+ imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1,
+ audio_pll2_bypass_sels,
+ ARRAY_SIZE(audio_pll2_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MN_ANATOP_VIDEO_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1,
+ video_pll_bypass_sels,
+ ARRAY_SIZE(video_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MN_ANATOP_DRAM_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1,
+ dram_pll_bypass_sels,
+ ARRAY_SIZE(dram_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MN_ANATOP_GPU_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1,
+ gpu_pll_bypass_sels,
+ ARRAY_SIZE(gpu_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MN_ANATOP_M7_ALT_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1,
+ m7_alt_pll_bypass_sels,
+ ARRAY_SIZE(m7_alt_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MN_ANATOP_ARM_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1,
+ arm_pll_bypass_sels,
+ ARRAY_SIZE(arm_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MN_ANATOP_SYS_PLL3_BYPASS] =
+ imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1,
+ sys_pll3_bypass_sels,
+ ARRAY_SIZE(sys_pll3_bypass_sels),
+ CLK_SET_RATE_PARENT);
+
+ /* PLL out gate */
+ hws[IMX8MN_ANATOP_AUDIO_PLL1_OUT] =
+ imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass",
+ base, 13);
+ hws[IMX8MN_ANATOP_AUDIO_PLL2_OUT] =
+ imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass",
+ base + 0x14, 13);
+ hws[IMX8MN_ANATOP_VIDEO_PLL_OUT] =
+ imx_clk_hw_gate("video_pll_out", "video_pll_bypass",
+ base + 0x28, 13);
+ hws[IMX8MN_ANATOP_DRAM_PLL_OUT] =
+ imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass",
+ base + 0x50, 13);
+ hws[IMX8MN_ANATOP_GPU_PLL_OUT] =
+ imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass",
+ base + 0x64, 11);
+ hws[IMX8MN_ANATOP_M7_ALT_PLL_OUT] =
+ imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass",
+ base + 0x74, 11);
+ hws[IMX8MN_ANATOP_ARM_PLL_OUT] =
+ imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass",
+ base + 0x84, 11);
+ hws[IMX8MN_ANATOP_SYS_PLL3_OUT] =
+ imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass",
+ base + 0x114, 11);
+
+ /* SYS PLL1 fixed output */
+ hws[IMX8MN_ANATOP_SYS_PLL1_OUT] =
+ imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
+ hws[IMX8MN_ANATOP_SYS_PLL1_40M] =
+ imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
+ hws[IMX8MN_ANATOP_SYS_PLL1_80M] =
+ imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
+ hws[IMX8MN_ANATOP_SYS_PLL1_100M] =
+ imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
+ hws[IMX8MN_ANATOP_SYS_PLL1_133M] =
+ imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
+ hws[IMX8MN_ANATOP_SYS_PLL1_160M] =
+ imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
+ hws[IMX8MN_ANATOP_SYS_PLL1_200M] =
+ imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
+ hws[IMX8MN_ANATOP_SYS_PLL1_266M] =
+ imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
+ hws[IMX8MN_ANATOP_SYS_PLL1_400M] =
+ imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
+ hws[IMX8MN_ANATOP_SYS_PLL1_800M] =
+ imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
+
+ /* SYS PLL2 fixed output */
+ hws[IMX8MN_ANATOP_SYS_PLL2_OUT] =
+ imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
+ hws[IMX8MN_ANATOP_SYS_PLL2_50M] =
+ imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
+ hws[IMX8MN_ANATOP_SYS_PLL2_100M] =
+ imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
+ hws[IMX8MN_ANATOP_SYS_PLL2_125M] =
+ imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
+ hws[IMX8MN_ANATOP_SYS_PLL2_166M] =
+ imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
+ hws[IMX8MN_ANATOP_SYS_PLL2_200M] =
+ imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
+ hws[IMX8MN_ANATOP_SYS_PLL2_250M] =
+ imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
+ hws[IMX8MN_ANATOP_SYS_PLL2_333M] =
+ imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
+ hws[IMX8MN_ANATOP_SYS_PLL2_500M] =
+ imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
+ hws[IMX8MN_ANATOP_SYS_PLL2_1000M] =
+ imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
+
+ hws[IMX8MN_ANATOP_CLK_CLKOUT1_SEL] =
+ imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4,
+ clkout_sels, ARRAY_SIZE(clkout_sels));
+ hws[IMX8MN_ANATOP_CLK_CLKOUT1_DIV] =
+ imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128,
+ 0, 4);
+ hws[IMX8MN_ANATOP_CLK_CLKOUT1] =
+ imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
+ hws[IMX8MN_ANATOP_CLK_CLKOUT2_SEL] =
+ imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4,
+ clkout_sels, ARRAY_SIZE(clkout_sels));
+ hws[IMX8MN_ANATOP_CLK_CLKOUT2_DIV] =
+ imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128,
+ 16, 4);
+ hws[IMX8MN_ANATOP_CLK_CLKOUT2] =
+ imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
+
+ imx_check_clk_hws(hws, IMX8MN_ANATOP_CLK_END);
+
+ ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
+ if (ret < 0) {
+ imx_unregister_hw_clocks(hws, IMX8MN_ANATOP_CLK_END);
+ return dev_err_probe(dev, ret,
+ "failed to register anatop clock provider\n");
+ }
+
+ dev_info(dev, "NXP i.MX8MN anatop clock driver probed\n");
+ return 0;
+}
+
+static const struct of_device_id imx8mn_anatop_clk_of_match[] = {
+ { .compatible = "fsl,imx8mn-anatop" },
+ { /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, imx8mn_anatop_clk_of_match);
+
+static struct platform_driver imx8mn_anatop_clk_driver = {
+ .probe = imx8mn_anatop_clocks_probe,
+ .driver = {
+ .name = "imx8mn-anatop",
+ /*
+ * Disable bind attributes: clocks are not removed and
+ * reloading the driver will crash or break devices.
+ */
+ .suppress_bind_attrs = true,
+ .of_match_table = imx8mn_anatop_clk_of_match,
+ },
+};
+
+module_platform_driver(imx8mn_anatop_clk_driver);
+
+MODULE_AUTHOR("Dario Binacchi <dario.binacchi@amarulasolutions.com>");
+MODULE_DESCRIPTION("NXP i.MX8MN anatop clock driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index ab77e148e70c..c3a3d063d58e 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -24,16 +24,6 @@ static u32 share_count_disp;
static u32 share_count_pdm;
static u32 share_count_nand;
-static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
-static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
-static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
-static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
-static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
-static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
-static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll", "m7_alt_pll_ref_sel", };
-static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
-static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
-
static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
@@ -308,21 +298,20 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy
"sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
"video_pll_out", "osc_32k", };
-static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
- "dummy", "dummy", "gpu_pll_out", "dummy",
- "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
- "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
-
static struct clk_hw_onecell_data *clk_hw_data;
static struct clk_hw **hws;
static int imx8mn_clocks_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
+ struct device_node *np = dev->of_node, *anp;
void __iomem *base;
int ret;
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (WARN_ON(IS_ERR(base)))
+ return PTR_ERR(base);
+
clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
IMX8MN_CLK_END), GFP_KERNEL);
if (WARN_ON(!clk_hw_data))
@@ -331,99 +320,90 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
clk_hw_data->num = IMX8MN_CLK_END;
hws = clk_hw_data->hws;
- hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
- hws[IMX8MN_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
- hws[IMX8MN_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
+ anp = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
+ if (!anp)
+ return dev_err_probe(dev, -ENODEV, "missing anatop\n");
+
+ of_node_put(anp);
+
+ hws[IMX8MN_CLK_DUMMY] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_DUMMY);
+ hws[IMX8MN_CLK_24M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_24M);
+ hws[IMX8MN_CLK_32K] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_32K);
hws[IMX8MN_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");
hws[IMX8MN_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2");
hws[IMX8MN_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3");
hws[IMX8MN_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4");
- np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
- base = devm_of_iomap(dev, np, 0, NULL);
- of_node_put(np);
- if (WARN_ON(IS_ERR(base))) {
- ret = PTR_ERR(base);
- goto unregister_hws;
- }
-
- hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
-
- hws[IMX8MN_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
- hws[IMX8MN_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);
- hws[IMX8MN_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", base + 0x28, &imx_1443x_pll);
- hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll);
- hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
- hws[IMX8MN_M7_ALT_PLL] = imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", base + 0x74, &imx_1416x_pll);
- hws[IMX8MN_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll);
- hws[IMX8MN_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000);
- hws[IMX8MN_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000);
- hws[IMX8MN_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll);
+ hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL);
+ hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL);
+ hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL_REF_SEL);
+ hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL_REF_SEL);
+ hws[IMX8MN_GPU_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL_REF_SEL);
+ hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL);
+ hws[IMX8MN_ARM_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL_REF_SEL);
+ hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_REF_SEL);
+
+ hws[IMX8MN_AUDIO_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1);
+ hws[IMX8MN_AUDIO_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2);
+ hws[IMX8MN_VIDEO_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL);
+ hws[IMX8MN_DRAM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL);
+ hws[IMX8MN_GPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL);
+ hws[IMX8MN_M7_ALT_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL);
+ hws[IMX8MN_ARM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL);
+ hws[IMX8MN_SYS_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1);
+ hws[IMX8MN_SYS_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2);
+ hws[IMX8MN_SYS_PLL3] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3);
/* PLL bypass out */
- hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
+ hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1_BYPASS);
+ hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2_BYPASS);
+ hws[IMX8MN_VIDEO_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL_BYPASS);
+ hws[IMX8MN_DRAM_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL_BYPASS);
+ hws[IMX8MN_GPU_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL_BYPASS);
+ hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL_BYPASS);
+ hws[IMX8MN_ARM_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL_BYPASS);
+ hws[IMX8MN_SYS_PLL3_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_BYPASS);
/* PLL out gate */
- hws[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
- hws[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
- hws[IMX8MN_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", base + 0x28, 13);
- hws[IMX8MN_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
- hws[IMX8MN_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
- hws[IMX8MN_M7_ALT_PLL_OUT] = imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", base + 0x74, 11);
- hws[IMX8MN_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
- hws[IMX8MN_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
+ hws[IMX8MN_AUDIO_PLL1_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1_OUT);
+ hws[IMX8MN_AUDIO_PLL2_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2_OUT);
+ hws[IMX8MN_VIDEO_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL_OUT);
+ hws[IMX8MN_DRAM_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL_OUT);
+ hws[IMX8MN_GPU_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL_OUT);
+ hws[IMX8MN_M7_ALT_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL_OUT);
+ hws[IMX8MN_ARM_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL_OUT);
+ hws[IMX8MN_SYS_PLL3_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_OUT);
/* SYS PLL1 fixed output */
- hws[IMX8MN_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
- hws[IMX8MN_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
- hws[IMX8MN_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
- hws[IMX8MN_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
- hws[IMX8MN_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
- hws[IMX8MN_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
- hws[IMX8MN_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
- hws[IMX8MN_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
- hws[IMX8MN_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
- hws[IMX8MN_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
+ hws[IMX8MN_SYS_PLL1_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_OUT);
+ hws[IMX8MN_SYS_PLL1_40M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_40M);
+ hws[IMX8MN_SYS_PLL1_80M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_80M);
+ hws[IMX8MN_SYS_PLL1_100M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_100M);
+ hws[IMX8MN_SYS_PLL1_133M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_133M);
+ hws[IMX8MN_SYS_PLL1_160M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_160M);
+ hws[IMX8MN_SYS_PLL1_200M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_200M);
+ hws[IMX8MN_SYS_PLL1_266M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_266M);
+ hws[IMX8MN_SYS_PLL1_400M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_400M);
+ hws[IMX8MN_SYS_PLL1_800M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_800M);
/* SYS PLL2 fixed output */
- hws[IMX8MN_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
- hws[IMX8MN_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
- hws[IMX8MN_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
- hws[IMX8MN_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
- hws[IMX8MN_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
- hws[IMX8MN_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
- hws[IMX8MN_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
- hws[IMX8MN_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
- hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
- hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
-
- hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
- hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
- hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
- hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
- hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
- hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
-
- np = dev->of_node;
- base = devm_platform_ioremap_resource(pdev, 0);
- if (WARN_ON(IS_ERR(base))) {
- ret = PTR_ERR(base);
- goto unregister_hws;
- }
+ hws[IMX8MN_SYS_PLL2_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_OUT);
+ hws[IMX8MN_SYS_PLL2_50M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_50M);
+ hws[IMX8MN_SYS_PLL2_100M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_100M);
+ hws[IMX8MN_SYS_PLL2_125M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_125M);
+ hws[IMX8MN_SYS_PLL2_166M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_166M);
+ hws[IMX8MN_SYS_PLL2_200M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_200M);
+ hws[IMX8MN_SYS_PLL2_250M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_250M);
+ hws[IMX8MN_SYS_PLL2_333M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_333M);
+ hws[IMX8MN_SYS_PLL2_500M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_500M);
+ hws[IMX8MN_SYS_PLL2_1000M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_1000M);
+
+ hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT1_SEL);
+ hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT1_DIV);
+ hws[IMX8MN_CLK_CLKOUT1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT1);
+ hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT2_SEL);
+ hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT2_DIV);
+ hws[IMX8MN_CLK_CLKOUT2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT2);
/* CORE */
hws[IMX8MN_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mn_a53_sels, base + 0x8000);
@@ -599,18 +579,15 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
if (ret < 0) {
- dev_err(dev, "failed to register hws for i.MX8MN\n");
- goto unregister_hws;
+ imx_unregister_hw_clocks(hws, IMX8MN_CLK_END);
+ return dev_err_probe(dev, ret,
+ "failed to register hws for i.MX8MN\n");
}
imx_register_uart_clocks();
+ dev_info(dev, "NXP i.MX8MN ccm clock driver probed\n");
return 0;
-
-unregister_hws:
- imx_unregister_hw_clocks(hws, IMX8MN_CLK_END);
-
- return ret;
}
static const struct of_device_id imx8mn_clk_of_match[] = {
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 12/23] dt-bindings: clock: imx8m-clock: add PLLs
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
` (6 preceding siblings ...)
2025-01-18 12:39 ` [PATCH v9 11/23] clk: imx: add support for i.MX8MN anatop clock driver Dario Binacchi
@ 2025-01-18 12:39 ` Dario Binacchi
2025-01-18 12:39 ` [PATCH v9 16/23] dt-bindings: clock: imx8m-clock: support spread spectrum clocking Dario Binacchi
` (8 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:39 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Krzysztof Kozlowski, Abel Vesa,
Conor Dooley, Fabio Estevam, Krzysztof Kozlowski,
Michael Turquette, Peng Fan, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree, imx,
linux-arm-kernel, linux-clk
Though adding the PLLs to clocks and clock-names properties will break
the ABI, it is required to accurately describe the hardware. Indeed,
the Clock Control Module (CCM) receives clocks from the PLLs and
oscillators and generates clocks for on-chip peripherals.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
(no changes since v7)
Changes in v7:
- Add 'Reviewed-by' tag of Krzysztof Kozlowski
Changes in v6:
- New
.../bindings/clock/imx8m-clock.yaml | 27 ++++++++++++++-----
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
index c643d4a81478..d96570bf60dc 100644
--- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
@@ -29,12 +29,12 @@ properties:
maxItems: 2
clocks:
- minItems: 6
- maxItems: 7
+ minItems: 7
+ maxItems: 10
clock-names:
- minItems: 6
- maxItems: 7
+ minItems: 7
+ maxItems: 10
'#clock-cells':
const: 1
@@ -86,6 +86,10 @@ allOf:
- description: ext2 clock input
- description: ext3 clock input
- description: ext4 clock input
+ - description: audio1 PLL input
+ - description: audio2 PLL input
+ - description: dram PLL input
+ - description: video PLL input
clock-names:
items:
@@ -95,20 +99,31 @@ allOf:
- const: clk_ext2
- const: clk_ext3
- const: clk_ext4
+ - const: audio_pll1
+ - const: audio_pll2
+ - const: dram_pll
+ - const: video_pll
additionalProperties: false
examples:
# Clock Control Module node:
- |
+ #include <dt-bindings/clock/imx8mm-clock.h>
+
clock-controller@30380000 {
compatible = "fsl,imx8mm-ccm";
reg = <0x30380000 0x10000>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
- <&clk_ext3>, <&clk_ext4>;
+ <&clk_ext3>, <&clk_ext4>,
+ <&anatop IMX8MM_ANATOP_AUDIO_PLL1>,
+ <&anatop IMX8MM_ANATOP_AUDIO_PLL2>,
+ <&anatop IMX8MM_ANATOP_DRAM_PLL>,
+ <&anatop IMX8MM_ANATOP_VIDEO_PLL>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4";
+ "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2",
+ "dram_pll", "video_pll";
};
- |
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 16/23] dt-bindings: clock: imx8m-clock: support spread spectrum clocking
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
` (7 preceding siblings ...)
2025-01-18 12:39 ` [PATCH v9 12/23] dt-bindings: clock: imx8m-clock: add PLLs Dario Binacchi
@ 2025-01-18 12:39 ` Dario Binacchi
2025-01-24 13:43 ` Krzysztof Kozlowski
2025-01-18 12:40 ` [PATCH v9 17/23] clk: imx: pll14xx: support spread spectrum clock generation Dario Binacchi
` (7 subsequent siblings)
16 siblings, 1 reply; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:39 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Krzysztof Kozlowski, Abel Vesa,
Conor Dooley, Fabio Estevam, Krzysztof Kozlowski,
Michael Turquette, Peng Fan, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree, imx,
linux-arm-kernel, linux-clk
The addition of DT bindings for enabling and tuning spread spectrum
clocking generation can be applied specifically to the PLLs.
The "" value for the fsl,ssc-method property is specifically intended to
specify a "no SSC" case, as in the example, when you don't want to
configure spread spectrum for one of the PLLs, thus avoiding the use of
a method that would only make sense if SSC were being set.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
(no changes since v7)
Changes in v7:
- List the PLLs to strictly define the setup order for each of the
added properties
- Drop maxItems from "fsl,ssc-modfreq-hz" and "fsl,ssc-modrate-percent"
properties
- Add 'Reviewed-by' tag of Krzysztof Kozlowski
Changes in v6:
- Improve the commit message
- change minItems from 7 to 1 for all the ssc properties added
- change maxItems from 10 to 4 for alle the ssc properties added
- update the DTS example
Changes in v4:
- Drop "fsl,ssc-clocks" property. The other added properties now refer
to the clock list.
- Updated minItems and maxItems of
- clocks
- clock-names
- fsl,ssc-modfreq-hz
- fsl,ssc-modrate-percent
- fsl,ssc-modmethod
- Updated the dts examples
Changes in v3:
- Added in v3
- The dt-bindings have been moved from fsl,imx8m-anatop.yaml to
imx8m-clock.yaml. The anatop device (fsl,imx8m-anatop.yaml) is
indeed more or less a syscon, so it represents a memory area
accessible by ccm (imx8m-clock.yaml) to setup the PLLs.
Changes in v2:
- Add "allOf:" and place it after "required:" block, like in the
example schema.
- Move the properties definition to the top-level.
- Drop unit types as requested by the "make dt_binding_check" command.
.../bindings/clock/imx8m-clock.yaml | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
index d96570bf60dc..d347d630764a 100644
--- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
@@ -43,6 +43,46 @@ properties:
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h
for the full list of i.MX8M clock IDs.
+ fsl,ssc-modfreq-hz:
+ description:
+ The values of modulation frequency (Hz unit) for each clock
+ supporting spread spectrum.
+ minItems: 1
+ items:
+ - description: audio_pll1
+ - description: audio_pll2
+ - description: dram_pll
+ - description: video_pll
+
+ fsl,ssc-modrate-percent:
+ description:
+ The percentage values of modulation rate for each clock
+ supporting spread spectrum.
+ minItems: 1
+ items:
+ - description: audio_pll1
+ - description: audio_pll2
+ - description: dram_pll
+ - description: video_pll
+
+ fsl,ssc-modmethod:
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ description: |
+ The modulation techniques for each clock supporting spread
+ spectrum in this order::
+ - audio_pll1
+ - audio_pll2
+ - dram_pll
+ - video_pll
+ minItems: 1
+ maxItems: 4
+ items:
+ enum:
+ - ""
+ - down-spread
+ - up-spread
+ - center-spread
+
required:
- compatible
- reg
@@ -76,6 +116,10 @@ allOf:
- const: clk_ext2
- const: clk_ext3
- const: clk_ext4
+ fsl,ssc-modfreq-hz: false
+ fsl,ssc-modrate-percent: false
+ fsl,ssc-modmethod: false
+
else:
properties:
clocks:
@@ -124,6 +168,9 @@ examples:
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2",
"dram_pll", "video_pll";
+ fsl,ssc-modfreq-hz = <6818>, <0>, <0>, <2419>;
+ fsl,ssc-modrate-percent = <3>, <0>, <0>, <7>;
+ fsl,ssc-modmethod = "down-spread", "", "", "center-spread";
};
- |
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v9 16/23] dt-bindings: clock: imx8m-clock: support spread spectrum clocking
2025-01-18 12:39 ` [PATCH v9 16/23] dt-bindings: clock: imx8m-clock: support spread spectrum clocking Dario Binacchi
@ 2025-01-24 13:43 ` Krzysztof Kozlowski
0 siblings, 0 replies; 22+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-24 13:43 UTC (permalink / raw)
To: Dario Binacchi, linux-kernel
Cc: linux-amarula, Krzysztof Kozlowski, Abel Vesa, Conor Dooley,
Fabio Estevam, Krzysztof Kozlowski, Michael Turquette, Peng Fan,
Pengutronix Kernel Team, Rob Herring, Sascha Hauer, Shawn Guo,
Stephen Boyd, devicetree, imx, linux-arm-kernel, linux-clk
On 18/01/2025 13:39, Dario Binacchi wrote:
> The addition of DT bindings for enabling and tuning spread spectrum
> clocking generation can be applied specifically to the PLLs.
>
> The "" value for the fsl,ssc-method property is specifically intended to
> specify a "no SSC" case, as in the example, when you don't want to
> configure spread spectrum for one of the PLLs, thus avoiding the use of
> a method that would only make sense if SSC were being set.
>
> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> ---
>
> (no changes since v7)
>
> Changes in v7:
> - List the PLLs to strictly define the setup order for each of the
> added properties
> - Drop maxItems from "fsl,ssc-modfreq-hz" and "fsl,ssc-modrate-percent"
> properties
> - Add 'Reviewed-by' tag of Krzysztof Kozlowski
>
> Changes in v6:
> - Improve the commit message
> - change minItems from 7 to 1 for all the ssc properties added
> - change maxItems from 10 to 4 for alle the ssc properties added
> - update the DTS example
>
> Changes in v4:
> - Drop "fsl,ssc-clocks" property. The other added properties now refer
> to the clock list.
> - Updated minItems and maxItems of
> - clocks
> - clock-names
> - fsl,ssc-modfreq-hz
> - fsl,ssc-modrate-percent
> - fsl,ssc-modmethod
> - Updated the dts examples
>
> Changes in v3:
> - Added in v3
> - The dt-bindings have been moved from fsl,imx8m-anatop.yaml to
> imx8m-clock.yaml. The anatop device (fsl,imx8m-anatop.yaml) is
> indeed more or less a syscon, so it represents a memory area
> accessible by ccm (imx8m-clock.yaml) to setup the PLLs.
>
> Changes in v2:
> - Add "allOf:" and place it after "required:" block, like in the
> example schema.
> - Move the properties definition to the top-level.
> - Drop unit types as requested by the "make dt_binding_check" command.
>
> .../bindings/clock/imx8m-clock.yaml | 47 +++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
> index d96570bf60dc..d347d630764a 100644
> --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
> @@ -43,6 +43,46 @@ properties:
> ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h
> for the full list of i.MX8M clock IDs.
>
> + fsl,ssc-modfreq-hz:
> + description:
> + The values of modulation frequency (Hz unit) for each clock
> + supporting spread spectrum.
> + minItems: 1
> + items:
> + - description: audio_pll1
> + - description: audio_pll2
> + - description: dram_pll
> + - description: video_pll
Ehh, so it looks that nine versions of this patches for iMX8 and NXP
comes with generic bindings for iMX9.
Better late than never, but a pity that they did not share the
intention, which would spare you effort.
Please work with Peng and unify approach for entire iMX and use common
bindings.
https://github.com/devicetree-org/dt-schema/pull/154
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v9 17/23] clk: imx: pll14xx: support spread spectrum clock generation
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
` (8 preceding siblings ...)
2025-01-18 12:39 ` [PATCH v9 16/23] dt-bindings: clock: imx8m-clock: support spread spectrum clocking Dario Binacchi
@ 2025-01-18 12:40 ` Dario Binacchi
2025-01-18 12:40 ` [PATCH v9 18/23] clk: imx8mn: " Dario Binacchi
` (6 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:40 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Peng Fan, Abel Vesa, Fabio Estevam,
Michael Turquette, Pengutronix Kernel Team, Sascha Hauer,
Shawn Guo, Stephen Boyd, imx, linux-arm-kernel, linux-clk
Add support for spread spectrum clock (SSC) generation to the pll14xxx
driver.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
(no changes since v7)
Changes in v7:
- Add 'Reviewed-by' tag of Peng Fan
Changes in v6:
- Update the code based on the changes made to the DT bindings
drivers/clk/imx/clk-pll14xx.c | 134 ++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk.h | 16 ++++
2 files changed, 150 insertions(+)
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index d63564dbb12c..c20f1ade9dff 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -20,6 +20,8 @@
#define GNRL_CTL 0x0
#define DIV_CTL0 0x4
#define DIV_CTL1 0x8
+#define SSCG_CTRL 0xc
+
#define LOCK_STATUS BIT(31)
#define LOCK_SEL_MASK BIT(29)
#define CLKE_MASK BIT(11)
@@ -31,6 +33,10 @@
#define KDIV_MASK GENMASK(15, 0)
#define KDIV_MIN SHRT_MIN
#define KDIV_MAX SHRT_MAX
+#define SSCG_ENABLE BIT(31)
+#define MFREQ_CTL_MASK GENMASK(19, 12)
+#define MRAT_CTL_MASK GENMASK(9, 4)
+#define SEL_PF_MASK GENMASK(1, 0)
#define LOCK_TIMEOUT_US 10000
@@ -40,6 +46,8 @@ struct clk_pll14xx {
enum imx_pll14xx_type type;
const struct imx_pll14xx_rate_table *rate_table;
int rate_count;
+ bool ssc_enable;
+ struct imx_pll14xx_ssc ssc_conf;
};
#define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw)
@@ -347,6 +355,27 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
return 0;
}
+static void clk_pll1443x_enable_ssc(struct clk_hw *hw, unsigned long parent_rate,
+ unsigned int pdiv, unsigned int mdiv)
+{
+ struct clk_pll14xx *pll = to_clk_pll14xx(hw);
+ struct imx_pll14xx_ssc *conf = &pll->ssc_conf;
+ u32 sscg_ctrl, mfr, mrr;
+
+ sscg_ctrl = readl_relaxed(pll->base + SSCG_CTRL);
+ sscg_ctrl &=
+ ~(SSCG_ENABLE | MFREQ_CTL_MASK | MRAT_CTL_MASK | SEL_PF_MASK);
+
+ mfr = parent_rate / (conf->mod_freq * pdiv * (1 << 5));
+ mrr = (conf->mod_rate * mdiv * (1 << 6)) / (100 * mfr);
+
+ sscg_ctrl |= SSCG_ENABLE | FIELD_PREP(MFREQ_CTL_MASK, mfr) |
+ FIELD_PREP(MRAT_CTL_MASK, mrr) |
+ FIELD_PREP(SEL_PF_MASK, conf->mod_type);
+
+ writel_relaxed(sscg_ctrl, pll->base + SSCG_CTRL);
+}
+
static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
@@ -368,6 +397,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv),
pll->base + DIV_CTL1);
+ if (pll->ssc_enable)
+ clk_pll1443x_enable_ssc(hw, prate, rate.pdiv, rate.mdiv);
+
return 0;
}
@@ -408,6 +440,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
gnrl_ctl &= ~BYPASS_MASK;
writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);
+ if (pll->ssc_enable)
+ clk_pll1443x_enable_ssc(hw, prate, rate.pdiv, rate.mdiv);
+
return 0;
}
@@ -542,3 +577,102 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
return hw;
}
EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx);
+
+void imx_clk_pll14xx_enable_ssc(struct clk_hw *hw, struct imx_pll14xx_ssc *conf)
+{
+ struct clk_pll14xx *pll = to_clk_pll14xx(hw);
+
+ pll->ssc_enable = true;
+ memcpy(&pll->ssc_conf, conf, sizeof(pll->ssc_conf));
+}
+EXPORT_SYMBOL_GPL(imx_clk_pll14xx_enable_ssc);
+
+static int clk_pll14xx_ssc_mod_type(const char *name,
+ enum imx_pll14xx_ssc_mod_type *mod_type)
+{
+ int i;
+ struct {
+ const char *name;
+ enum imx_pll14xx_ssc_mod_type id;
+ } mod_types[] = {
+ { .name = "down-spread", .id = IMX_PLL14XX_SSC_DOWN_SPREAD },
+ { .name = "up-spread", .id = IMX_PLL14XX_SSC_UP_SPREAD },
+ { .name = "center-spread", .id = IMX_PLL14XX_SSC_CENTER_SPREAD }
+ };
+
+ for (i = 0; i < ARRAY_SIZE(mod_types); i++) {
+ if (!strcmp(name, mod_types[i].name)) {
+ *mod_type = mod_types[i].id;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int clk_pll14xx_ssc_index(const char *pll_name)
+{
+ static const char *const pll_names[] = {
+ "audio_pll1",
+ "audio_pll2",
+ "dram_pll",
+ "video_pll"
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pll_names); i++) {
+ if (!strcmp(pll_names[i], pll_name))
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+int imx_clk_pll14xx_ssc_parse_dt(struct device_node *np, const char *pll_name,
+ struct imx_pll14xx_ssc *conf)
+{
+ int index, ret;
+ const char *s;
+
+ if (!conf)
+ return -EINVAL;
+
+ index = clk_pll14xx_ssc_index(pll_name);
+ if (index < 0)
+ return index;
+
+ ret = of_property_read_u32_index(np, "fsl,ssc-modfreq-hz", index,
+ &conf->mod_freq);
+ if (ret)
+ return ret;
+
+ ret = of_property_read_u32_index(np, "fsl,ssc-modrate-percent", index,
+ &conf->mod_rate);
+ if (ret) {
+ pr_err("missing fsl,ssc-modrate-percent property for %pOFn\n",
+ np);
+ return ret;
+ }
+
+ ret = of_property_read_string_index(np, "fsl,ssc-modmethod", index, &s);
+ if (ret) {
+ pr_err("failed to get fsl,ssc-modmethod property for %pOFn\n",
+ np);
+ return ret;
+ }
+
+ if (strlen(s) == 0)
+ return -ENODEV;
+
+ ret = clk_pll14xx_ssc_mod_type(s, &conf->mod_type);
+ if (ret) {
+ pr_err("wrong fsl,ssc-modmethod property for %pOFn\n", np);
+ return ret;
+ }
+
+ pr_debug("%s: SSC %s settings: mod_freq: %d, mod_rate: %d: mod_method: %s [%d]\n",
+ __func__, pll_name, conf->mod_freq, conf->mod_rate, s, conf->mod_type);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(imx_clk_pll14xx_ssc_parse_dt);
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 50e407cf48d9..38e4a4cf253d 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -69,6 +69,18 @@ struct imx_pll14xx_clk {
int flags;
};
+enum imx_pll14xx_ssc_mod_type {
+ IMX_PLL14XX_SSC_DOWN_SPREAD,
+ IMX_PLL14XX_SSC_UP_SPREAD,
+ IMX_PLL14XX_SSC_CENTER_SPREAD,
+};
+
+struct imx_pll14xx_ssc {
+ unsigned int mod_freq;
+ unsigned int mod_rate;
+ enum imx_pll14xx_ssc_mod_type mod_type;
+};
+
extern struct imx_pll14xx_clk imx_1416x_pll;
extern struct imx_pll14xx_clk imx_1443x_pll;
extern struct imx_pll14xx_clk imx_1443x_dram_pll;
@@ -489,4 +501,8 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,
struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id);
+void imx_clk_pll14xx_enable_ssc(struct clk_hw *hw, struct imx_pll14xx_ssc *conf);
+int imx_clk_pll14xx_ssc_parse_dt(struct device_node *np, const char *pll_name,
+ struct imx_pll14xx_ssc *conf);
+
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 18/23] clk: imx8mn: support spread spectrum clock generation
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
` (9 preceding siblings ...)
2025-01-18 12:40 ` [PATCH v9 17/23] clk: imx: pll14xx: support spread spectrum clock generation Dario Binacchi
@ 2025-01-18 12:40 ` Dario Binacchi
2025-01-18 12:40 ` [PATCH v9 19/23] clk: imx: add support for i.MX8MP anatop clock driver Dario Binacchi
` (5 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:40 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Peng Fan, Abel Vesa, Fabio Estevam,
Michael Turquette, Pengutronix Kernel Team, Sascha Hauer,
Shawn Guo, Stephen Boyd, imx, linux-arm-kernel, linux-clk
Add support for spread spectrum clock generation for the audio, video,
and DRAM PLLs.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
Changes in v9:
- Add 'Reviewed-by' tag of Peng Fan
drivers/clk/imx/clk-imx8mn.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index c3a3d063d58e..090b5924fa01 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -306,6 +306,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node, *anp;
void __iomem *base;
+ struct imx_pll14xx_ssc ssc_conf;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
@@ -344,9 +345,21 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_REF_SEL);
hws[IMX8MN_AUDIO_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll1", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL1], &ssc_conf);
+
hws[IMX8MN_AUDIO_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll2", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL2], &ssc_conf);
+
hws[IMX8MN_VIDEO_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "video_pll", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MN_VIDEO_PLL], &ssc_conf);
+
hws[IMX8MN_DRAM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "dram_pll", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MN_DRAM_PLL], &ssc_conf);
+
hws[IMX8MN_GPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL);
hws[IMX8MN_M7_ALT_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL);
hws[IMX8MN_ARM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL);
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 19/23] clk: imx: add support for i.MX8MP anatop clock driver
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
` (10 preceding siblings ...)
2025-01-18 12:40 ` [PATCH v9 18/23] clk: imx8mn: " Dario Binacchi
@ 2025-01-18 12:40 ` Dario Binacchi
2025-01-18 12:40 ` [PATCH v9 20/23] clk: imx8mp: rename ccm_base to base Dario Binacchi
` (4 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:40 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Abel Vesa, Fabio Estevam,
Michael Turquette, Peng Fan, Pengutronix Kernel Team,
Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel,
linux-clk
Support NXP i.MX8P anatop PLL module which generates PLLs to CCM root.
By doing so, we also simplify the CCM driver code. The changes are
backward compatible.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
drivers/clk/imx/Makefile | 2 +-
drivers/clk/imx/clk-imx8mp-anatop.c | 305 ++++++++++++++++++++++++++++
drivers/clk/imx/clk-imx8mp.c | 187 ++++++++---------
3 files changed, 390 insertions(+), 104 deletions(-)
create mode 100644 drivers/clk/imx/clk-imx8mp-anatop.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index f0f1d01c68f8..0c28a4727e9c 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o
obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn-anatop.o clk-imx8mn.o
-obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o
+obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp-anatop.o clk-imx8mp.o clk-imx8mp-audiomix.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
diff --git a/drivers/clk/imx/clk-imx8mp-anatop.c b/drivers/clk/imx/clk-imx8mp-anatop.c
new file mode 100644
index 000000000000..95ddc3fbadd3
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mp-anatop.c
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * clk-imx8mp-anatop.c - NXP i.MX8MP anatop clock driver
+ *
+ * Copyright (c) 2025 Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ */
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/of_platform.h>
+
+#include "clk.h"
+
+#define IMX8MP_ANATOP_CLK_END (IMX8MP_ANATOP_CLK_CLKOUT2 + 1)
+
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
+static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
+static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
+static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
+static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
+static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
+static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
+static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
+static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
+static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
+static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
+ "dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
+ "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
+ "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
+
+static struct clk_hw_onecell_data *clk_hw_data;
+static struct clk_hw **hws;
+
+static int imx8mp_anatop_clocks_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ void __iomem *base;
+ int ret;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base)) {
+ dev_err(dev, "failed to get base address\n");
+ return PTR_ERR(base);
+ }
+
+ clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
+ IMX8MP_ANATOP_CLK_END),
+ GFP_KERNEL);
+ if (WARN_ON(!clk_hw_data))
+ return -ENOMEM;
+
+ clk_hw_data->num = IMX8MP_ANATOP_CLK_END;
+ hws = clk_hw_data->hws;
+
+ hws[IMX8MP_ANATOP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
+ hws[IMX8MP_ANATOP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
+ hws[IMX8MP_ANATOP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
+
+ hws[IMX8MP_ANATOP_AUDIO_PLL1_REF_SEL] =
+ imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MP_ANATOP_AUDIO_PLL2_REF_SEL] =
+ imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MP_ANATOP_VIDEO_PLL_REF_SEL] =
+ imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MP_ANATOP_DRAM_PLL_REF_SEL] =
+ imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MP_ANATOP_GPU_PLL_REF_SEL] =
+ imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MP_ANATOP_VPU_PLL_REF_SEL] =
+ imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MP_ANATOP_ARM_PLL_REF_SEL] =
+ imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MP_ANATOP_SYS_PLL1_REF_SEL] =
+ imx_clk_hw_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MP_ANATOP_SYS_PLL2_REF_SEL] =
+ imx_clk_hw_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MP_ANATOP_SYS_PLL3_REF_SEL] =
+ imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+
+ hws[IMX8MP_ANATOP_AUDIO_PLL1] =
+ imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel",
+ base, &imx_1443x_pll);
+ hws[IMX8MP_ANATOP_AUDIO_PLL2] =
+ imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel",
+ base + 0x14, &imx_1443x_pll);
+ hws[IMX8MP_ANATOP_VIDEO_PLL] =
+ imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel",
+ base + 0x28, &imx_1443x_pll);
+ hws[IMX8MP_ANATOP_DRAM_PLL] =
+ imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel",
+ base + 0x50, &imx_1443x_dram_pll);
+ hws[IMX8MP_ANATOP_GPU_PLL] =
+ imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel",
+ base + 0x64, &imx_1416x_pll);
+ hws[IMX8MP_ANATOP_VPU_PLL] =
+ imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel",
+ base + 0x74, &imx_1416x_pll);
+ hws[IMX8MP_ANATOP_ARM_PLL] =
+ imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel",
+ base + 0x84, &imx_1416x_pll);
+ hws[IMX8MP_ANATOP_SYS_PLL1] =
+ imx_clk_hw_pll14xx("sys_pll1", "sys_pll1_ref_sel",
+ base + 0x94, &imx_1416x_pll);
+ hws[IMX8MP_ANATOP_SYS_PLL2] =
+ imx_clk_hw_pll14xx("sys_pll2", "sys_pll2_ref_sel",
+ base + 0x104, &imx_1416x_pll);
+ hws[IMX8MP_ANATOP_SYS_PLL3] =
+ imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel",
+ base + 0x114, &imx_1416x_pll);
+
+ hws[IMX8MP_ANATOP_AUDIO_PLL1_BYPASS] =
+ imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1,
+ audio_pll1_bypass_sels,
+ ARRAY_SIZE(audio_pll1_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MP_ANATOP_AUDIO_PLL2_BYPASS] =
+ imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14,
+ 16, 1, audio_pll2_bypass_sels,
+ ARRAY_SIZE(audio_pll2_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MP_ANATOP_VIDEO_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28,
+ 16, 1, video_pll_bypass_sels,
+ ARRAY_SIZE(video_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MP_ANATOP_DRAM_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50,
+ 16, 1, dram_pll_bypass_sels,
+ ARRAY_SIZE(dram_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MP_ANATOP_GPU_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64,
+ 28, 1, gpu_pll_bypass_sels,
+ ARRAY_SIZE(gpu_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MP_ANATOP_VPU_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74,
+ 28, 1, vpu_pll_bypass_sels,
+ ARRAY_SIZE(vpu_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MP_ANATOP_ARM_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84,
+ 28, 1, arm_pll_bypass_sels,
+ ARRAY_SIZE(arm_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MP_ANATOP_SYS_PLL1_BYPASS] =
+ imx_clk_hw_mux_flags("sys_pll1_bypass", base + 0x94,
+ 28, 1, sys_pll1_bypass_sels,
+ ARRAY_SIZE(sys_pll1_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MP_ANATOP_SYS_PLL2_BYPASS] =
+ imx_clk_hw_mux_flags("sys_pll2_bypass", base + 0x104,
+ 28, 1, sys_pll2_bypass_sels,
+ ARRAY_SIZE(sys_pll2_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MP_ANATOP_SYS_PLL3_BYPASS] =
+ imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114,
+ 28, 1, sys_pll3_bypass_sels,
+ ARRAY_SIZE(sys_pll3_bypass_sels),
+ CLK_SET_RATE_PARENT);
+
+ hws[IMX8MP_ANATOP_AUDIO_PLL1_OUT] =
+ imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass",
+ base, 13);
+ hws[IMX8MP_ANATOP_AUDIO_PLL2_OUT] =
+ imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass",
+ base + 0x14, 13);
+ hws[IMX8MP_ANATOP_VIDEO_PLL_OUT] =
+ imx_clk_hw_gate("video_pll_out", "video_pll_bypass",
+ base + 0x28, 13);
+ hws[IMX8MP_ANATOP_DRAM_PLL_OUT] =
+ imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass",
+ base + 0x50, 13);
+ hws[IMX8MP_ANATOP_GPU_PLL_OUT] =
+ imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass",
+ base + 0x64, 11);
+ hws[IMX8MP_ANATOP_VPU_PLL_OUT] =
+ imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass",
+ base + 0x74, 11);
+ hws[IMX8MP_ANATOP_ARM_PLL_OUT] =
+ imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass",
+ base + 0x84, 11);
+ hws[IMX8MP_ANATOP_SYS_PLL3_OUT] =
+ imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass",
+ base + 0x114, 11);
+
+ hws[IMX8MP_ANATOP_SYS_PLL1_OUT] =
+ imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass",
+ base + 0x94, 11);
+
+ hws[IMX8MP_ANATOP_SYS_PLL1_40M] =
+ imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
+ hws[IMX8MP_ANATOP_SYS_PLL1_80M] =
+ imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
+ hws[IMX8MP_ANATOP_SYS_PLL1_100M] =
+ imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
+ hws[IMX8MP_ANATOP_SYS_PLL1_133M] =
+ imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
+ hws[IMX8MP_ANATOP_SYS_PLL1_160M] =
+ imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
+ hws[IMX8MP_ANATOP_SYS_PLL1_200M] =
+ imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
+ hws[IMX8MP_ANATOP_SYS_PLL1_266M] =
+ imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
+ hws[IMX8MP_ANATOP_SYS_PLL1_400M] =
+ imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
+ hws[IMX8MP_ANATOP_SYS_PLL1_800M] =
+ imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
+
+ hws[IMX8MP_ANATOP_SYS_PLL2_OUT] =
+ imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass",
+ base + 0x104, 11);
+
+ hws[IMX8MP_ANATOP_SYS_PLL2_50M] =
+ imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
+ hws[IMX8MP_ANATOP_SYS_PLL2_100M] =
+ imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
+ hws[IMX8MP_ANATOP_SYS_PLL2_125M] =
+ imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
+ hws[IMX8MP_ANATOP_SYS_PLL2_166M] =
+ imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
+ hws[IMX8MP_ANATOP_SYS_PLL2_200M] =
+ imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
+ hws[IMX8MP_ANATOP_SYS_PLL2_250M] =
+ imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
+ hws[IMX8MP_ANATOP_SYS_PLL2_333M] =
+ imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
+ hws[IMX8MP_ANATOP_SYS_PLL2_500M] =
+ imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
+ hws[IMX8MP_ANATOP_SYS_PLL2_1000M] =
+ imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
+
+ hws[IMX8MP_ANATOP_CLK_CLKOUT1_SEL] =
+ imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4,
+ clkout_sels, ARRAY_SIZE(clkout_sels));
+ hws[IMX8MP_ANATOP_CLK_CLKOUT1_DIV] =
+ imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128,
+ 0, 4);
+ hws[IMX8MP_ANATOP_CLK_CLKOUT1] =
+ imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
+ hws[IMX8MP_ANATOP_CLK_CLKOUT2_SEL] =
+ imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4,
+ clkout_sels, ARRAY_SIZE(clkout_sels));
+ hws[IMX8MP_ANATOP_CLK_CLKOUT2_DIV] =
+ imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128,
+ 16, 4);
+ hws[IMX8MP_ANATOP_CLK_CLKOUT2] =
+ imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
+
+ imx_check_clk_hws(hws, IMX8MP_ANATOP_CLK_END);
+
+ ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
+ if (ret < 0) {
+ imx_unregister_hw_clocks(hws, IMX8MP_ANATOP_CLK_END);
+ return dev_err_probe(dev, ret,
+ "failed to register anatop clock provider\n");
+ }
+
+ dev_info(dev, "NXP i.MX8MP anatop clock driver probed\n");
+ return 0;
+}
+
+static const struct of_device_id imx8mp_anatop_clk_of_match[] = {
+ { .compatible = "fsl,imx8mp-anatop" },
+ { /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, imx8mp_anatop_clk_of_match);
+
+static struct platform_driver imx8mp_anatop_clk_driver = {
+ .probe = imx8mp_anatop_clocks_probe,
+ .driver = {
+ .name = "imx8mp-anatop",
+ /*
+ * Disable bind attributes: clocks are not removed and
+ * reloading the driver will crash or break devices.
+ */
+ .suppress_bind_attrs = true,
+ .of_match_table = imx8mp_anatop_clk_of_match,
+ },
+};
+
+module_platform_driver(imx8mp_anatop_clk_driver);
+
+MODULE_AUTHOR("Dario Binacchi <dario.binacchi@amarulasolutions.com>");
+MODULE_DESCRIPTION("NXP i.MX8MP anatop clock driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index e96460534e7d..9dda576e5fbd 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -20,18 +20,6 @@ static u32 share_count_media;
static u32 share_count_usb;
static u32 share_count_audio;
-static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
-static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
-static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
-static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
-static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
-static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
-static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
-static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
-static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
-static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
-static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
-
static const char * const imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
@@ -397,28 +385,16 @@ static const char * const imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "au
static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
-static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
- "dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
- "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
- "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
-
static struct clk_hw **hws;
static struct clk_hw_onecell_data *clk_hw_data;
static int imx8mp_clocks_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct device_node *np;
- void __iomem *anatop_base, *ccm_base;
+ struct device_node *np = dev->of_node, *anp;
+ void __iomem *ccm_base;
int err;
- np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
- anatop_base = devm_of_iomap(dev, np, 0, NULL);
- of_node_put(np);
- if (WARN_ON(IS_ERR(anatop_base)))
- return PTR_ERR(anatop_base);
-
- np = dev->of_node;
ccm_base = devm_platform_ioremap_resource(pdev, 0);
if (WARN_ON(IS_ERR(ccm_base)))
return PTR_ERR(ccm_base);
@@ -430,88 +406,92 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
clk_hw_data->num = IMX8MP_CLK_END;
hws = clk_hw_data->hws;
- hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
- hws[IMX8MP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
- hws[IMX8MP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
+ anp = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
+ if (!anp)
+ return dev_err_probe(dev, -ENODEV, "missing anatop\n");
+
+ of_node_put(anp);
+
+ hws[IMX8MP_CLK_DUMMY] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_DUMMY);
+ hws[IMX8MP_CLK_24M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_24M);
+ hws[IMX8MP_CLK_32K] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_32K);
hws[IMX8MP_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");
hws[IMX8MP_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2");
hws[IMX8MP_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3");
hws[IMX8MP_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4");
- hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MP_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", anatop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", anatop_base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MP_SYS_PLL1_REF_SEL] = imx_clk_hw_mux("sys_pll1_ref_sel", anatop_base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MP_SYS_PLL2_REF_SEL] = imx_clk_hw_mux("sys_pll2_ref_sel", anatop_base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MP_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", anatop_base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
-
- hws[IMX8MP_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", anatop_base, &imx_1443x_pll);
- hws[IMX8MP_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", anatop_base + 0x14, &imx_1443x_pll);
- hws[IMX8MP_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", anatop_base + 0x28, &imx_1443x_pll);
- hws[IMX8MP_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", anatop_base + 0x50, &imx_1443x_dram_pll);
- hws[IMX8MP_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", anatop_base + 0x64, &imx_1416x_pll);
- hws[IMX8MP_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", anatop_base + 0x74, &imx_1416x_pll);
- hws[IMX8MP_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", anatop_base + 0x84, &imx_1416x_pll);
- hws[IMX8MP_SYS_PLL1] = imx_clk_hw_pll14xx("sys_pll1", "sys_pll1_ref_sel", anatop_base + 0x94, &imx_1416x_pll);
- hws[IMX8MP_SYS_PLL2] = imx_clk_hw_pll14xx("sys_pll2", "sys_pll2_ref_sel", anatop_base + 0x104, &imx_1416x_pll);
- hws[IMX8MP_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", anatop_base + 0x114, &imx_1416x_pll);
-
- hws[IMX8MP_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MP_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MP_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", anatop_base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MP_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", anatop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MP_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", anatop_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MP_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", anatop_base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MP_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", anatop_base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MP_SYS_PLL1_BYPASS] = imx_clk_hw_mux_flags("sys_pll1_bypass", anatop_base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MP_SYS_PLL2_BYPASS] = imx_clk_hw_mux_flags("sys_pll2_bypass", anatop_base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MP_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", anatop_base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
-
- hws[IMX8MP_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", anatop_base, 13);
- hws[IMX8MP_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", anatop_base + 0x14, 13);
- hws[IMX8MP_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", anatop_base + 0x28, 13);
- hws[IMX8MP_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", anatop_base + 0x50, 13);
- hws[IMX8MP_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", anatop_base + 0x64, 11);
- hws[IMX8MP_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", anatop_base + 0x74, 11);
- hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11);
- hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11);
-
- hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11);
-
- hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
- hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
- hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
- hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
- hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
- hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
- hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
- hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
- hws[IMX8MP_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
-
- hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11);
-
- hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
- hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
- hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
- hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
- hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
- hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
- hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
- hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
- hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
-
- hws[IMX8MP_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", anatop_base + 0x128, 4, 4,
- imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels));
- hws[IMX8MP_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", anatop_base + 0x128, 0, 4);
- hws[IMX8MP_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", anatop_base + 0x128, 8);
- hws[IMX8MP_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", anatop_base + 0x128, 20, 4,
- imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels));
- hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128, 16, 4);
- hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", anatop_base + 0x128, 24);
+ hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO_PLL1_REF_SEL);
+ hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO_PLL2_REF_SEL);
+ hws[IMX8MP_VIDEO_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VIDEO_PLL_REF_SEL);
+ hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_DRAM_PLL_REF_SEL);
+ hws[IMX8MP_GPU_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_GPU_PLL_REF_SEL);
+ hws[IMX8MP_VPU_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VPU_PLL_REF_SEL);
+ hws[IMX8MP_ARM_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_ARM_PLL_REF_SEL);
+ hws[IMX8MP_SYS_PLL1_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL1_REF_SEL);
+ hws[IMX8MP_SYS_PLL2_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL2_REF_SEL);
+ hws[IMX8MP_SYS_PLL3_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL3_REF_SEL);
+
+ hws[IMX8MP_AUDIO_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO_PLL1);
+ hws[IMX8MP_AUDIO_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO_PLL2);
+ hws[IMX8MP_VIDEO_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VIDEO_PLL);
+ hws[IMX8MP_DRAM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_DRAM_PLL);
+ hws[IMX8MP_GPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_GPU_PLL);
+ hws[IMX8MP_VPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VPU_PLL);
+ hws[IMX8MP_ARM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_ARM_PLL);
+ hws[IMX8MP_SYS_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL1);
+ hws[IMX8MP_SYS_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL2);
+ hws[IMX8MP_SYS_PLL3] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL3);
+
+ hws[IMX8MP_AUDIO_PLL1_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO_PLL1_BYPASS);
+ hws[IMX8MP_AUDIO_PLL2_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO_PLL2_BYPASS);
+ hws[IMX8MP_VIDEO_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VIDEO_PLL_BYPASS);
+ hws[IMX8MP_DRAM_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_DRAM_PLL_BYPASS);
+ hws[IMX8MP_GPU_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_GPU_PLL_BYPASS);
+ hws[IMX8MP_VPU_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VPU_PLL_BYPASS);
+ hws[IMX8MP_ARM_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_ARM_PLL_BYPASS);
+ hws[IMX8MP_SYS_PLL1_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL1_BYPASS);
+ hws[IMX8MP_SYS_PLL2_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL2_BYPASS);
+ hws[IMX8MP_SYS_PLL3_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL3_BYPASS);
+
+ hws[IMX8MP_AUDIO_PLL1_OUT] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO_PLL1_OUT);
+ hws[IMX8MP_AUDIO_PLL2_OUT] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO_PLL2_OUT);
+ hws[IMX8MP_VIDEO_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VIDEO_PLL_OUT);
+ hws[IMX8MP_DRAM_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_DRAM_PLL_OUT);
+ hws[IMX8MP_GPU_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_GPU_PLL_OUT);
+ hws[IMX8MP_VPU_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VPU_PLL_OUT);
+ hws[IMX8MP_ARM_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_ARM_PLL_OUT);
+ hws[IMX8MP_SYS_PLL3_OUT] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL3_OUT);
+
+ hws[IMX8MP_SYS_PLL1_OUT] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL1_OUT);
+
+ hws[IMX8MP_SYS_PLL1_40M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL1_40M);
+ hws[IMX8MP_SYS_PLL1_80M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL1_80M);
+ hws[IMX8MP_SYS_PLL1_100M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL1_100M);
+ hws[IMX8MP_SYS_PLL1_133M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL1_133M);
+ hws[IMX8MP_SYS_PLL1_160M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL1_160M);
+ hws[IMX8MP_SYS_PLL1_200M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL1_200M);
+ hws[IMX8MP_SYS_PLL1_266M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL1_266M);
+ hws[IMX8MP_SYS_PLL1_400M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL1_400M);
+ hws[IMX8MP_SYS_PLL1_800M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL1_800M);
+
+ hws[IMX8MP_SYS_PLL2_OUT] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL2_OUT);
+
+ hws[IMX8MP_SYS_PLL2_50M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL2_50M);
+ hws[IMX8MP_SYS_PLL2_100M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL2_100M);
+ hws[IMX8MP_SYS_PLL2_125M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL2_125M);
+ hws[IMX8MP_SYS_PLL2_166M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL2_166M);
+ hws[IMX8MP_SYS_PLL2_200M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL2_200M);
+ hws[IMX8MP_SYS_PLL2_250M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL2_250M);
+ hws[IMX8MP_SYS_PLL2_333M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL2_333M);
+ hws[IMX8MP_SYS_PLL2_500M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL2_500M);
+ hws[IMX8MP_SYS_PLL2_1000M] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL2_1000M);
+
+ hws[IMX8MP_CLK_CLKOUT1_SEL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_CLKOUT1_SEL);
+ hws[IMX8MP_CLK_CLKOUT1_DIV] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_CLKOUT1_DIV);
+ hws[IMX8MP_CLK_CLKOUT1] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_CLKOUT1);
+ hws[IMX8MP_CLK_CLKOUT2_SEL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_CLKOUT2_SEL);
+ hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_CLKOUT2_DIV);
+ hws[IMX8MP_CLK_CLKOUT2] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_CLKOUT2);
hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
@@ -723,6 +703,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
imx_register_uart_clocks();
+ dev_info(dev, "NXP i.MX8MP ccm clock driver probed\n");
return 0;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 20/23] clk: imx8mp: rename ccm_base to base
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
` (11 preceding siblings ...)
2025-01-18 12:40 ` [PATCH v9 19/23] clk: imx: add support for i.MX8MP anatop clock driver Dario Binacchi
@ 2025-01-18 12:40 ` Dario Binacchi
2025-01-18 12:40 ` [PATCH v9 21/23] clk: imx8mp: support spread spectrum clock generation Dario Binacchi
` (3 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:40 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Abel Vesa, Fabio Estevam,
Michael Turquette, Peng Fan, Pengutronix Kernel Team,
Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel,
linux-clk
The old code also accessed the anatop address space and therefore used
the variables anatop_base and ccm_base to distinguish between the two
address spaces. However, now that a specific anatop driver exists for
the i.MX8MP platform, the variable ccm_base can be renamed to base, as
is usually the case for the variable pointing to the memory region
managed by a Linux driver.
The patch does not introduce any functional changes.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
drivers/clk/imx/clk-imx8mp.c | 378 +++++++++++++++++------------------
1 file changed, 189 insertions(+), 189 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 9dda576e5fbd..012cd3b52e3f 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -392,12 +392,12 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node, *anp;
- void __iomem *ccm_base;
+ void __iomem *base;
int err;
- ccm_base = devm_platform_ioremap_resource(pdev, 0);
- if (WARN_ON(IS_ERR(ccm_base)))
- return PTR_ERR(ccm_base);
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (WARN_ON(IS_ERR(base)))
+ return PTR_ERR(base);
clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MP_CLK_END), GFP_KERNEL);
if (WARN_ON(!clk_hw_data))
@@ -493,198 +493,198 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_CLKOUT2_DIV);
hws[IMX8MP_CLK_CLKOUT2] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_CLKOUT2);
- hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
+ hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, base + 0x8000);
hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
- hws[IMX8MP_CLK_M7_CORE] = imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, ccm_base + 0x8080);
- hws[IMX8MP_CLK_ML_CORE] = imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, ccm_base + 0x8100);
- hws[IMX8MP_CLK_GPU3D_CORE] = imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels, ccm_base + 0x8180);
- hws[IMX8MP_CLK_GPU3D_SHADER_CORE] = imx8m_clk_hw_composite("gpu3d_shader_core", imx8mp_gpu3d_shader_sels, ccm_base + 0x8200);
- hws[IMX8MP_CLK_GPU2D_CORE] = imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, ccm_base + 0x8280);
- hws[IMX8MP_CLK_AUDIO_AXI] = imx8m_clk_hw_composite("audio_axi", imx8mp_audio_axi_sels, ccm_base + 0x8300);
+ hws[IMX8MP_CLK_M7_CORE] = imx8m_clk_hw_composite_core("m7_core", imx8mp_m7_sels, base + 0x8080);
+ hws[IMX8MP_CLK_ML_CORE] = imx8m_clk_hw_composite_core("ml_core", imx8mp_ml_sels, base + 0x8100);
+ hws[IMX8MP_CLK_GPU3D_CORE] = imx8m_clk_hw_composite_core("gpu3d_core", imx8mp_gpu3d_core_sels, base + 0x8180);
+ hws[IMX8MP_CLK_GPU3D_SHADER_CORE] = imx8m_clk_hw_composite("gpu3d_shader_core", imx8mp_gpu3d_shader_sels, base + 0x8200);
+ hws[IMX8MP_CLK_GPU2D_CORE] = imx8m_clk_hw_composite("gpu2d_core", imx8mp_gpu2d_sels, base + 0x8280);
+ hws[IMX8MP_CLK_AUDIO_AXI] = imx8m_clk_hw_composite("audio_axi", imx8mp_audio_axi_sels, base + 0x8300);
hws[IMX8MP_CLK_AUDIO_AXI_SRC] = hws[IMX8MP_CLK_AUDIO_AXI];
- hws[IMX8MP_CLK_HSIO_AXI] = imx8m_clk_hw_composite("hsio_axi", imx8mp_hsio_axi_sels, ccm_base + 0x8380);
- hws[IMX8MP_CLK_MEDIA_ISP] = imx8m_clk_hw_composite("media_isp", imx8mp_media_isp_sels, ccm_base + 0x8400);
+ hws[IMX8MP_CLK_HSIO_AXI] = imx8m_clk_hw_composite("hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380);
+ hws[IMX8MP_CLK_MEDIA_ISP] = imx8m_clk_hw_composite("media_isp", imx8mp_media_isp_sels, base + 0x8400);
/* CORE SEL */
- hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels));
-
- hws[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mp_main_axi_sels, ccm_base + 0x8800);
- hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mp_enet_axi_sels, ccm_base + 0x8880);
- hws[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900);
- hws[IMX8MP_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mp_vpu_bus_sels, ccm_base + 0x8980);
- hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite_bus("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00);
- hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite_bus("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80);
- hws[IMX8MP_CLK_HDMI_APB] = imx8m_clk_hw_composite_bus("hdmi_apb", imx8mp_media_apb_sels, ccm_base + 0x8b00);
- hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite_bus("hdmi_axi", imx8mp_media_axi_sels, ccm_base + 0x8b80);
- hws[IMX8MP_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mp_gpu_axi_sels, ccm_base + 0x8c00);
- hws[IMX8MP_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mp_gpu_ahb_sels, ccm_base + 0x8c80);
- hws[IMX8MP_CLK_NOC] = imx8m_clk_hw_composite_bus_critical("noc", imx8mp_noc_sels, ccm_base + 0x8d00);
- hws[IMX8MP_CLK_NOC_IO] = imx8m_clk_hw_composite_bus_critical("noc_io", imx8mp_noc_io_sels, ccm_base + 0x8d80);
- hws[IMX8MP_CLK_ML_AXI] = imx8m_clk_hw_composite_bus("ml_axi", imx8mp_ml_axi_sels, ccm_base + 0x8e00);
- hws[IMX8MP_CLK_ML_AHB] = imx8m_clk_hw_composite_bus("ml_ahb", imx8mp_ml_ahb_sels, ccm_base + 0x8e80);
-
- hws[IMX8MP_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb_root", imx8mp_ahb_sels, ccm_base + 0x9000);
- hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100);
- hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);
- hws[IMX8MP_CLK_MEDIA_DISP2_PIX] = imx8m_clk_hw_composite_bus_flags("media_disp2_pix", imx8mp_media_disp_pix_sels, ccm_base + 0x9300, CLK_SET_RATE_PARENT);
-
- hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
-
- hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
- hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);
- hws[IMX8MP_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1_sels, ccm_base + 0xa100);
- hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180);
- hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200);
- hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, ccm_base + 0xa280);
- hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", imx8mp_pcie_aux_sels, ccm_base + 0xa400);
- hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, ccm_base + 0xa480);
- hws[IMX8MP_CLK_I2C6] = imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels, ccm_base + 0xa500);
- hws[IMX8MP_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels, ccm_base + 0xa580);
- hws[IMX8MP_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels, ccm_base + 0xa600);
- hws[IMX8MP_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mp_sai3_sels, ccm_base + 0xa680);
- hws[IMX8MP_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mp_sai5_sels, ccm_base + 0xa780);
- hws[IMX8MP_CLK_SAI6] = imx8m_clk_hw_composite("sai6", imx8mp_sai6_sels, ccm_base + 0xa800);
- hws[IMX8MP_CLK_ENET_QOS] = imx8m_clk_hw_composite("enet_qos", imx8mp_enet_qos_sels, ccm_base + 0xa880);
- hws[IMX8MP_CLK_ENET_QOS_TIMER] = imx8m_clk_hw_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, ccm_base + 0xa900);
- hws[IMX8MP_CLK_ENET_REF] = imx8m_clk_hw_composite("enet_ref", imx8mp_enet_ref_sels, ccm_base + 0xa980);
- hws[IMX8MP_CLK_ENET_TIMER] = imx8m_clk_hw_composite("enet_timer", imx8mp_enet_timer_sels, ccm_base + 0xaa00);
- hws[IMX8MP_CLK_ENET_PHY_REF] = imx8m_clk_hw_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, ccm_base + 0xaa80);
- hws[IMX8MP_CLK_NAND] = imx8m_clk_hw_composite("nand", imx8mp_nand_sels, ccm_base + 0xab00);
- hws[IMX8MP_CLK_QSPI] = imx8m_clk_hw_composite("qspi", imx8mp_qspi_sels, ccm_base + 0xab80);
- hws[IMX8MP_CLK_USDHC1] = imx8m_clk_hw_composite("usdhc1", imx8mp_usdhc1_sels, ccm_base + 0xac00);
- hws[IMX8MP_CLK_USDHC2] = imx8m_clk_hw_composite("usdhc2", imx8mp_usdhc2_sels, ccm_base + 0xac80);
- hws[IMX8MP_CLK_I2C1] = imx8m_clk_hw_composite("i2c1", imx8mp_i2c1_sels, ccm_base + 0xad00);
- hws[IMX8MP_CLK_I2C2] = imx8m_clk_hw_composite("i2c2", imx8mp_i2c2_sels, ccm_base + 0xad80);
- hws[IMX8MP_CLK_I2C3] = imx8m_clk_hw_composite("i2c3", imx8mp_i2c3_sels, ccm_base + 0xae00);
- hws[IMX8MP_CLK_I2C4] = imx8m_clk_hw_composite("i2c4", imx8mp_i2c4_sels, ccm_base + 0xae80);
-
- hws[IMX8MP_CLK_UART1] = imx8m_clk_hw_composite("uart1", imx8mp_uart1_sels, ccm_base + 0xaf00);
- hws[IMX8MP_CLK_UART2] = imx8m_clk_hw_composite("uart2", imx8mp_uart2_sels, ccm_base + 0xaf80);
- hws[IMX8MP_CLK_UART3] = imx8m_clk_hw_composite("uart3", imx8mp_uart3_sels, ccm_base + 0xb000);
- hws[IMX8MP_CLK_UART4] = imx8m_clk_hw_composite("uart4", imx8mp_uart4_sels, ccm_base + 0xb080);
- hws[IMX8MP_CLK_USB_CORE_REF] = imx8m_clk_hw_composite("usb_core_ref", imx8mp_usb_core_ref_sels, ccm_base + 0xb100);
- hws[IMX8MP_CLK_USB_PHY_REF] = imx8m_clk_hw_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, ccm_base + 0xb180);
- hws[IMX8MP_CLK_GIC] = imx8m_clk_hw_composite_critical("gic", imx8mp_gic_sels, ccm_base + 0xb200);
- hws[IMX8MP_CLK_ECSPI1] = imx8m_clk_hw_composite("ecspi1", imx8mp_ecspi1_sels, ccm_base + 0xb280);
- hws[IMX8MP_CLK_ECSPI2] = imx8m_clk_hw_composite("ecspi2", imx8mp_ecspi2_sels, ccm_base + 0xb300);
- hws[IMX8MP_CLK_PWM1] = imx8m_clk_hw_composite("pwm1", imx8mp_pwm1_sels, ccm_base + 0xb380);
- hws[IMX8MP_CLK_PWM2] = imx8m_clk_hw_composite("pwm2", imx8mp_pwm2_sels, ccm_base + 0xb400);
- hws[IMX8MP_CLK_PWM3] = imx8m_clk_hw_composite("pwm3", imx8mp_pwm3_sels, ccm_base + 0xb480);
- hws[IMX8MP_CLK_PWM4] = imx8m_clk_hw_composite("pwm4", imx8mp_pwm4_sels, ccm_base + 0xb500);
-
- hws[IMX8MP_CLK_GPT1] = imx8m_clk_hw_composite("gpt1", imx8mp_gpt1_sels, ccm_base + 0xb580);
- hws[IMX8MP_CLK_GPT2] = imx8m_clk_hw_composite("gpt2", imx8mp_gpt2_sels, ccm_base + 0xb600);
- hws[IMX8MP_CLK_GPT3] = imx8m_clk_hw_composite("gpt3", imx8mp_gpt3_sels, ccm_base + 0xb680);
- hws[IMX8MP_CLK_GPT4] = imx8m_clk_hw_composite("gpt4", imx8mp_gpt4_sels, ccm_base + 0xb700);
- hws[IMX8MP_CLK_GPT5] = imx8m_clk_hw_composite("gpt5", imx8mp_gpt5_sels, ccm_base + 0xb780);
- hws[IMX8MP_CLK_GPT6] = imx8m_clk_hw_composite("gpt6", imx8mp_gpt6_sels, ccm_base + 0xb800);
- hws[IMX8MP_CLK_WDOG] = imx8m_clk_hw_composite("wdog", imx8mp_wdog_sels, ccm_base + 0xb900);
- hws[IMX8MP_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk", imx8mp_wrclk_sels, ccm_base + 0xb980);
- hws[IMX8MP_CLK_IPP_DO_CLKO1] = imx8m_clk_hw_composite("ipp_do_clko1", imx8mp_ipp_do_clko1_sels, ccm_base + 0xba00);
- hws[IMX8MP_CLK_IPP_DO_CLKO2] = imx8m_clk_hw_composite("ipp_do_clko2", imx8mp_ipp_do_clko2_sels, ccm_base + 0xba80);
- hws[IMX8MP_CLK_HDMI_FDCC_TST] = imx8m_clk_hw_composite("hdmi_fdcc_tst", imx8mp_hdmi_fdcc_tst_sels, ccm_base + 0xbb00);
- hws[IMX8MP_CLK_HDMI_24M] = imx8m_clk_hw_composite("hdmi_24m", imx8mp_hdmi_24m_sels, ccm_base + 0xbb80);
- hws[IMX8MP_CLK_HDMI_REF_266M] = imx8m_clk_hw_composite("hdmi_ref_266m", imx8mp_hdmi_ref_266m_sels, ccm_base + 0xbc00);
- hws[IMX8MP_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3_sels, ccm_base + 0xbc80);
- hws[IMX8MP_CLK_MEDIA_CAM1_PIX] = imx8m_clk_hw_composite("media_cam1_pix", imx8mp_media_cam1_pix_sels, ccm_base + 0xbd00);
- hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_hw_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80);
- hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite_bus_flags("media_disp1_pix", imx8mp_media_disp_pix_sels, ccm_base + 0xbe00, CLK_SET_RATE_PARENT);
- hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80);
- hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00);
- hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base + 0xbf80);
- hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = imx8m_clk_hw_composite("media_mipi_test_byte", imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100);
- hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", imx8mp_ecspi3_sels, ccm_base + 0xc180);
- hws[IMX8MP_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, ccm_base + 0xc200);
- hws[IMX8MP_CLK_VPU_VC8000E] = imx8m_clk_hw_composite("vpu_vc8000e", imx8mp_vpu_vc8000e_sels, ccm_base + 0xc280);
- hws[IMX8MP_CLK_SAI7] = imx8m_clk_hw_composite("sai7", imx8mp_sai7_sels, ccm_base + 0xc300);
+ hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels));
+
+ hws[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800);
+ hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mp_enet_axi_sels, base + 0x8880);
+ hws[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900);
+ hws[IMX8MP_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus", imx8mp_vpu_bus_sels, base + 0x8980);
+ hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite_bus("media_axi", imx8mp_media_axi_sels, base + 0x8a00);
+ hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite_bus("media_apb", imx8mp_media_apb_sels, base + 0x8a80);
+ hws[IMX8MP_CLK_HDMI_APB] = imx8m_clk_hw_composite_bus("hdmi_apb", imx8mp_media_apb_sels, base + 0x8b00);
+ hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite_bus("hdmi_axi", imx8mp_media_axi_sels, base + 0x8b80);
+ hws[IMX8MP_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mp_gpu_axi_sels, base + 0x8c00);
+ hws[IMX8MP_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mp_gpu_ahb_sels, base + 0x8c80);
+ hws[IMX8MP_CLK_NOC] = imx8m_clk_hw_composite_bus_critical("noc", imx8mp_noc_sels, base + 0x8d00);
+ hws[IMX8MP_CLK_NOC_IO] = imx8m_clk_hw_composite_bus_critical("noc_io", imx8mp_noc_io_sels, base + 0x8d80);
+ hws[IMX8MP_CLK_ML_AXI] = imx8m_clk_hw_composite_bus("ml_axi", imx8mp_ml_axi_sels, base + 0x8e00);
+ hws[IMX8MP_CLK_ML_AHB] = imx8m_clk_hw_composite_bus("ml_ahb", imx8mp_ml_ahb_sels, base + 0x8e80);
+
+ hws[IMX8MP_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb_root", imx8mp_ahb_sels, base + 0x9000);
+ hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mp_audio_ahb_sels, base + 0x9100);
+ hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, base + 0x9200);
+ hws[IMX8MP_CLK_MEDIA_DISP2_PIX] = imx8m_clk_hw_composite_bus_flags("media_disp2_pix", imx8mp_media_disp_pix_sels, base + 0x9300, CLK_SET_RATE_PARENT);
+
+ hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1);
+
+ hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000);
+ hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080);
+ hws[IMX8MP_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1_sels, base + 0xa100);
+ hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, base + 0xa180);
+ hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, base + 0xa200);
+ hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, base + 0xa280);
+ hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400);
+ hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480);
+ hws[IMX8MP_CLK_I2C6] = imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500);
+ hws[IMX8MP_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels, base + 0xa580);
+ hws[IMX8MP_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels, base + 0xa600);
+ hws[IMX8MP_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mp_sai3_sels, base + 0xa680);
+ hws[IMX8MP_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mp_sai5_sels, base + 0xa780);
+ hws[IMX8MP_CLK_SAI6] = imx8m_clk_hw_composite("sai6", imx8mp_sai6_sels, base + 0xa800);
+ hws[IMX8MP_CLK_ENET_QOS] = imx8m_clk_hw_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880);
+ hws[IMX8MP_CLK_ENET_QOS_TIMER] = imx8m_clk_hw_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900);
+ hws[IMX8MP_CLK_ENET_REF] = imx8m_clk_hw_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980);
+ hws[IMX8MP_CLK_ENET_TIMER] = imx8m_clk_hw_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00);
+ hws[IMX8MP_CLK_ENET_PHY_REF] = imx8m_clk_hw_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80);
+ hws[IMX8MP_CLK_NAND] = imx8m_clk_hw_composite("nand", imx8mp_nand_sels, base + 0xab00);
+ hws[IMX8MP_CLK_QSPI] = imx8m_clk_hw_composite("qspi", imx8mp_qspi_sels, base + 0xab80);
+ hws[IMX8MP_CLK_USDHC1] = imx8m_clk_hw_composite("usdhc1", imx8mp_usdhc1_sels, base + 0xac00);
+ hws[IMX8MP_CLK_USDHC2] = imx8m_clk_hw_composite("usdhc2", imx8mp_usdhc2_sels, base + 0xac80);
+ hws[IMX8MP_CLK_I2C1] = imx8m_clk_hw_composite("i2c1", imx8mp_i2c1_sels, base + 0xad00);
+ hws[IMX8MP_CLK_I2C2] = imx8m_clk_hw_composite("i2c2", imx8mp_i2c2_sels, base + 0xad80);
+ hws[IMX8MP_CLK_I2C3] = imx8m_clk_hw_composite("i2c3", imx8mp_i2c3_sels, base + 0xae00);
+ hws[IMX8MP_CLK_I2C4] = imx8m_clk_hw_composite("i2c4", imx8mp_i2c4_sels, base + 0xae80);
+
+ hws[IMX8MP_CLK_UART1] = imx8m_clk_hw_composite("uart1", imx8mp_uart1_sels, base + 0xaf00);
+ hws[IMX8MP_CLK_UART2] = imx8m_clk_hw_composite("uart2", imx8mp_uart2_sels, base + 0xaf80);
+ hws[IMX8MP_CLK_UART3] = imx8m_clk_hw_composite("uart3", imx8mp_uart3_sels, base + 0xb000);
+ hws[IMX8MP_CLK_UART4] = imx8m_clk_hw_composite("uart4", imx8mp_uart4_sels, base + 0xb080);
+ hws[IMX8MP_CLK_USB_CORE_REF] = imx8m_clk_hw_composite("usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100);
+ hws[IMX8MP_CLK_USB_PHY_REF] = imx8m_clk_hw_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180);
+ hws[IMX8MP_CLK_GIC] = imx8m_clk_hw_composite_critical("gic", imx8mp_gic_sels, base + 0xb200);
+ hws[IMX8MP_CLK_ECSPI1] = imx8m_clk_hw_composite("ecspi1", imx8mp_ecspi1_sels, base + 0xb280);
+ hws[IMX8MP_CLK_ECSPI2] = imx8m_clk_hw_composite("ecspi2", imx8mp_ecspi2_sels, base + 0xb300);
+ hws[IMX8MP_CLK_PWM1] = imx8m_clk_hw_composite("pwm1", imx8mp_pwm1_sels, base + 0xb380);
+ hws[IMX8MP_CLK_PWM2] = imx8m_clk_hw_composite("pwm2", imx8mp_pwm2_sels, base + 0xb400);
+ hws[IMX8MP_CLK_PWM3] = imx8m_clk_hw_composite("pwm3", imx8mp_pwm3_sels, base + 0xb480);
+ hws[IMX8MP_CLK_PWM4] = imx8m_clk_hw_composite("pwm4", imx8mp_pwm4_sels, base + 0xb500);
+
+ hws[IMX8MP_CLK_GPT1] = imx8m_clk_hw_composite("gpt1", imx8mp_gpt1_sels, base + 0xb580);
+ hws[IMX8MP_CLK_GPT2] = imx8m_clk_hw_composite("gpt2", imx8mp_gpt2_sels, base + 0xb600);
+ hws[IMX8MP_CLK_GPT3] = imx8m_clk_hw_composite("gpt3", imx8mp_gpt3_sels, base + 0xb680);
+ hws[IMX8MP_CLK_GPT4] = imx8m_clk_hw_composite("gpt4", imx8mp_gpt4_sels, base + 0xb700);
+ hws[IMX8MP_CLK_GPT5] = imx8m_clk_hw_composite("gpt5", imx8mp_gpt5_sels, base + 0xb780);
+ hws[IMX8MP_CLK_GPT6] = imx8m_clk_hw_composite("gpt6", imx8mp_gpt6_sels, base + 0xb800);
+ hws[IMX8MP_CLK_WDOG] = imx8m_clk_hw_composite("wdog", imx8mp_wdog_sels, base + 0xb900);
+ hws[IMX8MP_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk", imx8mp_wrclk_sels, base + 0xb980);
+ hws[IMX8MP_CLK_IPP_DO_CLKO1] = imx8m_clk_hw_composite("ipp_do_clko1", imx8mp_ipp_do_clko1_sels, base + 0xba00);
+ hws[IMX8MP_CLK_IPP_DO_CLKO2] = imx8m_clk_hw_composite("ipp_do_clko2", imx8mp_ipp_do_clko2_sels, base + 0xba80);
+ hws[IMX8MP_CLK_HDMI_FDCC_TST] = imx8m_clk_hw_composite("hdmi_fdcc_tst", imx8mp_hdmi_fdcc_tst_sels, base + 0xbb00);
+ hws[IMX8MP_CLK_HDMI_24M] = imx8m_clk_hw_composite("hdmi_24m", imx8mp_hdmi_24m_sels, base + 0xbb80);
+ hws[IMX8MP_CLK_HDMI_REF_266M] = imx8m_clk_hw_composite("hdmi_ref_266m", imx8mp_hdmi_ref_266m_sels, base + 0xbc00);
+ hws[IMX8MP_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80);
+ hws[IMX8MP_CLK_MEDIA_CAM1_PIX] = imx8m_clk_hw_composite("media_cam1_pix", imx8mp_media_cam1_pix_sels, base + 0xbd00);
+ hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_hw_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, base + 0xbd80);
+ hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite_bus_flags("media_disp1_pix", imx8mp_media_disp_pix_sels, base + 0xbe00, CLK_SET_RATE_PARENT);
+ hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, base + 0xbe80);
+ hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", imx8mp_media_ldb_sels, base + 0xbf00);
+ hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, base + 0xbf80);
+ hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = imx8m_clk_hw_composite("media_mipi_test_byte", imx8mp_media_mipi_test_byte_sels, base + 0xc100);
+ hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", imx8mp_ecspi3_sels, base + 0xc180);
+ hws[IMX8MP_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, base + 0xc200);
+ hws[IMX8MP_CLK_VPU_VC8000E] = imx8m_clk_hw_composite("vpu_vc8000e", imx8mp_vpu_vc8000e_sels, base + 0xc280);
+ hws[IMX8MP_CLK_SAI7] = imx8m_clk_hw_composite("sai7", imx8mp_sai7_sels, base + 0xc300);
hws[IMX8MP_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
- hws[IMX8MP_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", ccm_base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL);
-
- hws[IMX8MP_CLK_DRAM1_ROOT] = imx_clk_hw_gate4_flags("dram1_root_clk", "dram_core_clk", ccm_base + 0x4050, 0, CLK_IS_CRITICAL);
- hws[IMX8MP_CLK_ECSPI1_ROOT] = imx_clk_hw_gate4("ecspi1_root_clk", "ecspi1", ccm_base + 0x4070, 0);
- hws[IMX8MP_CLK_ECSPI2_ROOT] = imx_clk_hw_gate4("ecspi2_root_clk", "ecspi2", ccm_base + 0x4080, 0);
- hws[IMX8MP_CLK_ECSPI3_ROOT] = imx_clk_hw_gate4("ecspi3_root_clk", "ecspi3", ccm_base + 0x4090, 0);
- hws[IMX8MP_CLK_ENET1_ROOT] = imx_clk_hw_gate4("enet1_root_clk", "enet_axi", ccm_base + 0x40a0, 0);
- hws[IMX8MP_CLK_GPIO1_ROOT] = imx_clk_hw_gate4("gpio1_root_clk", "ipg_root", ccm_base + 0x40b0, 0);
- hws[IMX8MP_CLK_GPIO2_ROOT] = imx_clk_hw_gate4("gpio2_root_clk", "ipg_root", ccm_base + 0x40c0, 0);
- hws[IMX8MP_CLK_GPIO3_ROOT] = imx_clk_hw_gate4("gpio3_root_clk", "ipg_root", ccm_base + 0x40d0, 0);
- hws[IMX8MP_CLK_GPIO4_ROOT] = imx_clk_hw_gate4("gpio4_root_clk", "ipg_root", ccm_base + 0x40e0, 0);
- hws[IMX8MP_CLK_GPIO5_ROOT] = imx_clk_hw_gate4("gpio5_root_clk", "ipg_root", ccm_base + 0x40f0, 0);
- hws[IMX8MP_CLK_GPT1_ROOT] = imx_clk_hw_gate4("gpt1_root_clk", "gpt1", ccm_base + 0x4100, 0);
- hws[IMX8MP_CLK_GPT2_ROOT] = imx_clk_hw_gate4("gpt2_root_clk", "gpt2", ccm_base + 0x4110, 0);
- hws[IMX8MP_CLK_GPT3_ROOT] = imx_clk_hw_gate4("gpt3_root_clk", "gpt3", ccm_base + 0x4120, 0);
- hws[IMX8MP_CLK_GPT4_ROOT] = imx_clk_hw_gate4("gpt4_root_clk", "gpt4", ccm_base + 0x4130, 0);
- hws[IMX8MP_CLK_GPT5_ROOT] = imx_clk_hw_gate4("gpt5_root_clk", "gpt5", ccm_base + 0x4140, 0);
- hws[IMX8MP_CLK_GPT6_ROOT] = imx_clk_hw_gate4("gpt6_root_clk", "gpt6", ccm_base + 0x4150, 0);
- hws[IMX8MP_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1", ccm_base + 0x4170, 0);
- hws[IMX8MP_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", ccm_base + 0x4180, 0);
- hws[IMX8MP_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", ccm_base + 0x4190, 0);
- hws[IMX8MP_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", ccm_base + 0x41a0, 0);
- hws[IMX8MP_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk", "ipg_root", ccm_base + 0x4210, 0);
- hws[IMX8MP_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", ccm_base + 0x4220, 0);
- hws[IMX8MP_CLK_PCIE_ROOT] = imx_clk_hw_gate4("pcie_root_clk", "pcie_aux", ccm_base + 0x4250, 0);
- hws[IMX8MP_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", ccm_base + 0x4280, 0);
- hws[IMX8MP_CLK_PWM2_ROOT] = imx_clk_hw_gate4("pwm2_root_clk", "pwm2", ccm_base + 0x4290, 0);
- hws[IMX8MP_CLK_PWM3_ROOT] = imx_clk_hw_gate4("pwm3_root_clk", "pwm3", ccm_base + 0x42a0, 0);
- hws[IMX8MP_CLK_PWM4_ROOT] = imx_clk_hw_gate4("pwm4_root_clk", "pwm4", ccm_base + 0x42b0, 0);
- hws[IMX8MP_CLK_QOS_ROOT] = imx_clk_hw_gate4("qos_root_clk", "ipg_root", ccm_base + 0x42c0, 0);
- hws[IMX8MP_CLK_QOS_ENET_ROOT] = imx_clk_hw_gate4("qos_enet_root_clk", "ipg_root", ccm_base + 0x42e0, 0);
- hws[IMX8MP_CLK_QSPI_ROOT] = imx_clk_hw_gate4("qspi_root_clk", "qspi", ccm_base + 0x42f0, 0);
- hws[IMX8MP_CLK_NAND_ROOT] = imx_clk_hw_gate2_shared2("nand_root_clk", "nand", ccm_base + 0x4300, 0, &share_count_nand);
- hws[IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", ccm_base + 0x4300, 0, &share_count_nand);
- hws[IMX8MP_CLK_I2C5_ROOT] = imx_clk_hw_gate2("i2c5_root_clk", "i2c5", ccm_base + 0x4330, 0);
- hws[IMX8MP_CLK_I2C6_ROOT] = imx_clk_hw_gate2("i2c6_root_clk", "i2c6", ccm_base + 0x4340, 0);
- hws[IMX8MP_CLK_CAN1_ROOT] = imx_clk_hw_gate2("can1_root_clk", "can1", ccm_base + 0x4350, 0);
- hws[IMX8MP_CLK_CAN2_ROOT] = imx_clk_hw_gate2("can2_root_clk", "can2", ccm_base + 0x4360, 0);
- hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk", "ipg_root", ccm_base + 0x43a0, 0);
- hws[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
- hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base + 0x43b0, 0);
- hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_core", ccm_base + 0x4450, 0);
- hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core", ccm_base + 0x4460, 0);
- hws[IMX8MP_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", ccm_base + 0x4490, 0);
- hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0);
- hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", ccm_base + 0x44b0, 0);
- hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", ccm_base + 0x44c0, 0);
- hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate2_shared2("usb_root_clk", "hsio_axi", ccm_base + 0x44d0, 0, &share_count_usb);
- hws[IMX8MP_CLK_USB_SUSP] = imx_clk_hw_gate2_shared2("usb_suspend_clk", "osc_32k", ccm_base + 0x44d0, 0, &share_count_usb);
- hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk", "usb_phy_ref", ccm_base + 0x44f0, 0);
- hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", ccm_base + 0x4510, 0);
- hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", ccm_base + 0x4520, 0);
- hws[IMX8MP_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk", "wdog", ccm_base + 0x4530, 0);
- hws[IMX8MP_CLK_WDOG2_ROOT] = imx_clk_hw_gate4("wdog2_root_clk", "wdog", ccm_base + 0x4540, 0);
- hws[IMX8MP_CLK_WDOG3_ROOT] = imx_clk_hw_gate4("wdog3_root_clk", "wdog", ccm_base + 0x4550, 0);
- hws[IMX8MP_CLK_VPU_G1_ROOT] = imx_clk_hw_gate4("vpu_g1_root_clk", "vpu_g1", ccm_base + 0x4560, 0);
- hws[IMX8MP_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", ccm_base + 0x4570, 0);
- hws[IMX8MP_CLK_VPU_VC8KE_ROOT] = imx_clk_hw_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", ccm_base + 0x4590, 0);
- hws[IMX8MP_CLK_VPU_G2_ROOT] = imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", ccm_base + 0x45a0, 0);
- hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk", "ml_core", ccm_base + 0x45b0, 0);
- hws[IMX8MP_CLK_HSIO_ROOT] = imx_clk_hw_gate4("hsio_root_clk", "ipg_root", ccm_base + 0x45c0, 0);
- hws[IMX8MP_CLK_MEDIA_APB_ROOT] = imx_clk_hw_gate2_shared2("media_apb_root_clk", "media_apb", ccm_base + 0x45d0, 0, &share_count_media);
- hws[IMX8MP_CLK_MEDIA_AXI_ROOT] = imx_clk_hw_gate2_shared2("media_axi_root_clk", "media_axi", ccm_base + 0x45d0, 0, &share_count_media);
- hws[IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_cam1_pix_root_clk", "media_cam1_pix", ccm_base + 0x45d0, 0, &share_count_media);
- hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix", ccm_base + 0x45d0, 0, &share_count_media);
- hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_media);
- hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_media);
- hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT] = imx_clk_hw_gate2_shared2("media_mipi_phy1_ref_root", "media_mipi_phy1_ref", ccm_base + 0x45d0, 0, &share_count_media);
- hws[IMX8MP_CLK_MEDIA_LDB_ROOT] = imx_clk_hw_gate2_shared2("media_ldb_root_clk", "media_ldb", ccm_base + 0x45d0, 0, &share_count_media);
- hws[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", ccm_base + 0x45d0, 0, &share_count_media);
-
- hws[IMX8MP_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0);
- hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0);
- hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0);
- hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0);
-
- hws[IMX8MP_CLK_AUDIO_AHB_ROOT] = imx_clk_hw_gate2_shared2("audio_ahb_root", "audio_ahb", ccm_base + 0x4650, 0, &share_count_audio);
- hws[IMX8MP_CLK_AUDIO_AXI_ROOT] = imx_clk_hw_gate2_shared2("audio_axi_root", "audio_axi", ccm_base + 0x4650, 0, &share_count_audio);
- hws[IMX8MP_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root", "sai1", ccm_base + 0x4650, 0, &share_count_audio);
- hws[IMX8MP_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root", "sai2", ccm_base + 0x4650, 0, &share_count_audio);
- hws[IMX8MP_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root", "sai3", ccm_base + 0x4650, 0, &share_count_audio);
- hws[IMX8MP_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root", "sai5", ccm_base + 0x4650, 0, &share_count_audio);
- hws[IMX8MP_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root", "sai6", ccm_base + 0x4650, 0, &share_count_audio);
- hws[IMX8MP_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root", "sai7", ccm_base + 0x4650, 0, &share_count_audio);
- hws[IMX8MP_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root", "pdm", ccm_base + 0x4650, 0, &share_count_audio);
+ hws[IMX8MP_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL);
+
+ hws[IMX8MP_CLK_DRAM1_ROOT] = imx_clk_hw_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL);
+ hws[IMX8MP_CLK_ECSPI1_ROOT] = imx_clk_hw_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0);
+ hws[IMX8MP_CLK_ECSPI2_ROOT] = imx_clk_hw_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
+ hws[IMX8MP_CLK_ECSPI3_ROOT] = imx_clk_hw_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
+ hws[IMX8MP_CLK_ENET1_ROOT] = imx_clk_hw_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
+ hws[IMX8MP_CLK_GPIO1_ROOT] = imx_clk_hw_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);
+ hws[IMX8MP_CLK_GPIO2_ROOT] = imx_clk_hw_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);
+ hws[IMX8MP_CLK_GPIO3_ROOT] = imx_clk_hw_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
+ hws[IMX8MP_CLK_GPIO4_ROOT] = imx_clk_hw_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
+ hws[IMX8MP_CLK_GPIO5_ROOT] = imx_clk_hw_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
+ hws[IMX8MP_CLK_GPT1_ROOT] = imx_clk_hw_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0);
+ hws[IMX8MP_CLK_GPT2_ROOT] = imx_clk_hw_gate4("gpt2_root_clk", "gpt2", base + 0x4110, 0);
+ hws[IMX8MP_CLK_GPT3_ROOT] = imx_clk_hw_gate4("gpt3_root_clk", "gpt3", base + 0x4120, 0);
+ hws[IMX8MP_CLK_GPT4_ROOT] = imx_clk_hw_gate4("gpt4_root_clk", "gpt4", base + 0x4130, 0);
+ hws[IMX8MP_CLK_GPT5_ROOT] = imx_clk_hw_gate4("gpt5_root_clk", "gpt5", base + 0x4140, 0);
+ hws[IMX8MP_CLK_GPT6_ROOT] = imx_clk_hw_gate4("gpt6_root_clk", "gpt6", base + 0x4150, 0);
+ hws[IMX8MP_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
+ hws[IMX8MP_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
+ hws[IMX8MP_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0);
+ hws[IMX8MP_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0);
+ hws[IMX8MP_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0);
+ hws[IMX8MP_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
+ hws[IMX8MP_CLK_PCIE_ROOT] = imx_clk_hw_gate4("pcie_root_clk", "pcie_aux", base + 0x4250, 0);
+ hws[IMX8MP_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0);
+ hws[IMX8MP_CLK_PWM2_ROOT] = imx_clk_hw_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0);
+ hws[IMX8MP_CLK_PWM3_ROOT] = imx_clk_hw_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0);
+ hws[IMX8MP_CLK_PWM4_ROOT] = imx_clk_hw_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0);
+ hws[IMX8MP_CLK_QOS_ROOT] = imx_clk_hw_gate4("qos_root_clk", "ipg_root", base + 0x42c0, 0);
+ hws[IMX8MP_CLK_QOS_ENET_ROOT] = imx_clk_hw_gate4("qos_enet_root_clk", "ipg_root", base + 0x42e0, 0);
+ hws[IMX8MP_CLK_QSPI_ROOT] = imx_clk_hw_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0);
+ hws[IMX8MP_CLK_NAND_ROOT] = imx_clk_hw_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand);
+ hws[IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand);
+ hws[IMX8MP_CLK_I2C5_ROOT] = imx_clk_hw_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0);
+ hws[IMX8MP_CLK_I2C6_ROOT] = imx_clk_hw_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0);
+ hws[IMX8MP_CLK_CAN1_ROOT] = imx_clk_hw_gate2("can1_root_clk", "can1", base + 0x4350, 0);
+ hws[IMX8MP_CLK_CAN2_ROOT] = imx_clk_hw_gate2("can2_root_clk", "can2", base + 0x4360, 0);
+ hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk", "ipg_root", base + 0x43a0, 0);
+ hws[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0);
+ hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0);
+ hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_core", base + 0x4450, 0);
+ hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core", base + 0x4460, 0);
+ hws[IMX8MP_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
+ hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
+ hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
+ hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
+ hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate2_shared2("usb_root_clk", "hsio_axi", base + 0x44d0, 0, &share_count_usb);
+ hws[IMX8MP_CLK_USB_SUSP] = imx_clk_hw_gate2_shared2("usb_suspend_clk", "osc_32k", base + 0x44d0, 0, &share_count_usb);
+ hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0);
+ hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
+ hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
+ hws[IMX8MP_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
+ hws[IMX8MP_CLK_WDOG2_ROOT] = imx_clk_hw_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0);
+ hws[IMX8MP_CLK_WDOG3_ROOT] = imx_clk_hw_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0);
+ hws[IMX8MP_CLK_VPU_G1_ROOT] = imx_clk_hw_gate4("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0);
+ hws[IMX8MP_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", base + 0x4570, 0);
+ hws[IMX8MP_CLK_VPU_VC8KE_ROOT] = imx_clk_hw_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", base + 0x4590, 0);
+ hws[IMX8MP_CLK_VPU_G2_ROOT] = imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0);
+ hws[IMX8MP_CLK_NPU_ROOT] = imx_clk_hw_gate4("npu_root_clk", "ml_core", base + 0x45b0, 0);
+ hws[IMX8MP_CLK_HSIO_ROOT] = imx_clk_hw_gate4("hsio_root_clk", "ipg_root", base + 0x45c0, 0);
+ hws[IMX8MP_CLK_MEDIA_APB_ROOT] = imx_clk_hw_gate2_shared2("media_apb_root_clk", "media_apb", base + 0x45d0, 0, &share_count_media);
+ hws[IMX8MP_CLK_MEDIA_AXI_ROOT] = imx_clk_hw_gate2_shared2("media_axi_root_clk", "media_axi", base + 0x45d0, 0, &share_count_media);
+ hws[IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_cam1_pix_root_clk", "media_cam1_pix", base + 0x45d0, 0, &share_count_media);
+ hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix", base + 0x45d0, 0, &share_count_media);
+ hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", base + 0x45d0, 0, &share_count_media);
+ hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", base + 0x45d0, 0, &share_count_media);
+ hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT] = imx_clk_hw_gate2_shared2("media_mipi_phy1_ref_root", "media_mipi_phy1_ref", base + 0x45d0, 0, &share_count_media);
+ hws[IMX8MP_CLK_MEDIA_LDB_ROOT] = imx_clk_hw_gate2_shared2("media_ldb_root_clk", "media_ldb", base + 0x45d0, 0, &share_count_media);
+ hws[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", base + 0x45d0, 0, &share_count_media);
+
+ hws[IMX8MP_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0);
+ hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", base + 0x45f0, 0);
+ hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", base + 0x4620, 0);
+ hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", base + 0x4630, 0);
+
+ hws[IMX8MP_CLK_AUDIO_AHB_ROOT] = imx_clk_hw_gate2_shared2("audio_ahb_root", "audio_ahb", base + 0x4650, 0, &share_count_audio);
+ hws[IMX8MP_CLK_AUDIO_AXI_ROOT] = imx_clk_hw_gate2_shared2("audio_axi_root", "audio_axi", base + 0x4650, 0, &share_count_audio);
+ hws[IMX8MP_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root", "sai1", base + 0x4650, 0, &share_count_audio);
+ hws[IMX8MP_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root", "sai2", base + 0x4650, 0, &share_count_audio);
+ hws[IMX8MP_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root", "sai3", base + 0x4650, 0, &share_count_audio);
+ hws[IMX8MP_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root", "sai5", base + 0x4650, 0, &share_count_audio);
+ hws[IMX8MP_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root", "sai6", base + 0x4650, 0, &share_count_audio);
+ hws[IMX8MP_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root", "sai7", base + 0x4650, 0, &share_count_audio);
+ hws[IMX8MP_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root", "pdm", base + 0x4650, 0, &share_count_audio);
hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
hws[IMX8MP_CLK_A53_CORE]->clk,
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 21/23] clk: imx8mp: support spread spectrum clock generation
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
` (12 preceding siblings ...)
2025-01-18 12:40 ` [PATCH v9 20/23] clk: imx8mp: rename ccm_base to base Dario Binacchi
@ 2025-01-18 12:40 ` Dario Binacchi
2025-01-18 12:40 ` [PATCH v9 22/23] clk: imx: add support for i.MX8MM anatop clock driver Dario Binacchi
` (2 subsequent siblings)
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:40 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Abel Vesa, Fabio Estevam,
Michael Turquette, Peng Fan, Pengutronix Kernel Team,
Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel,
linux-clk
Add support for spread spectrum clock generation for the audio, video,
and DRAM PLLs.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
drivers/clk/imx/clk-imx8mp.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 012cd3b52e3f..560f51d9232d 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -393,6 +393,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node, *anp;
void __iomem *base;
+ struct imx_pll14xx_ssc ssc_conf;
int err;
base = devm_platform_ioremap_resource(pdev, 0);
@@ -432,9 +433,21 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_SYS_PLL3_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_SYS_PLL3_REF_SEL);
hws[IMX8MP_AUDIO_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO_PLL1);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll1", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MP_AUDIO_PLL1], &ssc_conf);
+
hws[IMX8MP_AUDIO_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_AUDIO_PLL2);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll2", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MP_AUDIO_PLL2], &ssc_conf);
+
hws[IMX8MP_VIDEO_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VIDEO_PLL);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "video_pll", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MP_VIDEO_PLL], &ssc_conf);
+
hws[IMX8MP_DRAM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_DRAM_PLL);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "dram_pll", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MP_DRAM_PLL], &ssc_conf);
+
hws[IMX8MP_GPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_GPU_PLL);
hws[IMX8MP_VPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_VPU_PLL);
hws[IMX8MP_ARM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_ARM_PLL);
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 22/23] clk: imx: add support for i.MX8MM anatop clock driver
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
` (13 preceding siblings ...)
2025-01-18 12:40 ` [PATCH v9 21/23] clk: imx8mp: support spread spectrum clock generation Dario Binacchi
@ 2025-01-18 12:40 ` Dario Binacchi
2025-01-18 12:40 ` [PATCH v9 23/23] clk: imx8mm: support spread spectrum clock generation Dario Binacchi
2025-01-24 13:46 ` [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Krzysztof Kozlowski
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:40 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Abel Vesa, Fabio Estevam,
Michael Turquette, Peng Fan, Pengutronix Kernel Team,
Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel,
linux-clk
Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root.
By doing so, we also simplify the CCM driver code. The changes are
backward compatible.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
drivers/clk/imx/Makefile | 2 +-
drivers/clk/imx/clk-imx8mm-anatop.c | 287 ++++++++++++++++++++++++++++
drivers/clk/imx/clk-imx8mm.c | 172 ++++++++---------
3 files changed, 367 insertions(+), 94 deletions(-)
create mode 100644 drivers/clk/imx/clk-imx8mm-anatop.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 0c28a4727e9c..311a557900a9 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -25,7 +25,7 @@ mxc-clk-objs += clk-sscg-pll.o
mxc-clk-objs += clk-gpr-mux.o
obj-$(CONFIG_MXC_CLK) += mxc-clk.o
-obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
+obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm-anatop.o clk-imx8mm.o
obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn-anatop.o clk-imx8mn.o
obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp-anatop.o clk-imx8mp.o clk-imx8mp-audiomix.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
diff --git a/drivers/clk/imx/clk-imx8mm-anatop.c b/drivers/clk/imx/clk-imx8mm-anatop.c
new file mode 100644
index 000000000000..4ac870df6370
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mm-anatop.c
@@ -0,0 +1,287 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * clk-imx8mm-anatop.c - NXP i.MX8MM anatop clock driver
+ *
+ * Copyright (c) 2025 Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ */
+
+#include <dt-bindings/clock/imx8mm-clock.h>
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/of_platform.h>
+
+#include "clk.h"
+
+#define IMX8MM_ANATOP_CLK_END (IMX8MM_ANATOP_CLK_CLKOUT2 + 1)
+
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
+static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
+static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
+static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
+static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
+static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
+static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
+static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
+static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
+ "dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
+ "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
+ "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
+
+static struct clk_hw_onecell_data *clk_hw_data;
+static struct clk_hw **hws;
+
+static int imx8mm_anatop_clocks_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ void __iomem *base;
+ int ret;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base)) {
+ dev_err(dev, "failed to get base address\n");
+ return PTR_ERR(base);
+ }
+
+ clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
+ IMX8MM_ANATOP_CLK_END),
+ GFP_KERNEL);
+ if (WARN_ON(!clk_hw_data))
+ return -ENOMEM;
+
+ clk_hw_data->num = IMX8MM_ANATOP_CLK_END;
+ hws = clk_hw_data->hws;
+
+ hws[IMX8MM_ANATOP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
+ hws[IMX8MM_ANATOP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
+ hws[IMX8MM_ANATOP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
+
+ hws[IMX8MM_ANATOP_AUDIO_PLL1_REF_SEL] =
+ imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MM_ANATOP_AUDIO_PLL2_REF_SEL] =
+ imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MM_ANATOP_VIDEO_PLL_REF_SEL] =
+ imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MM_ANATOP_DRAM_PLL_REF_SEL] =
+ imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MM_ANATOP_GPU_PLL_REF_SEL] =
+ imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MM_ANATOP_VPU_PLL_REF_SEL] =
+ imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MM_ANATOP_ARM_PLL_REF_SEL] =
+ imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MM_ANATOP_SYS_PLL3_REF_SEL] =
+ imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+
+ hws[IMX8MM_ANATOP_AUDIO_PLL1] =
+ imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel",
+ base, &imx_1443x_pll);
+ hws[IMX8MM_ANATOP_AUDIO_PLL2] =
+ imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel",
+ base + 0x14, &imx_1443x_pll);
+ hws[IMX8MM_ANATOP_VIDEO_PLL] =
+ imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel",
+ base + 0x28, &imx_1443x_pll);
+ hws[IMX8MM_ANATOP_DRAM_PLL] =
+ imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel",
+ base + 0x50, &imx_1443x_dram_pll);
+ hws[IMX8MM_ANATOP_GPU_PLL] =
+ imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel",
+ base + 0x64, &imx_1416x_pll);
+ hws[IMX8MM_ANATOP_VPU_PLL] =
+ imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel",
+ base + 0x74, &imx_1416x_pll);
+ hws[IMX8MM_ANATOP_ARM_PLL] =
+ imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel",
+ base + 0x84, &imx_1416x_pll);
+ hws[IMX8MM_ANATOP_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000);
+ hws[IMX8MM_ANATOP_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000);
+ hws[IMX8MM_ANATOP_SYS_PLL3] =
+ imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel",
+ base + 0x114, &imx_1416x_pll);
+
+ /* PLL bypass out */
+ hws[IMX8MM_ANATOP_AUDIO_PLL1_BYPASS] =
+ imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1,
+ audio_pll1_bypass_sels,
+ ARRAY_SIZE(audio_pll1_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MM_ANATOP_AUDIO_PLL2_BYPASS] =
+ imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1,
+ audio_pll2_bypass_sels,
+ ARRAY_SIZE(audio_pll2_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MM_ANATOP_VIDEO_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1,
+ video_pll_bypass_sels,
+ ARRAY_SIZE(video_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MM_ANATOP_DRAM_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1,
+ dram_pll_bypass_sels,
+ ARRAY_SIZE(dram_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MM_ANATOP_GPU_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1,
+ gpu_pll_bypass_sels,
+ ARRAY_SIZE(gpu_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MM_ANATOP_VPU_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1,
+ vpu_pll_bypass_sels,
+ ARRAY_SIZE(vpu_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MM_ANATOP_ARM_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1,
+ arm_pll_bypass_sels,
+ ARRAY_SIZE(arm_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MM_ANATOP_SYS_PLL3_BYPASS] =
+ imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1,
+ sys_pll3_bypass_sels,
+ ARRAY_SIZE(sys_pll3_bypass_sels),
+ CLK_SET_RATE_PARENT);
+
+ /* PLL out gate */
+ hws[IMX8MM_ANATOP_AUDIO_PLL1_OUT] =
+ imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass",
+ base, 13);
+ hws[IMX8MM_ANATOP_AUDIO_PLL2_OUT] =
+ imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass",
+ base + 0x14, 13);
+ hws[IMX8MM_ANATOP_VIDEO_PLL_OUT] =
+ imx_clk_hw_gate("video_pll_out", "video_pll_bypass",
+ base + 0x28, 13);
+ hws[IMX8MM_ANATOP_DRAM_PLL_OUT] =
+ imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass",
+ base + 0x50, 13);
+ hws[IMX8MM_ANATOP_GPU_PLL_OUT] =
+ imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass",
+ base + 0x64, 11);
+ hws[IMX8MM_ANATOP_VPU_PLL_OUT] =
+ imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass",
+ base + 0x74, 11);
+ hws[IMX8MM_ANATOP_ARM_PLL_OUT] =
+ imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass",
+ base + 0x84, 11);
+ hws[IMX8MM_ANATOP_SYS_PLL3_OUT] =
+ imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass",
+ base + 0x114, 11);
+
+ /* SYS PLL1 fixed output */
+ hws[IMX8MM_ANATOP_SYS_PLL1_OUT] =
+ imx_clk_hw_gate("sys_pll1_out", "sys_pll1",
+ base + 0x94, 11);
+
+ hws[IMX8MM_ANATOP_SYS_PLL1_40M] =
+ imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
+ hws[IMX8MM_ANATOP_SYS_PLL1_80M] =
+ imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
+ hws[IMX8MM_ANATOP_SYS_PLL1_100M] =
+ imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
+ hws[IMX8MM_ANATOP_SYS_PLL1_133M] =
+ imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
+ hws[IMX8MM_ANATOP_SYS_PLL1_160M] =
+ imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
+ hws[IMX8MM_ANATOP_SYS_PLL1_200M] =
+ imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
+ hws[IMX8MM_ANATOP_SYS_PLL1_266M] =
+ imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
+ hws[IMX8MM_ANATOP_SYS_PLL1_400M] =
+ imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
+ hws[IMX8MM_ANATOP_SYS_PLL1_800M] =
+ imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
+
+ /* SYS PLL2 fixed output */
+ hws[IMX8MM_ANATOP_SYS_PLL2_OUT] =
+ imx_clk_hw_gate("sys_pll2_out", "sys_pll2",
+ base + 0x104, 11);
+
+ hws[IMX8MM_ANATOP_SYS_PLL2_50M] =
+ imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
+ hws[IMX8MM_ANATOP_SYS_PLL2_100M] =
+ imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
+ hws[IMX8MM_ANATOP_SYS_PLL2_125M] =
+ imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
+ hws[IMX8MM_ANATOP_SYS_PLL2_166M] =
+ imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
+ hws[IMX8MM_ANATOP_SYS_PLL2_200M] =
+ imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
+ hws[IMX8MM_ANATOP_SYS_PLL2_250M] =
+ imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
+ hws[IMX8MM_ANATOP_SYS_PLL2_333M] =
+ imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
+ hws[IMX8MM_ANATOP_SYS_PLL2_500M] =
+ imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
+ hws[IMX8MM_ANATOP_SYS_PLL2_1000M] =
+ imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
+
+ hws[IMX8MM_ANATOP_CLK_CLKOUT1_SEL] =
+ imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4,
+ clkout_sels, ARRAY_SIZE(clkout_sels));
+ hws[IMX8MM_ANATOP_CLK_CLKOUT1_DIV] =
+ imx_clk_hw_divider("clkout1_div", "clkout1_sel",
+ base + 0x128, 0, 4);
+ hws[IMX8MM_ANATOP_CLK_CLKOUT1] =
+ imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
+ hws[IMX8MM_ANATOP_CLK_CLKOUT2_SEL] =
+ imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4,
+ clkout_sels, ARRAY_SIZE(clkout_sels));
+ hws[IMX8MM_ANATOP_CLK_CLKOUT2_DIV] =
+ imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128,
+ 16, 4);
+ hws[IMX8MM_ANATOP_CLK_CLKOUT2] =
+ imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
+
+ imx_check_clk_hws(hws, IMX8MM_ANATOP_CLK_END);
+
+ ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
+ if (ret < 0) {
+ imx_unregister_hw_clocks(hws, IMX8MM_ANATOP_CLK_END);
+ return dev_err_probe(dev, ret,
+ "failed to register anatop clock provider\n");
+ }
+
+ dev_info(dev, "NXP i.MX8MM anatop clock driver probed\n");
+ return 0;
+}
+
+static const struct of_device_id imx8mm_anatop_clk_of_match[] = {
+ { .compatible = "fsl,imx8mm-anatop" },
+ { /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, imx8mm_anatop_clk_of_match);
+
+static struct platform_driver imx8mm_anatop_clk_driver = {
+ .probe = imx8mm_anatop_clocks_probe,
+ .driver = {
+ .name = "imx8mm-anatop",
+ /*
+ * Disable bind attributes: clocks are not removed and
+ * reloading the driver will crash or break devices.
+ */
+ .suppress_bind_attrs = true,
+ .of_match_table = imx8mm_anatop_clk_of_match,
+ },
+};
+
+module_platform_driver(imx8mm_anatop_clk_driver);
+
+MODULE_AUTHOR("Dario Binacchi <dario.binacchi@amarulasolutions.com>");
+MODULE_DESCRIPTION("NXP i.MX8MM anatop clock driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 8a1fc7e17ba2..d39de0a81a6f 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -25,16 +25,6 @@ static u32 share_count_disp;
static u32 share_count_pdm;
static u32 share_count_nand;
-static const char *pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
-static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
-static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
-static const char *video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
-static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
-static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
-static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
-static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
-static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
-
/* CCM ROOT */
static const char *imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
"sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
@@ -288,21 +278,20 @@ static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "
static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m",
"sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", };
-static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
- "dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
- "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
- "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
-
static struct clk_hw_onecell_data *clk_hw_data;
static struct clk_hw **hws;
static int imx8mm_clocks_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
+ struct device_node *np = dev->of_node, *anp;
void __iomem *base;
int ret;
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (WARN_ON(IS_ERR(base)))
+ return PTR_ERR(base);
+
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
IMX8MM_CLK_END), GFP_KERNEL);
if (WARN_ON(!clk_hw_data))
@@ -311,96 +300,92 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
clk_hw_data->num = IMX8MM_CLK_END;
hws = clk_hw_data->hws;
- hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
- hws[IMX8MM_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
- hws[IMX8MM_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
+ anp = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
+ if (!anp)
+ return dev_err_probe(dev, -ENODEV, "missing anatop\n");
+
+ of_node_put(anp);
+
+ hws[IMX8MM_CLK_DUMMY] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_DUMMY);
+ hws[IMX8MM_CLK_24M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_24M);
+ hws[IMX8MM_CLK_32K] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_32K);
hws[IMX8MM_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");
hws[IMX8MM_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2");
hws[IMX8MM_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3");
hws[IMX8MM_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4");
- np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
- base = of_iomap(np, 0);
- of_node_put(np);
- if (WARN_ON(!base))
- return -ENOMEM;
-
- hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MM_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
-
- hws[IMX8MM_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
- hws[IMX8MM_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);
- hws[IMX8MM_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", base + 0x28, &imx_1443x_pll);
- hws[IMX8MM_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll);
- hws[IMX8MM_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
- hws[IMX8MM_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll);
- hws[IMX8MM_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll);
- hws[IMX8MM_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000);
- hws[IMX8MM_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000);
- hws[IMX8MM_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll);
+ hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL1_REF_SEL);
+ hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL2_REF_SEL);
+ hws[IMX8MM_VIDEO_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VIDEO_PLL_REF_SEL);
+ hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_DRAM_PLL_REF_SEL);
+ hws[IMX8MM_GPU_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_GPU_PLL_REF_SEL);
+ hws[IMX8MM_VPU_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VPU_PLL_REF_SEL);
+ hws[IMX8MM_ARM_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_ARM_PLL_REF_SEL);
+ hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL3_REF_SEL);
+
+ hws[IMX8MM_AUDIO_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL1);
+ hws[IMX8MM_AUDIO_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL2);
+ hws[IMX8MM_VIDEO_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VIDEO_PLL);
+ hws[IMX8MM_DRAM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_DRAM_PLL);
+ hws[IMX8MM_GPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_GPU_PLL);
+ hws[IMX8MM_VPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VPU_PLL);
+ hws[IMX8MM_ARM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_ARM_PLL);
+ hws[IMX8MM_SYS_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1);
+ hws[IMX8MM_SYS_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2);
+ hws[IMX8MM_SYS_PLL3] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL3);
/* PLL bypass out */
- hws[IMX8MM_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MM_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MM_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MM_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MM_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MM_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MM_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MM_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
+ hws[IMX8MM_AUDIO_PLL1_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL1_BYPASS);
+ hws[IMX8MM_AUDIO_PLL2_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL2_BYPASS);
+ hws[IMX8MM_VIDEO_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VIDEO_PLL_BYPASS);
+ hws[IMX8MM_DRAM_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_DRAM_PLL_BYPASS);
+ hws[IMX8MM_GPU_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_GPU_PLL_BYPASS);
+ hws[IMX8MM_VPU_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VPU_PLL_BYPASS);
+ hws[IMX8MM_ARM_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_ARM_PLL_BYPASS);
+ hws[IMX8MM_SYS_PLL3_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL3_BYPASS);
/* PLL out gate */
- hws[IMX8MM_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
- hws[IMX8MM_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
- hws[IMX8MM_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", base + 0x28, 13);
- hws[IMX8MM_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
- hws[IMX8MM_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
- hws[IMX8MM_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
- hws[IMX8MM_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
- hws[IMX8MM_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
+ hws[IMX8MM_AUDIO_PLL1_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL1_OUT);
+ hws[IMX8MM_AUDIO_PLL2_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL2_OUT);
+ hws[IMX8MM_VIDEO_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VIDEO_PLL_OUT);
+ hws[IMX8MM_DRAM_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_DRAM_PLL_OUT);
+ hws[IMX8MM_GPU_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_GPU_PLL_OUT);
+ hws[IMX8MM_VPU_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VPU_PLL_OUT);
+ hws[IMX8MM_ARM_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_ARM_PLL_OUT);
+ hws[IMX8MM_SYS_PLL3_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL3_OUT);
/* SYS PLL1 fixed output */
- hws[IMX8MM_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
-
- hws[IMX8MM_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
- hws[IMX8MM_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
- hws[IMX8MM_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
- hws[IMX8MM_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
- hws[IMX8MM_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
- hws[IMX8MM_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
- hws[IMX8MM_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
- hws[IMX8MM_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
- hws[IMX8MM_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
+ hws[IMX8MM_SYS_PLL1_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_OUT);
+
+ hws[IMX8MM_SYS_PLL1_40M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_40M);
+ hws[IMX8MM_SYS_PLL1_80M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_80M);
+ hws[IMX8MM_SYS_PLL1_100M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_100M);
+ hws[IMX8MM_SYS_PLL1_133M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_133M);
+ hws[IMX8MM_SYS_PLL1_160M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_160M);
+ hws[IMX8MM_SYS_PLL1_200M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_200M);
+ hws[IMX8MM_SYS_PLL1_266M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_266M);
+ hws[IMX8MM_SYS_PLL1_400M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_400M);
+ hws[IMX8MM_SYS_PLL1_800M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL1_800M);
/* SYS PLL2 fixed output */
- hws[IMX8MM_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
- hws[IMX8MM_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
- hws[IMX8MM_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
- hws[IMX8MM_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
- hws[IMX8MM_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
- hws[IMX8MM_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
- hws[IMX8MM_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
- hws[IMX8MM_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
- hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
- hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
-
- hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
- hws[IMX8MM_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
- hws[IMX8MM_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
- hws[IMX8MM_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
- hws[IMX8MM_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
- hws[IMX8MM_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
-
- np = dev->of_node;
- base = devm_platform_ioremap_resource(pdev, 0);
- if (WARN_ON(IS_ERR(base)))
- return PTR_ERR(base);
+ hws[IMX8MM_SYS_PLL2_OUT] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_OUT);
+
+ hws[IMX8MM_SYS_PLL2_50M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_50M);
+ hws[IMX8MM_SYS_PLL2_100M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_100M);
+ hws[IMX8MM_SYS_PLL2_125M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_125M);
+ hws[IMX8MM_SYS_PLL2_166M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_166M);
+ hws[IMX8MM_SYS_PLL2_200M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_200M);
+ hws[IMX8MM_SYS_PLL2_250M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_250M);
+ hws[IMX8MM_SYS_PLL2_333M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_333M);
+ hws[IMX8MM_SYS_PLL2_500M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_500M);
+ hws[IMX8MM_SYS_PLL2_1000M] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL2_1000M);
+
+ hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_CLKOUT1_SEL);
+ hws[IMX8MM_CLK_CLKOUT1_DIV] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_CLKOUT1_DIV);
+ hws[IMX8MM_CLK_CLKOUT1] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_CLKOUT1);
+ hws[IMX8MM_CLK_CLKOUT2_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_CLKOUT2_SEL);
+ hws[IMX8MM_CLK_CLKOUT2_DIV] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_CLKOUT2_DIV);
+ hws[IMX8MM_CLK_CLKOUT2] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_CLKOUT2);
/* Core Slice */
hws[IMX8MM_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mm_a53_sels, base + 0x8000);
@@ -611,6 +596,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
imx_register_uart_clocks();
+ dev_info(dev, "NXP i.MX8MM ccm clock driver probed\n");
return 0;
unregister_hws:
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v9 23/23] clk: imx8mm: support spread spectrum clock generation
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
` (14 preceding siblings ...)
2025-01-18 12:40 ` [PATCH v9 22/23] clk: imx: add support for i.MX8MM anatop clock driver Dario Binacchi
@ 2025-01-18 12:40 ` Dario Binacchi
2025-01-24 13:46 ` [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Krzysztof Kozlowski
16 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-18 12:40 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Abel Vesa, Fabio Estevam,
Michael Turquette, Peng Fan, Pengutronix Kernel Team,
Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel,
linux-clk
Add support for spread spectrum clock generation for the audio, video,
and DRAM PLLs.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
Changes in v9:
- Add 'Reviewed-by' tag of Peng Fan for imx8mn platform patches
- Fix building warning raised by the kernel test robot for patch
v8, 11/18 clk: imx: add support for i.MX8MN anatop clock driver
- Add patches for imx8m{m,p} platforms:
- 23/23 clk: imx8mm: support spread spectrum clock generation
- 22/23 clk: imx: add support for i.MX8MM anatop clock driver
- 21/23 clk: imx8mp: support spread spectrum clock generation
- 20/23 clk: imx8mp: rename ccm_base to base
- 19/23 clk: imx: add support for i.MX8MP anatop clock driver
Changes in v8:
- Drop the patches added in version 7:
- 10/23 dt-bindings: clock: imx8m-clock: add phandle to the anatop
- 11/23 arm64: dts: imx8mm: add phandle to anatop within CCM
- 12/23 arm64: dts: imx8mn: add phandle to anatop within CCM
- 13/23 arm64: dts: imx8mp: add phandle to anatop within CCM
- 14/23 arm64: dts: imx8mq: add phandle to anatop within CCM
Changes in v7:
- Add and manage fsl,anatop property as phandle to the anatop node with
the new patches:
- 10/23 dt-bindings: clock: imx8m-clock: add phandle to the anatop
- 11/23 arm64: dts: imx8mm: add phandle to anatop within CCM
- 12/23 arm64: dts: imx8mn: add phandle to anatop within CCM
- 13/23 arm64: dts: imx8mp: add phandle to anatop within CCM
- 14/23 arm64: dts: imx8mq: add phandle to anatop within CCM
Changes in v6:
- Merge patches:
10/20 dt-bindings: clock: imx8mm: add binding definitions for anatop
11/20 dt-bindings: clock: imx8mn: add binding definitions for anatop
12/20 dt-bindings: clock: imx8mp: add binding definitions for anatop
to
05/20 dt-bindings: clock: imx8m-anatop: define clocks/clock-names
now renamed
05/18 dt-bindings: clock: imx8m-anatop: add oscillators and PLLs
- Split the patch
15/20 dt-bindings-clock-imx8m-clock-support-spread-spectru.patch
into
12/18 dt-bindings: clock: imx8m-clock: add PLLs
16/18 dt-bindings: clock: imx8m-clock: support spread spectrum clocking
Changes in v5:
- Fix compilation errors.
- Separate driver code from dt-bindings
Changes in v4:
- Add dt-bindings for anatop
- Add anatop driver
- Drop fsl,ssc-clocks from spread spectrum dt-bindings
Changes in v3:
- Patches 1/8 has been added in version 3. The dt-bindings have
been moved from fsl,imx8m-anatop.yaml to imx8m-clock.yaml. The
anatop device (fsl,imx8m-anatop.yaml) is indeed more or less a
syscon, so it represents a memory area accessible by ccm
(imx8m-clock.yaml) to setup the PLLs.
- Patches {3,5}/8 have been added in version 3.
- Patches {4,6,8}/8 use ccm device node instead of the anatop one.
Changes in v2:
- Add "allOf:" and place it after "required:" block, like in the
example schema.
- Move the properties definition to the top-level.
- Drop unit types as requested by the "make dt_binding_check" command.
drivers/clk/imx/clk-imx8mm.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index d39de0a81a6f..f8413f495d5d 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -286,6 +286,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node, *anp;
void __iomem *base;
+ struct imx_pll14xx_ssc ssc_conf;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
@@ -324,9 +325,21 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL3_REF_SEL);
hws[IMX8MM_AUDIO_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL1);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll1", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MM_AUDIO_PLL1], &ssc_conf);
+
hws[IMX8MM_AUDIO_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO_PLL2);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll2", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MM_AUDIO_PLL2], &ssc_conf);
+
hws[IMX8MM_VIDEO_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VIDEO_PLL);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "video_pll", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MM_VIDEO_PLL], &ssc_conf);
+
hws[IMX8MM_DRAM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_DRAM_PLL);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "dram_pll", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MM_DRAM_PLL], &ssc_conf);
+
hws[IMX8MM_GPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_GPU_PLL);
hws[IMX8MM_VPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VPU_PLL);
hws[IMX8MM_ARM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_ARM_PLL);
--
2.43.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs
2025-01-18 12:39 [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Dario Binacchi
` (15 preceding siblings ...)
2025-01-18 12:40 ` [PATCH v9 23/23] clk: imx8mm: support spread spectrum clock generation Dario Binacchi
@ 2025-01-24 13:46 ` Krzysztof Kozlowski
2025-01-24 23:47 ` Peng Fan
16 siblings, 1 reply; 22+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-24 13:46 UTC (permalink / raw)
To: Dario Binacchi, linux-kernel
Cc: linux-amarula, Abel Vesa, Conor Dooley, Dan Carpenter,
Fabio Estevam, Krzysztof Kozlowski, Michael Turquette, Peng Fan,
Pengutronix Kernel Team, Rob Herring, Sascha Hauer, Shawn Guo,
Stephen Boyd, devicetree, imx, linux-arm-kernel, linux-clk
On 18/01/2025 13:39, Dario Binacchi wrote:
> The series adds support for spread spectrum clocking for i.MX8M{M,N,P}
> PLLs (audio, video and DRAM). It has been tested for the video PLL on
> boards using i.MX8MN and i.MX8MP.
>
> Changes in v9:
> - Add 'Reviewed-by' tag of Peng Fan for imx8mn platform patches
> - Fix building warning raised by the kernel test robot for patch
> v8, 11/18 clk: imx: add support for i.MX8MN anatop clock driver
> - Add patches for imx8m{m,p} platforms:
> - 23/23 clk: imx8mm: support spread spectrum clock generation
> - 22/23 clk: imx: add support for i.MX8MM anatop clock driver
> - 21/23 clk: imx8mp: support spread spectrum clock generation
> - 20/23 clk: imx8mp: rename ccm_base to base
> - 19/23 clk: imx: add support for i.MX8MP anatop clock driver
I responded in particular patch, but let's respond for formality to
cover letter as well.
The bindings here might get obsolete already with work:
https://github.com/devicetree-org/dt-schema/pull/154
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread* RE: [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs
2025-01-24 13:46 ` [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs Krzysztof Kozlowski
@ 2025-01-24 23:47 ` Peng Fan
2025-01-25 13:11 ` Dario Binacchi
0 siblings, 1 reply; 22+ messages in thread
From: Peng Fan @ 2025-01-24 23:47 UTC (permalink / raw)
To: Krzysztof Kozlowski, Dario Binacchi, linux-kernel@vger.kernel.org
Cc: linux-amarula@amarulasolutions.com, Abel Vesa, Conor Dooley,
Dan Carpenter, Fabio Estevam, Krzysztof Kozlowski,
Michael Turquette, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org
> Subject: Re: [PATCH v9 00/23] Support spread spectrum clocking for
> i.MX8M PLLs
>
> On 18/01/2025 13:39, Dario Binacchi wrote:
> > The series adds support for spread spectrum clocking for
> i.MX8M{M,N,P}
> > PLLs (audio, video and DRAM). It has been tested for the video PLL on
> > boards using i.MX8MN and i.MX8MP.
> >
> > Changes in v9:
> > - Add 'Reviewed-by' tag of Peng Fan for imx8mn platform patches
> > - Fix building warning raised by the kernel test robot for patch
> > v8, 11/18 clk: imx: add support for i.MX8MN anatop clock driver
> > - Add patches for imx8m{m,p} platforms:
> > - 23/23 clk: imx8mm: support spread spectrum clock generation
> > - 22/23 clk: imx: add support for i.MX8MM anatop clock driver
> > - 21/23 clk: imx8mp: support spread spectrum clock generation
> > - 20/23 clk: imx8mp: rename ccm_base to base
> > - 19/23 clk: imx: add support for i.MX8MP anatop clock driver
> I responded in particular patch, but let's respond for formality to cover
> letter as well.
Sorry to come into the binding part at so late stage. I just
got a request for i.MX95 SCMI CLK a few days ago which is impossible
for vendor specific properties.
But I am not sure "assigned-clock-sscs" is welcomed by maintainers.
Please also help to check whether this is usable for your patches
to enable SSC for i.MX8M PLL.
>
> The bindings here might get obsolete already with work:
> https://github.com/devicetree-org/dt-schema/pull/154
Not intend to waste to your effort.
I also replied in the PR to express my apologize.
Thanks,
Peng.
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v9 00/23] Support spread spectrum clocking for i.MX8M PLLs
2025-01-24 23:47 ` Peng Fan
@ 2025-01-25 13:11 ` Dario Binacchi
0 siblings, 0 replies; 22+ messages in thread
From: Dario Binacchi @ 2025-01-25 13:11 UTC (permalink / raw)
To: Peng Fan, Abel Vesa
Cc: Krzysztof Kozlowski, linux-kernel@vger.kernel.org,
linux-amarula@amarulasolutions.com, Conor Dooley, Dan Carpenter,
Fabio Estevam, Krzysztof Kozlowski, Michael Turquette,
Pengutronix Kernel Team, Rob Herring, Sascha Hauer, Shawn Guo,
Stephen Boyd, devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Hi Peng and Abel,
On Sat, Jan 25, 2025 at 12:47 AM Peng Fan <peng.fan@nxp.com> wrote:
>
> > Subject: Re: [PATCH v9 00/23] Support spread spectrum clocking for
> > i.MX8M PLLs
> >
> > On 18/01/2025 13:39, Dario Binacchi wrote:
> > > The series adds support for spread spectrum clocking for
> > i.MX8M{M,N,P}
> > > PLLs (audio, video and DRAM). It has been tested for the video PLL on
> > > boards using i.MX8MN and i.MX8MP.
> > >
> > > Changes in v9:
> > > - Add 'Reviewed-by' tag of Peng Fan for imx8mn platform patches
> > > - Fix building warning raised by the kernel test robot for patch
> > > v8, 11/18 clk: imx: add support for i.MX8MN anatop clock driver
> > > - Add patches for imx8m{m,p} platforms:
> > > - 23/23 clk: imx8mm: support spread spectrum clock generation
> > > - 22/23 clk: imx: add support for i.MX8MM anatop clock driver
> > > - 21/23 clk: imx8mp: support spread spectrum clock generation
> > > - 20/23 clk: imx8mp: rename ccm_base to base
> > > - 19/23 clk: imx: add support for i.MX8MP anatop clock driver
> > I responded in particular patch, but let's respond for formality to cover
> > letter as well.
>
> Sorry to come into the binding part at so late stage. I just
> got a request for i.MX95 SCMI CLK a few days ago which is impossible
> for vendor specific properties.
>
> But I am not sure "assigned-clock-sscs" is welcomed by maintainers.
> Please also help to check whether this is usable for your patches
> to enable SSC for i.MX8M PLL.
>
> >
> > The bindings here might get obsolete already with work:
> > https://github.com/devicetree-org/dt-schema/pull/154
>
> Not intend to waste to your effort.
> I also replied in the PR to express my apologize.
Please let me know clearly how you intend to proceed with this
series in light of Peng's series and PR. My team and I, along
with my company, have been working on this series for three months
now. We do not intend to stop, but we are requesting feedback from
the maintainer on the quality of the work and guidance on how to
address the next steps.
Thanks and regards,
Dario
>
> Thanks,
> Peng.
>
> >
> > Best regards,
> > Krzysztof
--
Dario Binacchi
Senior Embedded Linux Developer
dario.binacchi@amarulasolutions.com
__________________________________
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 22+ messages in thread