[PATCH v4 0/4] Multiplex sdmmc low jitter clock path

[PATCH v4 0/4] Multiplex sdmmc low jitter clock path

[Aapo Vienamo]

The SDMMC clocks have a Low Jitter (LJ) clock path which bypasses a
divider to achieve better jitter performance with high speed signaling
modes. The clock path with the divider is needed by some of the slower
signaling modes. This series automatically multiplexes the LJ and
non-LJ clock paths based on the requested frequency.

Changelog:
v4:
	- Add a changelog

v3:
	- Use <asm/div64.h> include instead of <linux/kernel.h> for
	  do_div()
	- Use SPDX tags for new files
	- Make mux_lj_idx[] and mux_non_lj_idx[] const
	- Make tegra_clk_sdmmc_mux_ops static
	- Fix the includes for fence_udelay() in a separate patch

v2:
	- Fix the type compatibility error on do_div

Aapo Vienamo (1):
  clk: tegra: Fix includes required by fence_udelay()

Peter De Schrijver (1):
  clk: tegra: refactor 7.1 div calculation

Peter De-Schrijver (2):
  clk: tegra: Add sdmmc mux divider clock
  clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks

 drivers/clk/tegra/Makefile           |   2 +
 drivers/clk/tegra/clk-divider.c      |  30 +----
 drivers/clk/tegra/clk-id.h           |   2 -
 drivers/clk/tegra/clk-sdmmc-mux.c    | 250 +++++++++++++++++++++++++++++++++++
 drivers/clk/tegra/clk-tegra-periph.c |  11 --
 drivers/clk/tegra/clk-tegra210.c     |  14 +-
 drivers/clk/tegra/clk.h              |  30 +++++
 drivers/clk/tegra/div71.c            |  43 ++++++
 8 files changed, 342 insertions(+), 40 deletions(-)
 create mode 100644 drivers/clk/tegra/clk-sdmmc-mux.c
 create mode 100644 drivers/clk/tegra/div71.c

-- 
2.7.4

[PATCH v4 1/4] clk: tegra: Fix includes required by fence_udelay()

[Aapo Vienamo]

Add the missing linux/delay.h include statement for udelay() used by
fence_udelay() macro.

Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
---
 drivers/clk/tegra/clk.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index e1f8846..e3b9c22 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -19,6 +19,7 @@
 
 #include <linux/clk-provider.h>
 #include <linux/clkdev.h>
+#include <linux/delay.h>
 
 /**
  * struct tegra_clk_sync_source - external clock source from codec
-- 
2.7.4

[PATCH v4 2/4] clk: tegra: refactor 7.1 div calculation

[Aapo Vienamo]

From: Peter De Schrijver <pdeschrijver@nvidia.com>

Move this to a separate file so it can be used to calculate the sdmmc
clock dividers.

Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/clk/tegra/Makefile      |  1 +
 drivers/clk/tegra/clk-divider.c | 30 +++++-----------------------
 drivers/clk/tegra/clk.h         |  3 +++
 drivers/clk/tegra/div71.c       | 43 +++++++++++++++++++++++++++++++++++++++++
 4 files changed, 52 insertions(+), 25 deletions(-)
 create mode 100644 drivers/clk/tegra/div71.c

diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index b716923..6d4f563 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_TEGRA_132_SOC)	+= clk-tegra124.o
 obj-y					+= cvb.o
 obj-$(CONFIG_ARCH_TEGRA_210_SOC)	+= clk-tegra210.o
 obj-$(CONFIG_CLK_TEGRA_BPMP)		+= clk-bpmp.o
+obj-y					+= div71.o
diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 16e0aee..ad87858 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -32,35 +32,15 @@
 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
 		   unsigned long parent_rate)
 {
-	u64 divider_ux1 = parent_rate;
-	u8 flags = divider->flags;
-	int mul;
-
-	if (!rate)
-		return 0;
-
-	mul = get_mul(divider);
-
-	if (!(flags & TEGRA_DIVIDER_INT))
-		divider_ux1 *= mul;
-
-	if (flags & TEGRA_DIVIDER_ROUND_UP)
-		divider_ux1 += rate - 1;
-
-	do_div(divider_ux1, rate);
-
-	if (flags & TEGRA_DIVIDER_INT)
-		divider_ux1 *= mul;
+	int div;
 
-	divider_ux1 -= mul;
+	div = div71_get(rate, parent_rate, divider->width, divider->frac_width,
+			divider->flags);
 
-	if ((s64)divider_ux1 < 0)
+	if (div < 0)
 		return 0;
 
-	if (divider_ux1 > get_max_div(divider))
-		return get_max_div(divider);
-
-	return divider_ux1;
+	return div;
 }
 
 static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index e3b9c22..149cc70 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -812,6 +812,9 @@ extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
+int div71_get(unsigned long rate, unsigned parent_rate, u8 width,
+	      u8 frac_width, u8 flags);
+
 
 /* Combined read fence with delay */
 #define fence_udelay(delay, reg)	\
diff --git a/drivers/clk/tegra/div71.c b/drivers/clk/tegra/div71.c
new file mode 100644
index 0000000..1eecc84
--- /dev/null
+++ b/drivers/clk/tegra/div71.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#include <asm/div64.h>
+
+#include "clk.h"
+
+#define div_mask(w) ((1 << (w)) - 1)
+
+int div71_get(unsigned long rate, unsigned parent_rate, u8 width,
+	      u8 frac_width, u8 flags)
+{
+	u64 divider_ux1 = parent_rate;
+	int mul;
+
+	if (!rate)
+		return 0;
+
+	mul = 1 << frac_width;
+
+	if (!(flags & TEGRA_DIVIDER_INT))
+		divider_ux1 *= mul;
+
+	if (flags & TEGRA_DIVIDER_ROUND_UP)
+		divider_ux1 += rate - 1;
+
+	do_div(divider_ux1, rate);
+
+	if (flags & TEGRA_DIVIDER_INT)
+		divider_ux1 *= mul;
+
+	if (divider_ux1 < mul)
+		return 0;
+
+	divider_ux1 -= mul;
+
+	if (divider_ux1 > div_mask(width))
+		return div_mask(width);
+
+	return divider_ux1;
+}
-- 
2.7.4

Re: [PATCH v4 2/4] clk: tegra: refactor 7.1 div calculation

[Jon Hunter]

On 09/07/18 17:38, Aapo Vienamo wrote:
> From: Peter De Schrijver <pdeschrijver@nvidia.com>
> 
> Move this to a separate file so it can be used to calculate the sdmmc
> clock dividers.

Sorry for not commenting sooner, but what is the motivation for moving
this to its own file? I don't see why we need to do this in order to use
elsewhere. Furthermore, the original file is quite aptly named 'clk-divider.c'
and now we have a div71.c which seems quite specific.
> Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
>  drivers/clk/tegra/Makefile      |  1 +
>  drivers/clk/tegra/clk-divider.c | 30 +++++-----------------------
>  drivers/clk/tegra/clk.h         |  3 +++
>  drivers/clk/tegra/div71.c       | 43 +++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 52 insertions(+), 25 deletions(-)
>  create mode 100644 drivers/clk/tegra/div71.c
> 
> diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
> index b716923..6d4f563 100644
> --- a/drivers/clk/tegra/Makefile
> +++ b/drivers/clk/tegra/Makefile
> @@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_TEGRA_132_SOC)	+= clk-tegra124.o
>  obj-y					+= cvb.o
>  obj-$(CONFIG_ARCH_TEGRA_210_SOC)	+= clk-tegra210.o
>  obj-$(CONFIG_CLK_TEGRA_BPMP)		+= clk-bpmp.o
> +obj-y					+= div71.o
> diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
> index 16e0aee..ad87858 100644
> --- a/drivers/clk/tegra/clk-divider.c
> +++ b/drivers/clk/tegra/clk-divider.c
> @@ -32,35 +32,15 @@
>  static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
>  		   unsigned long parent_rate)
>  {
> -	u64 divider_ux1 = parent_rate;
> -	u8 flags = divider->flags;
> -	int mul;
> -
> -	if (!rate)
> -		return 0;
> -
> -	mul = get_mul(divider);
> -
> -	if (!(flags & TEGRA_DIVIDER_INT))
> -		divider_ux1 *= mul;
> -
> -	if (flags & TEGRA_DIVIDER_ROUND_UP)
> -		divider_ux1 += rate - 1;
> -
> -	do_div(divider_ux1, rate);
> -
> -	if (flags & TEGRA_DIVIDER_INT)
> -		divider_ux1 *= mul;
> +	int div;
>  
> -	divider_ux1 -= mul;
> +	div = div71_get(rate, parent_rate, divider->width, divider->frac_width,
> +			divider->flags);
>  
> -	if ((s64)divider_ux1 < 0)
> +	if (div < 0)
>  		return 0;
>  
> -	if (divider_ux1 > get_max_div(divider))
> -		return get_max_div(divider);
> -
> -	return divider_ux1;
> +	return div;
>  }
>  
>  static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index e3b9c22..149cc70 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -812,6 +812,9 @@ extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
>  int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
>  u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
>  int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
> +int div71_get(unsigned long rate, unsigned parent_rate, u8 width,
> +	      u8 frac_width, u8 flags);
> +
>  
>  /* Combined read fence with delay */
>  #define fence_udelay(delay, reg)	\
> diff --git a/drivers/clk/tegra/div71.c b/drivers/clk/tegra/div71.c
> new file mode 100644
> index 0000000..1eecc84
> --- /dev/null
> +++ b/drivers/clk/tegra/div71.c
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
> + */
> +
> +#include <asm/div64.h>
> +
> +#include "clk.h"
> +
> +#define div_mask(w) ((1 << (w)) - 1)
> +
> +int div71_get(unsigned long rate, unsigned parent_rate, u8 width,
> +	      u8 frac_width, u8 flags)
> +{
> +	u64 divider_ux1 = parent_rate;
> +	int mul;
> +
> +	if (!rate)
> +		return 0;
> +
> +	mul = 1 << frac_width;
> +
> +	if (!(flags & TEGRA_DIVIDER_INT))
> +		divider_ux1 *= mul;
> +
> +	if (flags & TEGRA_DIVIDER_ROUND_UP)
> +		divider_ux1 += rate - 1;
> +
> +	do_div(divider_ux1, rate);
> +
> +	if (flags & TEGRA_DIVIDER_INT)
> +		divider_ux1 *= mul;
> +
> +	if (divider_ux1 < mul)
> +		return 0;
> +
> +	divider_ux1 -= mul;
> +
> +	if (divider_ux1 > div_mask(width))
> +		return div_mask(width);
> +
> +	return divider_ux1;
> +}

I don't see anything in the above that makes this 7.1? It seems that the
fractional width is being passed meaning it could be m.n unless I am missing
something.

Cheers
Jon

-- 
nvpublic

Re: [PATCH v4 2/4] clk: tegra: refactor 7.1 div calculation

[Peter De Schrijver]

On Tue, Jul 10, 2018 at 05:17:05PM +0100, Jon Hunter wrote:
> 
> On 09/07/18 17:38, Aapo Vienamo wrote:
> > From: Peter De Schrijver <pdeschrijver@nvidia.com>
> > 
> > Move this to a separate file so it can be used to calculate the sdmmc
> > clock dividers.
> 
> Sorry for not commenting sooner, but what is the motivation for moving
> this to its own file? I don't see why we need to do this in order to use
> elsewhere. Furthermore, the original file is quite aptly named 'clk-divider.c'
> and now we have a div71.c which seems quite specific.

How else would you do it?

Peter.

> > Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
> > Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> > Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> > ---
> >  drivers/clk/tegra/Makefile      |  1 +
> >  drivers/clk/tegra/clk-divider.c | 30 +++++-----------------------
> >  drivers/clk/tegra/clk.h         |  3 +++
> >  drivers/clk/tegra/div71.c       | 43 +++++++++++++++++++++++++++++++++++++++++
> >  4 files changed, 52 insertions(+), 25 deletions(-)
> >  create mode 100644 drivers/clk/tegra/div71.c
> > 
> > diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
> > index b716923..6d4f563 100644
> > --- a/drivers/clk/tegra/Makefile
> > +++ b/drivers/clk/tegra/Makefile
> > @@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_TEGRA_132_SOC)	+= clk-tegra124.o
> >  obj-y					+= cvb.o
> >  obj-$(CONFIG_ARCH_TEGRA_210_SOC)	+= clk-tegra210.o
> >  obj-$(CONFIG_CLK_TEGRA_BPMP)		+= clk-bpmp.o
> > +obj-y					+= div71.o
> > diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
> > index 16e0aee..ad87858 100644
> > --- a/drivers/clk/tegra/clk-divider.c
> > +++ b/drivers/clk/tegra/clk-divider.c
> > @@ -32,35 +32,15 @@
> >  static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
> >  		   unsigned long parent_rate)
> >  {
> > -	u64 divider_ux1 = parent_rate;
> > -	u8 flags = divider->flags;
> > -	int mul;
> > -
> > -	if (!rate)
> > -		return 0;
> > -
> > -	mul = get_mul(divider);
> > -
> > -	if (!(flags & TEGRA_DIVIDER_INT))
> > -		divider_ux1 *= mul;
> > -
> > -	if (flags & TEGRA_DIVIDER_ROUND_UP)
> > -		divider_ux1 += rate - 1;
> > -
> > -	do_div(divider_ux1, rate);
> > -
> > -	if (flags & TEGRA_DIVIDER_INT)
> > -		divider_ux1 *= mul;
> > +	int div;
> >  
> > -	divider_ux1 -= mul;
> > +	div = div71_get(rate, parent_rate, divider->width, divider->frac_width,
> > +			divider->flags);
> >  
> > -	if ((s64)divider_ux1 < 0)
> > +	if (div < 0)
> >  		return 0;
> >  
> > -	if (divider_ux1 > get_max_div(divider))
> > -		return get_max_div(divider);
> > -
> > -	return divider_ux1;
> > +	return div;
> >  }
> >  
> >  static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
> > diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> > index e3b9c22..149cc70 100644
> > --- a/drivers/clk/tegra/clk.h
> > +++ b/drivers/clk/tegra/clk.h
> > @@ -812,6 +812,9 @@ extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
> >  int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
> >  u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
> >  int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
> > +int div71_get(unsigned long rate, unsigned parent_rate, u8 width,
> > +	      u8 frac_width, u8 flags);
> > +
> >  
> >  /* Combined read fence with delay */
> >  #define fence_udelay(delay, reg)	\
> > diff --git a/drivers/clk/tegra/div71.c b/drivers/clk/tegra/div71.c
> > new file mode 100644
> > index 0000000..1eecc84
> > --- /dev/null
> > +++ b/drivers/clk/tegra/div71.c
> > @@ -0,0 +1,43 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
> > + */
> > +
> > +#include <asm/div64.h>
> > +
> > +#include "clk.h"
> > +
> > +#define div_mask(w) ((1 << (w)) - 1)
> > +
> > +int div71_get(unsigned long rate, unsigned parent_rate, u8 width,
> > +	      u8 frac_width, u8 flags)
> > +{
> > +	u64 divider_ux1 = parent_rate;
> > +	int mul;
> > +
> > +	if (!rate)
> > +		return 0;
> > +
> > +	mul = 1 << frac_width;
> > +
> > +	if (!(flags & TEGRA_DIVIDER_INT))
> > +		divider_ux1 *= mul;
> > +
> > +	if (flags & TEGRA_DIVIDER_ROUND_UP)
> > +		divider_ux1 += rate - 1;
> > +
> > +	do_div(divider_ux1, rate);
> > +
> > +	if (flags & TEGRA_DIVIDER_INT)
> > +		divider_ux1 *= mul;
> > +
> > +	if (divider_ux1 < mul)
> > +		return 0;
> > +
> > +	divider_ux1 -= mul;
> > +
> > +	if (divider_ux1 > div_mask(width))
> > +		return div_mask(width);
> > +
> > +	return divider_ux1;
> > +}
> 
> I don't see anything in the above that makes this 7.1? It seems that the
> fractional width is being passed meaning it could be m.n unless I am missing
> something.
> 
> Cheers
> Jon
> 
> -- 
> nvpublic
> --
> To unsubscribe from this list: send the line "unsubscribe linux-clk" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v4 2/4] clk: tegra: refactor 7.1 div calculation

[Jon Hunter]

On 11/07/18 09:00, Peter De Schrijver wrote:
> On Tue, Jul 10, 2018 at 05:17:05PM +0100, Jon Hunter wrote:
>>
>> On 09/07/18 17:38, Aapo Vienamo wrote:
>>> From: Peter De Schrijver <pdeschrijver@nvidia.com>
>>>
>>> Move this to a separate file so it can be used to calculate the sdmmc
>>> clock dividers.
>>
>> Sorry for not commenting sooner, but what is the motivation for moving
>> this to its own file? I don't see why we need to do this in order to use
>> elsewhere. Furthermore, the original file is quite aptly named 'clk-divider.c'
>> and now we have a div71.c which seems quite specific.
> 
> How else would you do it?

Keep it in the same file?

Jon
 -- 
nvpublic

Re: [PATCH v4 2/4] clk: tegra: refactor 7.1 div calculation

[Peter De Schrijver]

On Wed, Jul 11, 2018 at 09:42:20AM +0100, Jon Hunter wrote:
> 
> On 11/07/18 09:00, Peter De Schrijver wrote:
> > On Tue, Jul 10, 2018 at 05:17:05PM +0100, Jon Hunter wrote:
> >>
> >> On 09/07/18 17:38, Aapo Vienamo wrote:
> >>> From: Peter De Schrijver <pdeschrijver@nvidia.com>
> >>>
> >>> Move this to a separate file so it can be used to calculate the sdmmc
> >>> clock dividers.
> >>
> >> Sorry for not commenting sooner, but what is the motivation for moving
> >> this to its own file? I don't see why we need to do this in order to use
> >> elsewhere. Furthermore, the original file is quite aptly named 'clk-divider.c'
> >> and now we have a div71.c which seems quite specific.
> > 
> > How else would you do it?
> 
> Keep it in the same file?
> 

That seems odd. clk-divider.c is meant to implement a clock type, not
utility functions we happen to need in several types.

Peter.

Re: [PATCH v4 2/4] clk: tegra: refactor 7.1 div calculation

[Jon Hunter]

On 11/07/18 12:17, Peter De Schrijver wrote:
> On Wed, Jul 11, 2018 at 09:42:20AM +0100, Jon Hunter wrote:
>>
>> On 11/07/18 09:00, Peter De Schrijver wrote:
>>> On Tue, Jul 10, 2018 at 05:17:05PM +0100, Jon Hunter wrote:
>>>>
>>>> On 09/07/18 17:38, Aapo Vienamo wrote:
>>>>> From: Peter De Schrijver <pdeschrijver@nvidia.com>
>>>>>
>>>>> Move this to a separate file so it can be used to calculate the sdmmc
>>>>> clock dividers.
>>>>
>>>> Sorry for not commenting sooner, but what is the motivation for moving
>>>> this to its own file? I don't see why we need to do this in order to use
>>>> elsewhere. Furthermore, the original file is quite aptly named 'clk-divider.c'
>>>> and now we have a div71.c which seems quite specific.
>>>
>>> How else would you do it?
>>
>> Keep it in the same file?
>>
> 
> That seems odd. clk-divider.c is meant to implement a clock type, not
> utility functions we happen to need in several types.

I see, then why not have a clk-utils.c for stuff like this. I am painting
the bikeshed here, but div71.c seems very specific and I still don't
understand the 7.1 bit.

Cheers
Jon

-- 
nvpublic

Re: [PATCH v4 2/4] clk: tegra: refactor 7.1 div calculation

[Aapo Vienamo]

On Wed, 11 Jul 2018 16:14:13 +0100
Jon Hunter <jonathanh@nvidia.com> wrote:

> On 11/07/18 12:17, Peter De Schrijver wrote:
> > On Wed, Jul 11, 2018 at 09:42:20AM +0100, Jon Hunter wrote:  
> >>
> >> On 11/07/18 09:00, Peter De Schrijver wrote:  
> >>> On Tue, Jul 10, 2018 at 05:17:05PM +0100, Jon Hunter wrote:  
> >>>>
> >>>> On 09/07/18 17:38, Aapo Vienamo wrote:  
> >>>>> From: Peter De Schrijver <pdeschrijver@nvidia.com>
> >>>>>
> >>>>> Move this to a separate file so it can be used to calculate the sdmmc
> >>>>> clock dividers.  
> >>>>
> >>>> Sorry for not commenting sooner, but what is the motivation for moving
> >>>> this to its own file? I don't see why we need to do this in order to use
> >>>> elsewhere. Furthermore, the original file is quite aptly named 'clk-divider.c'
> >>>> and now we have a div71.c which seems quite specific.  
> >>>
> >>> How else would you do it?  
> >>
> >> Keep it in the same file?
> >>  
> > 
> > That seems odd. clk-divider.c is meant to implement a clock type, not
> > utility functions we happen to need in several types.  
> 
> I see, then why not have a clk-utils.c for stuff like this. I am painting
> the bikeshed here, but div71.c seems very specific and I still don't
> understand the 7.1 bit.

While the code could work with other dividers, it was called 7.1 because
the current usecases were only on 7.1 dividers. I can submit another
version with a different filename if other changes to the series come
about or if it's seen necessary to change div-frac.c from the latest
version of the series to something else.

 -Aapo

[PATCH v4 4/4] clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks

[Aapo Vienamo]

From: Peter De-Schrijver <pdeschrijver@nvidia.com>

These clocks have low jitter paths to certain parents. To model these
correctly, use the sdmmc mux divider clock type.

Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/clk/tegra/clk-id.h           |  2 --
 drivers/clk/tegra/clk-tegra-periph.c | 11 -----------
 drivers/clk/tegra/clk-tegra210.c     | 14 ++++++++++++--
 3 files changed, 12 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index b616e33..de466b4 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -227,13 +227,11 @@ enum clk_id {
 	tegra_clk_sdmmc1_9,
 	tegra_clk_sdmmc2,
 	tegra_clk_sdmmc2_8,
-	tegra_clk_sdmmc2_9,
 	tegra_clk_sdmmc3,
 	tegra_clk_sdmmc3_8,
 	tegra_clk_sdmmc3_9,
 	tegra_clk_sdmmc4,
 	tegra_clk_sdmmc4_8,
-	tegra_clk_sdmmc4_9,
 	tegra_clk_se,
 	tegra_clk_soc_therm,
 	tegra_clk_soc_therm_8,
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 2acba29..38c4eb2 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -451,15 +451,6 @@ static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
 	[0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7,
 };
 
-static const char *mux_pllp_clkm_pllc4_out2_out1_out0_lj[] = {
-	"pll_p",
-	"pll_c4_out2", "pll_c4_out0",	/* LJ input */
-	"pll_c4_out2", "pll_c4_out1",
-	"pll_c4_out1",			/* LJ input */
-	"clk_m", "pll_c4_out0"
-};
-#define mux_pllp_clkm_pllc4_out2_out1_out0_lj_idx NULL
-
 static const char *mux_pllp_pllc2_c_c3_clkm[] = {
 	"pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m"
 };
@@ -686,9 +677,7 @@ static struct tegra_periph_init_data periph_clks[] = {
 	MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
 	MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
 	MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9),
-	MUX8("sdmmc2", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_9),
 	MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9),
-	MUX8("sdmmc4", mux_pllp_clkm_pllc4_out2_out1_out0_lj, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_9),
 	MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
 	MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
 	MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 5435d01..9eb1cb1 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -44,6 +44,8 @@
 #define CLK_SOURCE_EMC 0x19c
 #define CLK_SOURCE_SOR1 0x410
 #define CLK_SOURCE_LA 0x1f8
+#define CLK_SOURCE_SDMMC2 0x154
+#define CLK_SOURCE_SDMMC4 0x164
 
 #define PLLC_BASE 0x80
 #define PLLC_OUT 0x84
@@ -2286,11 +2288,9 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
 	[tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
 	[tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
-	[tegra_clk_sdmmc2_9] = { .dt_id = TEGRA210_CLK_SDMMC2, .present = true },
 	[tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
 	[tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
 	[tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
-	[tegra_clk_sdmmc4_9] = { .dt_id = TEGRA210_CLK_SDMMC4, .present = true },
 	[tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
 	[tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
 	[tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
@@ -3030,6 +3030,16 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
 				0, NULL);
 	clks[TEGRA210_CLK_ACLK] = clk;
 
+	clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
+					    CLK_SOURCE_SDMMC2, 9,
+					    TEGRA_DIVIDER_ROUND_UP, 0, NULL);
+	clks[TEGRA210_CLK_SDMMC2] = clk;
+
+	clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
+					    CLK_SOURCE_SDMMC4, 15,
+					    TEGRA_DIVIDER_ROUND_UP, 0, NULL);
+	clks[TEGRA210_CLK_SDMMC4] = clk;
+
 	for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) {
 		struct tegra_periph_init_data *init = &tegra210_periph[i];
 		struct clk **clkp;
-- 
2.7.4

Re: [PATCH v4 0/4] Multiplex sdmmc low jitter clock path

[Peter De Schrijver]

Series Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>

Peter.

On Mon, Jul 09, 2018 at 07:38:54PM +0300, Aapo Vienamo wrote:
> The SDMMC clocks have a Low Jitter (LJ) clock path which bypasses a
> divider to achieve better jitter performance with high speed signaling
> modes. The clock path with the divider is needed by some of the slower
> signaling modes. This series automatically multiplexes the LJ and
> non-LJ clock paths based on the requested frequency.
> 
> Changelog:
> v4:
> 	- Add a changelog
> 
> v3:
> 	- Use <asm/div64.h> include instead of <linux/kernel.h> for
> 	  do_div()
> 	- Use SPDX tags for new files
> 	- Make mux_lj_idx[] and mux_non_lj_idx[] const
> 	- Make tegra_clk_sdmmc_mux_ops static
> 	- Fix the includes for fence_udelay() in a separate patch
> 
> v2:
> 	- Fix the type compatibility error on do_div
> 
> Aapo Vienamo (1):
>   clk: tegra: Fix includes required by fence_udelay()
> 
> Peter De Schrijver (1):
>   clk: tegra: refactor 7.1 div calculation
> 
> Peter De-Schrijver (2):
>   clk: tegra: Add sdmmc mux divider clock
>   clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks
> 
>  drivers/clk/tegra/Makefile           |   2 +
>  drivers/clk/tegra/clk-divider.c      |  30 +----
>  drivers/clk/tegra/clk-id.h           |   2 -
>  drivers/clk/tegra/clk-sdmmc-mux.c    | 250 +++++++++++++++++++++++++++++++++++
>  drivers/clk/tegra/clk-tegra-periph.c |  11 --
>  drivers/clk/tegra/clk-tegra210.c     |  14 +-
>  drivers/clk/tegra/clk.h              |  30 +++++
>  drivers/clk/tegra/div71.c            |  43 ++++++
>  8 files changed, 342 insertions(+), 40 deletions(-)
>  create mode 100644 drivers/clk/tegra/clk-sdmmc-mux.c
>  create mode 100644 drivers/clk/tegra/div71.c
> 
> -- 
> 2.7.4
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-clk" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html