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From: Xu Yilun <yilun.xu@linux.intel.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: linux-pci@vger.kernel.org, linux-coco@lists.linux.dev,
	gregkh@linuxfoundation.org, aik@amd.com, aneesh.kumar@kernel.org,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: Re: [PATCH v8 2/9] PCI/IDE: Enumerate Selective Stream IDE capabilities
Date: Sun, 9 Nov 2025 00:15:47 +0800	[thread overview]
Message-ID: <aQ9ss3oK7ds4Srd9@yilunxu-OptiPlex-7050> (raw)
In-Reply-To: <20251031212902.2256310-3-dan.j.williams@intel.com>

On Fri, Oct 31, 2025 at 02:28:54PM -0700, Dan Williams wrote:
> Link encryption is a new PCIe feature enumerated by "PCIe r7.0 section
> 7.9.26 IDE Extended Capability".
> 
> It is both a standalone port + endpoint capability, and a building block
> for the security protocol defined by "PCIe r7.0 section 11 TEE Device
> Interface Security Protocol (TDISP)". That protocol coordinates device
> security setup between a platform TSM (TEE Security Manager) and a
> device DSM (Device Security Manager). While the platform TSM can
> allocate resources like Stream ID and manage keys, it still requires
> system software to manage the IDE capability register block.
> 
> Add register definitions and basic enumeration in preparation for
> Selective IDE Stream establishment. A follow on change selects the new
> CONFIG_PCI_IDE symbol. Note that while the IDE specification defines
> both a point-to-point "Link Stream" and a Root Port to endpoint
> "Selective Stream", only "Selective Stream" is considered for Linux as
> that is the predominant mode expected by Trusted Execution Environment
> Security Managers (TSMs), and it is the security model that limits the
> number of PCI components within the TCB in a PCIe topology with
> switches.
> 
> Co-developed-by: Alexey Kardashevskiy <aik@amd.com>
> Signed-off-by: Alexey Kardashevskiy <aik@amd.com>
> Co-developed-by: Xu Yilun <yilun.xu@linux.intel.com>
> Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Alexey Kardashevskiy <aik@amd.com>
> Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@kernel.org>

Reviewed-by: Xu Yilun <yilun.xu@linux.intel.com>

> Signed-off-by: Dan Williams <dan.j.williams@intel.com>

  reply	other threads:[~2025-11-08 16:30 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-31 21:28 [PATCH v8 0/9] PCI/TSM: Core infrastructure for PCI device security (TDISP) Dan Williams
2025-10-31 21:28 ` [PATCH v8 1/9] coco/tsm: Introduce a core device for TEE Security Managers Dan Williams
2025-11-08 15:45   ` Xu Yilun
2025-10-31 21:28 ` [PATCH v8 2/9] PCI/IDE: Enumerate Selective Stream IDE capabilities Dan Williams
2025-11-08 16:15   ` Xu Yilun [this message]
2025-10-31 21:28 ` [PATCH v8 3/9] PCI: Introduce pci_walk_bus_reverse(), for_each_pci_dev_reverse() Dan Williams
2025-10-31 21:28 ` [PATCH v8 4/9] PCI/TSM: Establish Secure Sessions and Link Encryption Dan Williams
2025-11-10  3:44   ` Xu Yilun
2025-11-10 23:19     ` dan.j.williams
2025-10-31 21:28 ` [PATCH v8 5/9] PCI: Add PCIe Device 3 Extended Capability enumeration Dan Williams
2025-11-10  3:45   ` Xu Yilun
2025-10-31 21:28 ` [PATCH v8 6/9] PCI: Establish document for PCI host bridge sysfs attributes Dan Williams
2025-10-31 21:28 ` [PATCH v8 7/9] PCI/IDE: Add IDE establishment helpers Dan Williams
2025-11-03 15:04   ` Jonathan Cameron
2025-11-10  4:16   ` Xu Yilun
2025-11-10 23:21     ` dan.j.williams
2025-10-31 21:29 ` [PATCH v8 8/9] PCI/IDE: Report available IDE streams Dan Williams
2025-11-10  4:49   ` Xu Yilun
2025-11-10 23:49     ` dan.j.williams
2025-10-31 21:29 ` [PATCH v8 9/9] PCI/TSM: Report active " Dan Williams
2025-11-10  4:52   ` Xu Yilun

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